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November 1988  
Revised March 2005  
74AC541 • 74ACT541  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
The 74AC541 and 74ACT541 are octal buffer/line drivers  
designed to be employed as memory and address drivers,  
clock drivers and bus oriented transmitter/receivers.  
Features  
■ ICC and IOZ reduced by 50%  
■ 3-STATE outputs  
■ Inputs and outputs opposite side of package, allowing  
easier interface to microprocessors  
These devices are similar in function to the 74AC244 and  
74ACTC244 while providing flow-through architecture  
(inputs on opposite side from outputs). This pinout arrange-  
ment makes these devices especially useful as an output  
port for microprocessors, allowing ease of layout and  
greater PC board density.  
■ Output source/sink 24 mA  
■ 74AC541 is a non-inverting option of the 74AC540  
■ 74ACT541 has TTL-compatible inputs  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74AC541SC  
74AC541SJ  
74AC541MTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MTC20  
MTC20  
74AC541MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74AC541PC  
N20A  
M20B  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74ACT541SC  
74ACT541MTC  
MTC20  
MTC20  
74ACT541MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74ACT541PC  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDED J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS009967  
www.fairchildsemi.com  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Table  
Inputs  
OE2  
Outputs  
I
OE1  
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
Z
H
HIGH Voltage Level  
X
Immaterial  
L
LOW Voltage Level  
High Impedance  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
DC Input Diode Current (IIK  
VI 0.5V  
)
0.5V to 7.0V  
)
Supply Voltage (VCC  
AC  
)
20 mA  
20 mA  
2.0V to 6.0V  
4.5V to 5.5V  
0V to VCC  
VI VCC 0.5V  
ACT  
DC Input Voltage (VI)  
0.5V to VCC 0.5V  
Input Voltage (VI)  
Output Voltage (VO)  
DC Output Diode Current (IOK  
VO 0.5V  
)
0V to VCC  
20 mA  
20 mA  
Operating Temperature (TA)  
Minimum Input Edge Rate ( V/ t)  
AC: VIN from 30% to 70% of VCC  
VCC @ 3.3V, 4.5V, 5.5V  
40 C to 85 C  
125 mV/ns  
VO VCC 0.5V  
DC Output Voltage (VO)  
DC Output Source  
0.5V to VCC 0.5V  
or Sink Current (IO)  
50 mA  
ACT:VIN from 0.8V to 2.0V  
VCC @ 4.5V, 5.5V  
DC VCC or Ground Current  
per Output Pin (ICC or IGND  
)
50 mA  
Note 2: Absolute maximum ratings are those values beyond which dam-  
age to the device may occur. The databook specifications should be met,  
without exception, to ensure that the system design is reliable over its  
power supply, temperature, and output/input loading variables. Fairchild  
does not recommend operation of FACT circuits outside databook specifi-  
cations.  
Storage Temperature (TSTG  
Junction Temperature (TJ)  
PDIP  
)
65 C to 150 C  
140 C  
DC Electrical Characteristics for AC  
V
T
25 C  
T
A
40 C to 85 C  
CC  
A
Symbol  
Parameter  
Units  
Conditions  
(V)  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
Typ  
1.5  
Guaranteed Limits  
V
V
V
Minimum HIGH Level  
2.1  
2.1  
V
0.1V  
IH  
OUT  
Input Voltage  
2.25  
2.75  
1.5  
3.15  
3.85  
0.9  
3.15  
3.85  
0.9  
V
or V  
0.1V  
CC  
Maximum LOW Level  
Input Voltage  
V
0.1V  
0.1V  
IL  
OUT  
2.25  
2.75  
2.99  
4.49  
5.49  
1.35  
1.65  
2.9  
1.35  
1.65  
2.9  
V
V
or V  
CC  
Minimum HIGH Level  
Output Voltage  
OH  
4.4  
4.4  
I
50 A  
OUT  
5.4  
5.4  
V
V or V  
IL IH  
IN  
OH  
OH  
OH  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
2.56  
3.86  
4.86  
0.1  
2.46  
3.76  
4.76  
0.1  
I
I
I
12 mA  
24 mA  
V
V
V
24 mA (Note 3)  
V
Maximum LOW Level  
Output Voltage  
0.002  
0.001  
0.001  
OL  
0.1  
0.1  
I
50  
A
OUT  
0.1  
0.1  
V
V
or V  
IH  
IN  
OL  
OL  
OL  
IL  
3.0  
4.5  
5.5  
5.5  
0.36  
0.36  
0.36  
0.1  
0.44  
0.44  
0.44  
1.0  
I
I
I
12 mA  
24 mA  
24 mA (Note 3)  
V , GND  
CC  
I
I
(Note 5) Maximum Input Leakage Current  
Maximum 3-STATE  
A
A
V
IN  
I
V (OE)  
V , V  
IL IH  
OZ  
I
Leakage Current  
5.5  
0.25  
2.5  
V
V
V
V
V
V
, GND  
I
CC  
V
, GND  
O
CC  
I
I
I
Minimum Dynamic  
5.5  
5.5  
5.5  
75  
75  
mA  
mA  
A
1.65V Max  
3.85V Min  
OLD  
OHD  
OLD  
Output Current (Note 4)  
OHD  
IN  
(Note 5) Maximum Quiescent Supply Current  
4.0  
40.0  
V
or GND  
CC  
CC  
Note 3: All outputs loaded; thresholds on input associated with output under test.  
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.  
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .  
CC  
IN  
CC  
3
www.fairchildsemi.com  
AC Electrical Characteristics for AC  
V
T
25 C  
T
40 C to 85 C  
50 pF  
Min Max  
CC  
A
A
C
50 pF  
C
L
Symbol  
Parameter  
(V)  
(Note 6)  
3.3  
Units  
L
Min  
2.0  
1.5  
2.0  
1.5  
3.0  
2.0  
2.5  
1.5  
3.5  
2.0  
2.5  
2.0  
Typ  
Max  
8.0  
t
t
t
t
t
t
Propagation Delay  
5.5  
4.0  
5.5  
4.0  
8.0  
6.0  
7.0  
5.5  
9.0  
7.0  
6.5  
5.5  
1.5  
1.0  
1.5  
1.0  
3.0  
1.5  
2.5  
1.0  
2.5  
1.0  
2.0  
1.0  
9.0  
6.5  
PLH  
ns  
ns  
ns  
ns  
ns  
ns  
Data to Output  
5.0  
6.0  
Propagation Delay  
Data to Output  
3.3  
8.0  
8.5  
PHL  
PZH  
PZL  
PHZ  
PLZ  
5.0  
6.0  
6.5  
Output Enable Time  
3.3  
11.5  
8.5  
12.5  
9.5  
5.0  
Output Enable Time  
Output Disable Time  
Output Disable Time  
3.3  
10.0  
7.5  
11.5  
8.5  
5.0  
3.3  
12.5  
9.5  
14.0  
10.5  
10.5  
8.5  
5.0  
3.3  
9.5  
5.0  
7.5  
Note 6: Voltage Range 3.3 is 3.3V 0.3V  
Voltage Range 5.0 is 5.0V 0.5V  
DC Electrical Characteristics for ACT  
V
T
25 C  
T
A
40 C to 85 C  
CC  
A
Symbol  
Parameter  
Units  
Conditions  
(V)  
4.5  
5.5  
4.5  
5.5  
3.0  
4.5  
4.5  
5.5  
Typ  
1.5  
1.5  
1.5  
1.5  
Guaranteed Limits  
V
V
V
Minimum HIGH Level  
Input Voltage  
2.0  
2.0  
2.0  
V
0.1V  
0.1V  
0.1V  
0.1V  
50  
IH  
OUT  
V
V
V
2.0  
0.8  
or V  
CC  
Maximum LOW Level  
Input Voltage  
0.8  
V
IL  
OUT  
0.8  
0.8  
or V  
CC  
Minimum HIGH Level  
Output Voltage  
2.99  
4.49  
2.9  
2.9  
I
A
OH  
OUT  
4.4  
4.4  
3.86  
4.86  
3.76  
4.76  
V
V or V  
IL IH  
IN  
OH  
OH  
V
V
I
I
I
24 mA  
24 mA (Note 7)  
V
Maximum LOW Level  
Output Voltage  
3.0  
4.5  
4.5  
5.5  
0.002  
0.001  
0.1  
0.1  
0.1  
0.1  
50  
A
OL  
OUT  
0.36  
0.36  
0.44  
0.44  
V
V
or V  
IH  
IN  
OH  
OH  
IL  
V
A
I
I
24 mA  
24 mA (Note 7)  
I
I
Maximum Input  
5.5  
5.5  
0.1  
1.0  
2.5  
V
V
V
V
, GND  
IN  
I
CC  
Leakage Current  
Maximum 3-STATE  
Leakage Current  
0.25  
V
V
V
V
V
V
, V  
OZ  
I
IL  
IH  
A
V
, GND  
O
I
CC  
I
I
I
I
Maximum I /Input  
CC  
5.5  
5.5  
5.5  
5.5  
0.6  
1.5  
75  
mA  
mA  
mA  
A
2.1V  
CCT  
OLD  
OHD  
CC  
CC  
Minimum Dynamic  
Output Current (Note 8)  
Maximum Quiescent  
Supply Current  
1.65V Max  
3.85V Min  
OLD  
OHD  
IN  
75  
4.0  
40.0  
V
or GND  
CC  
Note 7: All outputs loaded; thresholds on input associated with output under test.  
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.  
www.fairchildsemi.com  
4
AC Electrical Characteristics for ACT  
V
T
25 C  
T
40 C to 85 C  
50 pF  
Min Max  
CC  
A
A
C
50 pF  
C
L
Symbol  
Parameter  
(V)  
Units  
L
(Note 9)  
Min  
2.0  
2.0  
2.0  
2.0  
1.5  
1.5  
Typ  
Max  
7.0  
7.0  
9.0  
9.0  
7.5  
7.5  
t
t
t
t
t
t
Propagation Delay  
4.5  
5.5  
5.0  
6.5  
5.5  
5.5  
2.0  
2.0  
2.0  
2.0  
1.5  
1.5  
7.5  
7.5  
9.5  
9.5  
8.0  
8.0  
PLH  
5.0  
5.0  
5.0  
ns  
ns  
ns  
Data to Output  
PHL  
PZH  
PZL  
PHZ  
PLZ  
Output Enable Time  
Output Disable Time  
Note 9: Voltage Range 5.0 is 5.0V 0.5V  
Capacitance  
Symbol  
Parameter  
Input Capacitance  
Typ  
Units  
Conditions  
C
C
4.5  
pF  
V
OPEN  
5.0V  
IN  
CC  
Power Dissipation Capacitance for AC  
Power Dissipation Capacitance for ACT  
30.0  
70.0  
PD  
pF  
V
CC  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Package Number N20A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
9
www.fairchildsemi.com