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May 1992  
Revised March 2005  
74ABT244  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
The ABT244 is an octal buffer and line driver with 3-STATE  
Features  
■ Non-inverting buffers  
outputs designed to be employed as  
address driver, clock driver, or bus-oriented transmitter/  
receiver.  
a memory and  
■ Output sink capability of 64 mA, source capability of  
32 mA  
■ Guaranteed output skew  
■ Guaranteed multiple output switching specifications  
■ Output switching specified for both 50 pF and 250 pF  
loads  
■ Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
■ Guaranteed latchup protection  
■ High impedance glitch free bus loading during entire  
power up and power down cycle  
■ Nondestructive hot insertion capability  
■ Disable time less than enable time to avoid bus conten-  
tion  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74ABT244CSC  
74ABT244CSJ  
74ABT244CMSA  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Pb-Free 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
MSA20  
MSA20  
74ABT244CMSAX_NL  
(Note 1)  
74ABT244CMTC  
MTC20  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74ABT244CMTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74ABT244CPC  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
© 2005 Fairchild Semiconductor Corporation  
DS010992  
www.fairchildsemi.com  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OE1, OE2  
Output Enable Input  
(Active LOW)  
Inputs  
I0–I7  
O0–O7  
Outputs  
Truth Table  
OE1  
I0–3  
O0–3  
OE2  
I4–7  
O4–7  
H
L
L
X
H
L
Z
H
L
H
L
L
X
H
L
Z
H
L
H
L
X
Z
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
High Impedance  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions  
Storage Temperature  
65 C to 150 C  
Ambient Temperature under Bias  
Junction Temperature under Bias  
VCC Pin Potential to Ground Pin  
Input Voltage (Note 3)  
55 C to 125 C  
55 C to 150 C  
0.5V to 7.0V  
Free Air Ambient Temperature  
Supply Voltage  
40 C to 85 C  
4.5V to 5.5V  
Minimum Input Edge Rate ( V/ t)  
Data Input  
0.5V to 7.0V  
50 mV/ns  
20 mV/ns  
Input Current (Note 3)  
30 mA to 5.0 mA  
Enable Input  
Voltage Applied to Any Output  
in the Disabled or  
Power-Off State  
0.5V to 5.5V  
0.5V to VCC  
in the HIGH State  
Current Applied to Output  
in LOW State (Max)  
twice the rated IOL (mA)  
Note 2: Absolute maximum ratings are values beyond which the device  
may be damaged or have its useful life impaired. Functional operation  
under these conditions is not implied.  
DC Latchup Source Current  
Over Voltage Latchup (I/O)  
500 mA  
10V  
Note 3: Either voltage limit or current limit is sufficient to protect inputs.  
DC Electrical Characteristics  
V
Symbol  
Parameter  
Input HIGH Voltage  
Min  
Typ  
Max  
Units  
Conditions  
Recognized HIGH Signal  
Recognized LOW Signal  
CC  
V
2.0  
V
V
V
V
V
IH  
V
V
V
Input LOW Voltage  
0.8  
1.2  
IL  
Input Clamp Diode Voltage  
Output HIGH Voltage  
Min  
Min  
Min  
I
I
I
I
18 mA  
3 mA  
CD  
OH  
IN  
2.5  
2.0  
OH  
OH  
OL  
32 mA  
V
Output LOW Voltage  
Input HIGH Current  
0.55  
64 mA  
OL  
I
1
1
7
1
1
A
Max  
V
V
V
V
V
2.7V (Note 5)  
IH  
IN  
IN  
IN  
IN  
IN  
V
CC  
I
I
Input HIGH Current Breakdown Test  
Input LOW Current  
A
A
Max  
Max  
0.0  
7.0V  
BVI  
IL  
0.5V (Note 5)  
0.0V  
V
Input Leakage Test  
4.75  
100  
V
I
1.9  
A
ID  
ID  
All Other Pins Grounded  
I
Output Leakage Current  
10  
A
0
0
5.5V  
5.5V  
Max  
V
2.7V; OE  
2.0V  
2.0V  
OZH  
OUT  
n
I
I
I
I
I
I
Output Leakage Current  
Output Short-Circuit Current  
Output High Leakage Current  
Bus Drainage Test  
10  
275  
50  
A
mA  
A
V
V
V
V
0.5V; OE  
0.0V  
OZL  
OS  
OUT  
OUT  
OUT  
OUT  
n
Max  
0.0  
V
CC  
CEX  
ZZ  
100  
50  
A
5.5V; All Others GND  
Power Supply Current  
Power Supply Current  
A
Max  
Max  
All Outputs HIGH  
All Outputs LOW  
CCH  
CCL  
30  
mA  
I
Power Supply Current  
50  
A
Max  
OE  
V
,
CCZ  
n
CC  
All Others at V or Ground  
CC  
I
Additional I /Input  
Outputs Enabled  
Outputs 3-STATE  
Outputs 3-STATE  
2.5  
2.5  
50  
mA  
mA  
A
V
V
2.1V  
CCT  
CC  
I
CC  
Max  
Enable Input V  
V
2.1V  
2.1V  
I
CC  
Data Input V  
V
I
CC  
All Others at V or Ground  
CC  
I
Dynamic I  
(Note 5)  
No Load  
mA/  
Outputs OPEN  
CCD  
CC  
Max  
0.1  
MHz  
OE  
GND, (Note 4)  
n
One Bit Toggling, 50% Duty Cycle  
Note 4: For 8 bits toggling, I  
0.8 mA/MHz.  
CCD  
Note 5: Guaranteed, but not tested.  
3
www.fairchildsemi.com  
DC Electrical Characteristics  
(SOIC package)  
Conditions  
V
C
50 pF,  
500  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
CC  
L
R
L
V
Quiet Output Maximum Dynamic V  
0.5  
0.8  
3.1  
1.5  
1.1  
0.8  
V
V
V
V
V
5.0  
5.0  
5.0  
5.0  
5.0  
T
T
T
T
T
25 C (Note 6)  
25 C (Note 6)  
25 C (Note 8)  
25 C (Note 7)  
25 C (Note 7)  
OLP  
OLV  
OHV  
IHD  
ILD  
OL  
A
A
A
A
A
V
V
V
V
Quiet Output Minimum Dynamic V  
1.3  
2.7  
2.0  
OL  
Minimum HIGH Level Dynamic Output Voltage  
Minimum HIGH Level Dynamic Input Voltage  
Maximum LOW Level Dynamic Input Voltage  
0.8  
Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.  
Note 7: Max number of data inputs (n) switching. n 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ), 0V to threshold (V ).  
ILD  
IHD  
Guaranteed, but not tested.  
Note 8: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.  
AC Electrical Characteristics  
(SOIC and SSOP package)  
T
25 C  
5V  
T
55 C to 125 C  
T
A
40 C to 85 C  
A
A
V
V
4.5V–5.5V  
V
CC  
4.5V–5.5V  
CC  
CC  
Symbol  
Parameter  
Units  
C
50 pF  
C
50 pF  
C
L
50 pF  
Max  
L
L
Min  
1.0  
1.0  
1.5  
1.5  
1.7  
1.7  
Typ  
Max  
3.6  
3.6  
6.0  
6.0  
5.6  
5.6  
Min  
1.0  
1.0  
0.8  
1.2  
1.2  
1.0  
Max  
5.3  
5.0  
6.5  
7.9  
7.6  
7.9  
Min  
1.0  
1.0  
1.5  
1.5  
1.7  
1.7  
t
t
t
t
t
t
Propagation Delay  
2.5  
2.3  
3.5  
3.6  
3.5  
3.3  
3.6  
3.6  
6.0  
6.0  
5.6  
5.6  
PLH  
ns  
ns  
ns  
Data to Outputs  
Output Enable  
Time  
PHL  
PZH  
PZL  
PHZ  
PLZ  
Output Disable  
Time  
Extended AC Electrical Characteristics  
(SOIC package)  
T
40 C to 85 C  
T
40 C to 85 C  
4.5V–5.5V  
250 pF  
T
A
40 C to 85 C  
4.5V–5.5V  
250 pF  
L
A
A
V
4.5V–5.5V  
V
V
CC  
CC  
CC  
C
C
50 pF  
C
Symbol  
Parameter  
Units  
L
L
8 Outputs Switching  
(Note 9)  
1 Output Switching  
(Note 10)  
8 Outputs Switching  
(Note 11)  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
f
Max Toggle Frequency  
Propagation Delay  
Data to Outputs  
100  
MHz  
ns  
TOGGLE  
t
1.5  
1.5  
1.5  
1.5  
1.0  
1.0  
5.0  
5.0  
6.5  
6.5  
5.6  
5.6  
1.5  
1.5  
2.5  
2.5  
6.0  
6.0  
7.5  
7.5  
2.5  
2.5  
2.5  
2.5  
8.5  
8.5  
PLH  
t
PHL  
t
Output Enable Time  
10.0  
12.0  
PZH  
ns  
ns  
t
PZL  
t
Output Disable Time  
PHZ  
(Note 12)  
(Note 12)  
t
PLZ  
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase  
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).  
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load  
capacitors in the standard AC load. This specification pertains to single output switching only.  
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase  
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.  
Note 12: The 3-STATE delays are dominated by the RC network (500 , 250 pF) on the output and have been excluded from the datasheet.  
www.fairchildsemi.com  
4
Skew  
T
40 C to 85 C  
T
40 C to 85 C  
A
A
V
4.5V–5.5V  
V
4.5V–5.5V  
CC  
CC  
C
50 pF  
C
250 pF  
L
L
Symbol  
Parameter  
Units  
8 Outputs Switching  
(Note 15)  
8 Outputs Switching  
(Note 16)  
Max  
Max  
t
Pin to Pin Skew  
HL Transitions  
Pin to Pin Skew  
LH Transitions  
Duty Cycle  
OSHL  
0.8  
0.8  
1.0  
1.0  
1.5  
1.8  
1.8  
2.5  
2.5  
3.0  
ns  
ns  
ns  
ns  
ns  
(Note 13)  
t
OSLH  
(Note 13)  
t
PS  
(Note 17)  
LH–HL Skew  
Pin to Pin Skew  
t
OST  
(Note 13)  
LH/HL Transitions  
Device to Device Skew  
LH/HL Transitions  
t
PV  
(Note 14)  
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.  
The specification applies to any outputs switching HIGH-to-LOW (t ), LOW-to-HIGH (t ), or any combination switching LOW-to-HIGH and/or  
OSHL  
OSLH  
HIGH-to-LOW (t  
). The specification is guaranteed but not tested.  
OST  
Note 14: Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This specification is guaranteed but not  
CC  
tested.  
Note 15: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase  
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)  
Note 16: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load  
capacitors in the standard AC load.  
Note 17: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all  
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.  
Capacitance  
Conditions  
Symbol  
Parameter  
Typ  
Units  
T
25 C  
A
C
C
Input Capacitance  
Output Capacitance  
5.0  
9.0  
pF  
pF  
V
V
0V  
IN  
CC  
CC  
(Note 18)  
5.0V  
OUT  
Note 18: C  
is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.  
OUT  
5
www.fairchildsemi.com  
AC Loading  
*Includes jig and probe capacitance  
FIGURE 1. Standard AC Test Load  
AC Waveforms  
FIGURE 5. 3-STATE Output HIGH  
and LOW Enable and Disable Times  
FIGURE 2. Test Input Signal Levels  
Amplitude Rep. Rate  
3.0V 1 MHz  
tW  
tr  
tf  
500 ns  
2.5 ns  
2.5 ns  
FIGURE 3. Test Input Signal Requirements  
FIGURE 6. Propagation Delay Waveforms for  
Inverting and Non-Inverting Functions  
FIGURE 4. Propagation Delay,  
Pulse Width Waveforms  
FIGURE 7. Setup Time, Hold Time  
and Recovery Time Waveforms  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Package Number MSA20  
9
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
www.fairchildsemi.com  
10  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Package Number N20A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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11  
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