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November 1992  
Revised March 2005  
74ABT574  
Octal D-Type Flip-Flop with 3-STATE Outputs  
General Description  
Features  
The ABT574 is an octal flip-flop with a buffered common  
Clock (CP) and a buffered common Output Enable (OE).  
The information presented to the D inputs is stored in the  
flip-flops on the LOW-to-HIGH Clock (CP) transition.  
■ Inputs and outputs on opposite sides of package  
allowing easy interface with microprocessors  
■ Useful as input or output port for microprocessors  
■ Functionally identical to ABT374  
The device is functionally identical to the ABT374 but has  
broadside pinouts.  
■ 3-STATE outputs for bus-oriented applications  
■ Output sink capability of 64 mA, source capability  
of 32 mA  
■ Guaranteed output skew  
■ Guaranteed multiple output switching specifications  
■ Output switching specified for both 50 pF and  
250 pF loads  
■ Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
■ Guaranteed latchup protection  
■ High impedance glitch free bus loading during entire  
power up and power down cycle  
■ Non-destructive hot insertion capability  
Ordering Code:  
Order Number Package Number  
Package Description  
74ABT574CSC  
74ABT574CSJ  
74ABT574CMSA  
74ABT574CMTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MSA20  
MTC20  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Pin Descriptions  
Connection Diagram  
Pin Names  
Description  
D0–D7  
CP  
Data Inputs  
Clock Pulse Input (Active Rising Edge)  
3-STATE Output Enable Input (Active LOW)  
3-STATE Outputs  
OE  
O0–O7  
© 2005 Fairchild Semiconductor Corporation  
DS011511  
www.fairchildsemi.com  
Functional Description  
The ABT574 consists of eight edge-triggered flip-flops with  
individual D-type inputs and 3-STATE true outputs. The  
buffered clock and buffered Output Enable are common to  
all flip-flops. The eight flip-flops will store the state of their  
individual D inputs that meet the setup and hold times  
requirements on the LOW-to-HIGH Clock (CP) transition.  
With the Output Enable (OE) LOW, the contents of the  
eight flip-flops are available at the outputs. When OE is  
HIGH, the outputs are in a high impedance state. Opera-  
tion of the OE input does not affect the state of the flip-  
flops.  
Function Table  
Inputs  
Internal Outputs  
Function  
OE  
H
H
H
H
L
CP  
D
L
Q
NC  
NC  
L
O
H or L  
H or L  
Z
Z
Hold  
H
L
Hold  
Z
Load  
H
L
H
Z
Load  
L
L
Data Available  
Data Available  
No Change in Data  
No Change in Data  
L
H
L
H
H
L
H or L  
H or L  
NC  
NC  
NC  
NC  
L
H
H
L
X
Z
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
High Impedance  
LOW-to-HIGH Transition  
NC No Change  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 1)  
Recommended Operating  
Conditions  
Storage Temperature  
65 C to 150 C  
Ambient Temperature under Bias  
Junction Temperature under Bias  
VCC Pin Potential to Ground Pin  
Input Voltage (Note 2)  
55 C to 125 C  
55 C to 150 C  
0.5V to 7.0V  
Free Air Ambient Temperature  
Supply Voltage  
40 C to 85 C  
4.5V to 5.5V  
Minimum Input Edge Rate ( V/ t)  
Data Input  
0.5V to 7.0V  
50 mV/ns  
20 mV/ns  
100 mV/ns  
Input Current (Note 2)  
30 mA to 5.0 mA  
Enable Input  
Voltage Applied to Any Output  
in the Disabled or  
Clock Input  
Power-Off State  
0.5V to 5.5V  
0.5V to VCC  
in the HIGH State  
Current Applied to Output  
in LOW State (Max)  
twice the rated IOL (mA)  
Note 1: Absolute maximum ratings are values beyond which the device  
may be damaged or have its useful life impaired. Functional operation  
under these conditions is not implied.  
DC Latchup Source Current  
Over Voltage Latchup (I/O)  
500 mA  
10V  
Note 2: Either voltage limit or current limit is sufficient to protect inputs.  
DC Electrical Characteristics  
V
Symbol  
Parameter  
Input HIGH Voltage  
Min  
Typ  
Max  
Units  
Conditions  
CC  
V
2.0  
V
V
V
V
V
Recognized HIGH Signal  
Recognized LOW Signal  
IH  
V
V
V
Input LOW Voltage  
0.8  
1.2  
IL  
Input Clamp Diode Voltage  
Output HIGH Voltage  
Min  
Min  
Min  
I
I
I
I
18 mA  
3 mA  
CD  
OH  
IN  
2.5  
2.0  
OH  
OH  
OL  
32 mA  
V
Output LOW Voltage  
Input HIGH Current  
0.55  
64 mA  
OL  
I
1
1
7
1
1
V
V
V
V
V
2.7V (Note 3)  
IH  
IN  
IN  
IN  
IN  
IN  
A
A
Max  
Max  
Max  
0.0  
V
CC  
I
Input HIGH Current Breakdown Test  
Input LOW Current  
7.0V  
BVI  
I
0.5V (Note 3)  
0.0V  
IL  
A
V
Input Leakage Test  
4.75  
100  
V
I
1.9  
A
ID  
ID  
All Other Pins Grounded  
I
Output Leakage Current  
10  
A
0
0
5.5V  
5.5V  
Max  
V
2.7V; OE 2.0V  
OZH  
OUT  
I
Output Leakage Current  
Output Short-Circuit Current  
Output High Leakage Current  
Bus Drainage Test  
10  
275  
50  
A
mA  
A
V
V
V
V
0.5V; OE 2.0V  
0.0V  
OZL  
OUT  
OUT  
OUT  
OUT  
I
OS  
I
Max  
0.0  
V
CC  
CEX  
I
100  
50  
A
5.5V; All Other GND  
ZZ  
I
Power Supply Current  
Power Supply Current  
A
Max  
Max  
All Outputs HIGH  
All Outputs LOW  
CCH  
I
30  
mA  
CCL  
I
Power Supply Current  
50  
A
Max  
OE  
V
CC  
CCZ  
All Others at V or GND  
CC  
I
Additional I /Input  
Outputs Enabled  
Outputs 3-STATE  
Outputs 3-STATE  
2.5  
2.5  
2.5  
mA  
mA  
mA  
V
V
2.1V  
CCT  
CC  
I
CC  
Max  
Enable Input V  
V
2.1V  
2.1V  
I
CC  
Data Input V  
V
I
CC  
All Others at V or GND  
CC  
I
Dynamic I  
(Note 3)  
No Load  
mA/  
Outputs Open, OE GND,  
One Bit Toggling (Note 4),  
50% Duty Cycle  
CCD  
CC  
Max  
0.30  
MHz  
Note 3: Guaranteed, but not tested.  
Note 4: For 8-bit toggling, I 0.8 mA/MHz.  
CCD  
3
www.fairchildsemi.com  
DC Electrical Characteristics  
(SOIC Package)  
Conditions  
50 pF, R  
V
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
CC  
C
500  
L
L
V
V
V
V
V
Quiet Output Maximum Dynamic V  
0.7  
1.1  
3.0  
1.6  
1.2  
1.0  
V
V
V
V
V
5.0  
5.0  
5.0  
5.0  
5.0  
T
25 C (Note 5)  
25 C (Note 5)  
25 C (Note 6)  
25 C (Note 7)  
25 C (Note 7)  
OLP  
OLV  
OHV  
IHD  
ILD  
OL  
A
Quiet Output Minimum Dynamic V  
1.5  
2.5  
2.0  
T
T
T
T
OL  
A
A
A
A
Minimum HIGH Level Dynamic Output Voltage  
Minimum HIGH Level Dynamic Input Voltage  
Maximum LOW Level Dynamic Input Voltage  
0.8  
Note 5: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.  
Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.  
Note 7: Max number of data inputs (n) switching. n 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ), 0V to threshold (V ).  
ILD  
IHD  
Guaranteed, but not tested.  
AC Electrical Characteristics  
(SOIC and SSOP Package)  
T
25 C  
5.0V  
T
55 C to 125 C  
4.5V to 5.5V  
T
A
40 C to 85 C  
4.5V to 5.5V  
50 pF  
Max  
A
A
V
V
V
CC  
CC  
CC  
Symbol  
Parameter  
Units  
C
50 pF  
C
50 pF  
Max  
C
L
L
L
Min  
150  
2.0  
2.0  
1.5  
1.5  
1.5  
1.5  
Typ  
Max  
Min  
150  
1.5  
1.5  
1.0  
1.0  
1.0  
1.0  
Min  
150  
2.0  
2.0  
1.5  
1.5  
1.5  
1.5  
f
t
t
t
t
t
t
Maximum Clock Frequency  
Propagation Delay  
200  
3.2  
3.3  
3.1  
3.1  
3.6  
3.4  
MHz  
ns  
MAX  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
5.0  
5.0  
5.3  
5.3  
5.4  
5.4  
7.0  
7.4  
6.5  
7.2  
7.2  
6.7  
5.0  
5.0  
5.3  
5.3  
5.4  
5.4  
CP to O  
n
Output Enable Time  
ns  
ns  
Output Disable Time  
AC Operating Requirements  
T
25 C  
5.0V  
T
55 C to 125 C  
4.5V to 5.5V  
T
A
40 C to 85 C  
4.5V to 5.5V  
A
A
V
V
V
CC  
CC  
CC  
Symbol  
Parameter  
Units  
C
50 pF  
C
50 pF  
Max  
C
L
50 pF  
Max  
L
L
Min  
1.0  
1.5  
1.0  
1.0  
3.0  
3.0  
Max  
Min  
1.5  
2.0  
2.0  
2.0  
3.3  
3.3  
Min  
1.0  
1.5  
1.0  
1.0  
3.0  
3.0  
t (H)  
Setup Time, HIGH  
S
ns  
ns  
ns  
t (L)  
or LOW D to CP  
n
S
t (H)  
Hold Time, HIGH  
H
t (L)  
or LOW D to CP  
n
H
t
(H)  
(L)  
Pulse Width, CP,  
HIGH or LOW  
W
t
W
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4
Extended AC Electrical Characteristics  
(SOIC Package)  
T
40 C to 85 C  
4.5V to 5.5V  
T
40 C to 85 C  
4.5V to 5.5V  
T
A
40 C to 85 C  
4.5V to 5.5V  
A
A
V
V
V
CC  
CC  
CC  
C
50 pF  
C
250 pF  
C
L
250 pF  
L
L
Symbol  
Parameter  
Units  
8 Outputs Switching  
(Note 8)  
(Note 9)  
8 Outputs Switching  
(Note 10)  
Min  
1.5  
1.5  
1.5  
1.5  
1.0  
1.0  
Max  
5.7  
5.7  
6.2  
6.2  
5.5  
5.5  
Min  
2.0  
2.0  
2.0  
2.0  
Max  
Min  
2.0  
2.0  
2.0  
2.0  
Max  
10.0  
10.0  
10.5  
10.5  
t
t
t
t
t
t
Propagation Delay  
CP to O  
7.8  
7.8  
8.0  
8.0  
PLH  
ns  
ns  
ns  
PHL  
PZH  
PZL  
PHZ  
PLZ  
n
Output Enable Time  
Output Disable Time  
(Note 11)  
(Note 11)  
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase  
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).  
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-  
itors in the standard AC load. This specification pertains to single output switching only.  
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase  
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.  
Note 11: The 3-STATE Delay Times are dominated by the RC network (500 , 250 pF) on the output and has been excluded from the datasheet.  
Skew (Note 12)  
(SOIC package)  
T
40 C to 85 C  
4.5V–5.5V  
T
40 C to 85 C  
4.5V–5.5V  
A
A
V
V
CC  
CC  
C
50 pF  
C
250 pF  
L
L
Symbol  
Parameter  
Units  
8 Outputs Switching  
(Note 12)  
8 Outputs Switching  
(Note 13)  
Max  
Max  
t
Pin to Pin Skew  
HL Transitions  
Pin to Pin Skew  
LH Transitions  
Duty Cycle  
OSHL  
1.0  
1.0  
1.8  
2.0  
2.5  
1.8  
1.8  
4.3  
4.3  
4.6  
ns  
ns  
ns  
ns  
ns  
(Note 14)  
t
OSLH  
(Note 14)  
t
PS  
(Note 15)  
LH–HL Skew  
Pin to Pin Skew  
t
OST  
(Note 14)  
LH/HL Transitions  
Device to Device Skew  
LH/HL Transitions  
t
PV  
(Note 16)  
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase  
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).  
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load  
capacitors in the standard AC load.  
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.  
The specification applies to any outputs switching HIGH-to-LOW (t  
), LOW-to-HIGH (t  
), or any combination switching LOW-to-HIGH and/or HIGH-  
OSLH  
OSHL  
to-LOW (t  
). This specification is guaranteed but not tested.  
OST  
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all  
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.  
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This specification is guaranteed but not  
CC  
tested.  
Capacitance  
Conditions  
Symbol  
Parameter  
Typ  
Units  
T
25 C  
A
C
C
Input Capacitance  
Output Capacitance  
5.0  
9.0  
pF  
pF  
V
V
0V  
IN  
CC  
CC  
(Note 17)  
5.0V  
OUT  
Note 17: C  
is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.  
OUT  
5
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AC Loading  
*Includes jig and probe capacitance  
FIGURE 2. VM 1.5V  
FIGURE 1. Standard AC Test Load  
Input Pulse Requirements  
Amplitude Rep. Rate  
3.0V 1 MHz  
tW  
tr  
tf  
500 ns  
2.5 ns  
2.5 ns  
FIGURE 3. Test Input Signal Requirements  
AC Waveforms  
FIGURE 4. Propagation Delay Waveforms for  
Inverting and Non-Inverting Functions  
FIGURE 6. 3-STATE Output HIGH  
and LOW Enable and Disable Times  
FIGURE 7. Setup Time, Hold Time  
and Recovery Time Waveforms  
FIGURE 5. Propagation Delay,  
Pulse Width Waveforms  
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6
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Package Number MSA20  
9
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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10