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March 2007  
74ABT373  
tm  
Octal Transparent Latch with 3-STATE Outputs  
Features  
General Description  
■ 3-STATE outputs for bus interfacing  
The ABT373 consists of eight latches with 3-STATE  
outputs for bus organized system applications. The flip-  
flops appear transparent to the data when Latch Enable  
(LE) is HIGH. When LE is LOW, the data that meets the  
setup times is latched. Data appears on the bus when  
the Output Enable (OE) is LOW. When OE is HIGH the  
bus output is in the high impedance state.  
■ Output sink capability of 64mA, source capability of  
32mA  
■ Guaranteed output skew  
■ Guaranteed multiple output switching specifications  
■ Output switching specified for both 50pF and 250pF  
loads  
■ Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
■ Guaranteed latchup protection  
■ High-impedance, glitch-free bus loading during entire  
power up and power down  
■ Nondestructive, hot-insertion capability  
Ordering Information  
Package  
Order Number  
74ABT373CSC  
74ABT373CSJ  
74ABT373CMSA  
74ABT373CMTC  
Number  
Package Description  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
M20D  
MSA20  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
D –D  
Data Inputs  
0
7
LE  
Latch Enable Input (Active HIGH)  
Output Enable Input (Active LOW)  
3-STATE Latch Outputs  
OE  
O –O  
0
7
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
Functional Description  
Truth Table  
The ABT373 contains eight D-type latches with 3-STATE  
output buffers. When the Latch Enable (LE) input is  
Inputs  
Output  
LE  
H
OE  
L
D
O
n
n
HIGH, data on the D inputs enters the latches. In this  
n
condition the latches are transparent, i.e., a latch output  
will change state each time its D input changes. When  
LE is LOW, the latches store the information that was  
present on the D inputs at setup time preceding the  
HIGH-to-LOW transition of LE. The 3-STATE buffers are  
controlled by the Output Enable (OE) input. When OE is  
LOW, the buffers are in the bi-state mode. When OE is  
HIGH the buffers are in the high impedance mode but  
this does not interfere with entering new data into the  
latches.  
H
H
H
L
L
X
X
L
L
L
O (no change)  
n
X
H
Z
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = HIGH Impedance State  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to  
estimate propagation delays.  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Rating  
T
Storage Temperature  
–65°C to +150°C  
STG  
T
Ambient Temperature Under Bias  
Junction Temperature Under Bias  
–55°C to +125°C  
–55°C to +150°C  
–0.5V to +7.0V  
A
T
J
V
V
Pin Potential to Ground Pin  
CC  
CC  
(1)  
V
Input Voltage  
Input Current  
–0.5V to +7.0V  
IN  
IN  
(1)  
I
–30mA to +5.0mA  
V
Voltage Applied to Any Output  
Disabled or Power-Off State  
HIGH State  
O
–0.5V to +5.5V  
–0.5V to V  
CC  
Current Applied to Output in LOW State (Max.)  
DC Latchup Source Current Across Common Operating Range  
OE Pin  
twice the rated I (mA)  
OL  
–150mA  
–500mA  
10V  
Other Pins  
Over Voltage Latchup (I/O)  
Note:  
1. Either voltage limit or current limit is sufficient to protect inputs.  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
Parameter  
Rating  
T
Free Air Ambient Temperature  
Supply Voltage  
–40°C to +85°C  
A
V
+4.5V to +5.5V  
CC  
∆V / ∆t  
Minimum Input Edge Rate  
Data Input  
50mV/ns  
20mV/ns  
Enable Input  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
3
DC Electrical Characteristics  
Symbol  
Parameter  
Input HIGH Voltage  
V
Conditions  
Recognized HIGH Signal  
Recognized LOW Signal  
Min. Typ. Max. Units  
CC  
V
2.0  
V
V
V
V
IH  
V
Input LOW Voltage  
0.8  
IL  
V
V
Input Clamp Diode Voltage  
Output HIGH Voltage  
Min.  
Min.  
I
I
I
I
= –18mA  
= –3mA  
–1.2  
CD  
OH  
IN  
2.5  
2.0  
OH  
OH  
OL  
= –32mA  
= 64mA  
V
Output LOW Voltage  
Input HIGH Current  
Min.  
0.55  
V
OL  
(3)  
I
Max.  
V
V
V
= 2.7V  
1
1
7
µA  
IH  
IN  
IN  
IN  
= V  
CC  
I
Input HIGH Current  
Breakdown Test  
Max.  
Max.  
= 7.0V  
µA  
µA  
BVI  
(3)  
I
Input LOW Current  
V
V
I
= 0.5V  
–1  
–1  
IL  
IN  
IN  
= 0.0V  
V
Input Leakage Test  
0.0  
= 1.9µA, All Other Pins  
4.75  
V
ID  
ID  
Grounded  
I
Output Leakage Current  
Output Leakage Current  
Output Short-Circuit Current  
Output HIGH Leakage Current  
Bus Drainage Test  
0–5.5V V  
0–5.5V V  
= 2.7V, OE = 2.0V  
= 0.5V, OE = 2.0V  
= 0.0V  
10  
–10  
–275  
50  
µA  
µA  
mA  
µA  
µA  
µA  
mA  
µA  
OZH  
OUT  
OUT  
OUT  
OUT  
OUT  
I
OZL  
I
Max.  
Max.  
0.0  
V
V
V
–100  
OS  
I
= V  
CEX  
CC  
I
= 5.5V, All Others GND  
100  
50  
ZZ  
I
Power Supply Current  
Power Supply Current  
Power Supply Current  
Max. All Outputs HIGH  
Max. All Outputs LOW  
CCH  
I
I
30  
CCL  
Max. OE = V , All Others at V  
CC  
50  
CCZ  
CC  
or Ground  
I
Additional Outputs Enabled  
Max. V = V – 2.1V  
2.5  
2.5  
2.5  
mA  
mA  
mA  
CCT  
I
CC  
I
/Input  
CC  
Outputs 3-STATE  
Outputs 3-STATE  
Enable Input V = V – 2.1V  
I CC  
Data Input V = V – 2.1V,  
I
CC  
All Others at V or Ground  
CC  
(3)  
I
Dynamic I No Load  
Max. Outputs OPEN, LE = V ,  
CC  
0.12  
mA/  
MHz  
CCD  
CC  
(2)  
OE = GND  
,
One-Bit Toggling,  
50% Duty Cycle  
Notes:  
2. For 8-bit toggling, I  
< 0.8mA/MHz.  
CCD  
3. Guaranteed, but not tested.  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
4
DC Electrical Characteristics  
SOIC package.  
Conditions  
CL = 50pF, RL = 500Ω  
(4)  
Symbol  
Parameter  
VCC  
Min.  
Typ.  
Max. Units  
V
Quiet Output Maximum Dynamic  
5.0  
T = 25°C  
0.4  
0.8  
V
V
V
V
V
OLP  
A
V
OL  
(4)  
V
Quiet Output Minimum Dynamic  
5.0  
5.0  
5.0  
5.0  
T = 25°C  
–1.2  
2.5  
–0.8  
3.0  
OLV  
A
V
OL  
(5)  
V
Minimum HIGH Level Dynamic  
Output Voltage  
T = 25°C  
OHV  
A
(6)  
V
Minimum HIGH Level Dynamic  
Input Voltage  
T = 25°C  
2.0  
1.7  
IHD  
A
(6)  
V
Maximum LOW Level Dynamic  
Input Voltage  
T = 25°C  
0.9  
0.6  
ILD  
A
Notes:  
4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not  
tested.  
5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not  
tested.  
6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold  
(V ), 0V to threshold (V ). Guaranteed, but not tested.  
ILD  
IHD  
AC Electrical Characteristics  
SOIC and SSOP package.  
TA = +25°C,  
VCC = +5.0V,  
CL = 50pF  
TA = –55°C to +125°C, TA = –40°C to +85°C,  
VCC = 4.5V to 5.5V,  
CL = 50pF  
VCC = 4.5V to 5.5V,  
CL = 50pF  
Symbol  
Parameter  
Min. Typ. Max.  
Min.  
1.0  
1.0  
1.0  
1.5  
1.0  
1.5  
1.7  
1.0  
Max.  
6.8  
7.0  
7.7  
7.7  
6.7  
7.2  
8.0  
7.0  
Min.  
1.9  
1.9  
2.0  
2.0  
1.5  
1.5  
2.0  
2.0  
Max.  
4.5  
4.5  
5.0  
5.0  
5.3  
5.3  
5.4  
5.4  
Units  
t
t
t
t
Propagation Delay  
1.9  
1.9  
2.0  
2.0  
1.5  
1.5  
2.0  
2.0  
2.7  
2.8  
3.1  
3.0  
3.1  
3.1  
3.6  
3.4  
4.5  
4.5  
5.0  
5.0  
5.3  
5.3  
5.4  
5.4  
ns  
PLH  
PHL  
PLH  
PHL  
PZH  
D to O  
n
n
Propagation Delay  
LE to O  
ns  
ns  
ns  
n
t
Output Enable Time  
t
PZL  
PHZ  
t
Output Disable Time  
t
PLZ  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
5
AC Operating Requirements  
SOIC and SSOP packages.  
TA = +25°C,  
VCC = +5.0V,  
CL = 50pF  
TA = –55°C to +125°C, TA = –40°C to +85°C,  
VCC = 4.5V to 5.5V,  
CL = 50pF,  
VCC = 4.5V to 5.5V  
CL = 50pF  
Symbol  
Parameter  
Min. Typ. Max.  
Min.  
100  
2.5  
Max.  
Min.  
Max.  
Units  
MHz  
ns  
f
Max Toggle Frequency  
100  
TOGGLE  
t (H)  
Setup Time, HIGH or  
1.5  
1.5  
1.0  
1.0  
3.0  
1.5  
1.5  
1.0  
1.0  
3.0  
S
LOW, D to LE  
n
t (L)  
2.5  
S
t (H)  
Hold Time, HIGH or  
2.5  
ns  
ns  
H
LOW, D to LE  
n
t (L)  
2.5  
H
t (H)  
Pulse Width, LE HIGH  
3.3  
W
Extended AC Electrical Characteristics  
SOIC package.  
TA = –40°C to +85°C,  
VCC = 4.5V to 5.5V,  
CL = 50pF,  
TA = –40°C to +85°C,  
VCC = 4.5V to 5.5V,  
CL = 250pF,  
TA = –40°C to +85°C,  
VCC = 4.5V to 5.5V,  
CL = 250pF(8)  
8 Outputs  
8 Outputs  
Switching(7)  
Switching(9)  
Symbol  
Parameter  
Min.  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.0  
1.0  
Max.  
5.2  
5.2  
5.5  
5.5  
6.2  
6.2  
5.5  
5.5  
Min.  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
Max.  
6.8  
Min.  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
Max.  
9.0  
Units  
t
t
t
t
Propagation Delay,  
ns  
PLH  
PHL  
PLH  
PHL  
PZH  
D to O  
n
n
6.8  
9.0  
Propagation Delay,  
LE to O  
7.5  
9.5  
ns  
ns  
ns  
n
7.5  
9.5  
t
Output Enable Time  
8.0  
10.5  
10.5  
t
8.0  
PZL  
PHZ  
(10)  
(10)  
t
Output Disable Time  
t
PZL  
Notes:  
7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described  
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).  
8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors  
in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching  
only.  
9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described  
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load  
capacitors in the standard AC load.  
10. The 3-STATE delay times are dominated by the RC network (500Ω, 250pF) on the output and has been excluded  
from the datasheet.  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
6
Skew  
SOIC package.  
T = –40°C to +85°C,  
T = –40°C to +85°C,  
A
A
V
= 4.5V–5.5V,  
V
= 4.5V–5.5V,  
CC  
CC  
C = 50pF,  
C = 250pF,  
L
8 Outputs Switching  
L
(11)  
(12)  
8 Outputs Switching  
Symbol  
Parameter  
Max.  
Max.  
Units  
(13)  
t
Pin to Pin Skew,  
1.0  
1.5  
ns  
OSHL  
HL Transitions  
(13)  
t
Pin to Pin Skew,  
LH Transitions  
1.0  
1.5  
ns  
OSLH  
(15)  
t
Duty Cycle, LH–HL Skew  
1.4  
1.5  
3.5  
3.9  
ns  
ns  
PS  
(13)  
t
Pin to Pin Skew,  
LH/HL Transitions  
OST  
(14)  
t
Device to Device Skew,  
LH/HL Transitions  
2.0  
4.0  
ns  
PV  
Notes:  
11. This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors  
in place of the 50pF load capacitors in the standard AC load.  
12. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described  
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).  
13. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate  
outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (t  
), LOW-to-HIGH  
OSHL  
(t  
), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (t  
). This specification is guaranteed  
OSLH  
OST  
but not tested.  
14. Propagation delay variation is for a given set of conditions (i.e., temperature and V ) from device to device. This  
CC  
specification is guaranteed but not tested.  
15. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same  
pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the  
guaranteed specification. This specification is guaranteed but not tested.  
Capacitance  
Conditions  
Symbol  
Parameter  
T = 25°C  
Typ.  
Units  
pF  
A
C
Input Capacitance  
Output Capacitance  
V
V
= 0V  
5
9
IN  
CC  
(16)  
C
= 5.0V  
pF  
OUT  
CC  
Note:  
16. C  
is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.  
OUT  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
7
AC Loading  
*Includes jig and probe capacitance  
Figure 2.Test Input Signal Levels  
Figure 1. Standard AC Test Load  
Amplitude  
Rep. Rate  
t
t
t
f
w
r
3.0V  
1MHz  
500ns  
2.5ns  
2.5ns  
Figure 3.Test Input Signal Requirements  
AC Waveforms  
Figure 4. Propagation Delay Waveforms for  
Inverting and Non-Inverting Functions  
Figure 6. 3-STATE Output HIGH and  
LOW Enable and Disable Times  
Figure 5. Propagation Delay, Pulse Width Waveforms  
Figure 7. Setup Time, Hold Time  
and Recovery Time Waveforms  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
8
Physical Dimensions  
Dimensions are in inches (millimeters) unless otherwise noted.  
Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
9
Physical Dimensions (Continued)  
Dimensions are in millimeters unless otherwise noted.  
Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
10  
Physical Dimensions (Continued)  
Dimensions are in millimeters unless otherwise noted.  
Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Package Number MSA20  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
11  
Physical Dimensions (Continued)  
Dimensions are in millimeters unless otherwise noted.  
Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
©1993 Fairchild Semiconductor Corporation  
74ABT373 Rev. 1.4  
www.fairchildsemi.com  
12  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an  
exhaustive list of all such trademarks.  
ACEx®  
TinyLogic®  
TINYOPTO¥  
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TruTranslation¥  
PSerDes¥  
UHC®  
UniFET¥  
VCX¥  
Wire¥  
HiSeC¥  
i-Lo¥  
Programmable Active Droop¥  
QFET®  
QS¥  
QT Optoelectronics¥  
Quiet Series¥  
RapidConfigure¥  
RapidConnect¥  
ScalarPump¥  
SMART START¥  
SPM®  
STEALTH™  
SuperFET¥  
SuperSOT¥-3  
SuperSOT¥-6  
SuperSOT¥-8  
SyncFET™  
Across the board. Around the world.¥  
ActiveArray¥  
Bottomless¥  
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CoolFET¥  
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IntelliMAX¥  
ISOPLANAR¥  
MICROCOUPLER¥  
MicroPak¥  
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MSX¥  
CROSSVOLT¥  
CTL™  
Current Transfer Logic™  
DOME¥  
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OCX¥  
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EcoSPARK®  
EnSigna¥  
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OPTOLOGIC®  
OPTOPLANAR®  
PACMAN¥  
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FACT Quiet Series™  
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DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS  
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE  
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER  
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S  
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR  
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,  
which, (a) are intended for surgical implant into the body or  
(b) support or sustain life, and (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in a significant injury of the user.  
device, or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In Design  
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Rev. I24  
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74ABT373 Rev. 1.4  
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