转到网站首页
转为中文步骤：
1、请用电脑端360浏览器打开本页地址，如您电脑未安装360浏览器，请点这里下载;
2、点击360浏览器右上角的翻译插件，如右图红圈中所示:
3、点击所弹出窗口里的右下角的按钮 “翻译当前网页”;
4、弹窗提示翻译完毕后关闭弹窗即可；
November 1988  
Revised March 2005  
74AC245 • 74ACT245  
Octal Bidirectional Transceiver with 3-STATE  
Inputs/Outputs  
General Description  
Features  
■ ICC and IOZ reduced by 50%  
The AC/ACT245 contains eight non-inverting bidirectional  
buffers with 3-STATE outputs and is intended for bus-ori-  
ented applications. Current sinking capability is 24 mA at  
both the A and B ports. The Transmit/Receive (T/R) input  
determines the direction of data flow through the bidirec-  
tional transceiver. Transmit (active-HIGH) enables data  
from A ports to B ports; Receive (active-LOW) enables  
data from B ports to A ports. The Output Enable input,  
when HIGH, disables both A and B ports by placing them in  
a HIGH Z condition.  
■ Non-inverting buffers  
■ Bidirectional data path  
■ A and B outputs source/sink 24 mA  
■ ACT245 has TTL-compatible inputs  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74AC245SC  
74AC245SJ  
74AC245MTC  
74AC245PC  
74ACT245SC  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
M20B  
M20B  
74ACT245SCX_NL  
(Note 1)  
74ACT245SJ  
M20D  
MSA20  
MTC20  
MTC20  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74ACT245MSA  
74ACT245MTC  
74ACT245MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74ACT245PC  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS009944  
www.fairchildsemi.com  
Connection Diagram  
Pin Descriptions  
Pin  
Description  
Names  
OE  
Output Enable Input  
Transmit/Receive Input  
T/R  
A0–A7  
B0–B7  
Side A 3-STATE Inputs or 3-STATE Outputs  
Side B 3-STATE Inputs or 3-STATE Outputs  
Truth Table  
Inputs  
Outputs  
OE  
L
T/R  
L
Logic Symbols  
Bus B Data to Bus A  
Bus A Data to Bus B  
HIGH-Z State  
L
H
H
X
H
L
X
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
IEEE/IEC  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
DC Input Diode Current (IIK  
VI 0.5V  
)
0.5V to 7.0V  
)
Supply Voltage (VCC  
)
20 mA  
20 mA  
AC  
2.0V to 6.0V  
4.5V to 5.5V  
0V to VCC  
VI VCC 0.5V  
ACT  
DC Input Voltage (VI)  
0.5V to VCC 0.5V  
Input Voltage (VI)  
Output Voltage (VO)  
DC Output Diode Current (IOK  
VO 0.5V  
)
0V to VCC  
20 mA  
20 mA  
Operating Temperature (TA)  
Minimum Input Edge Rate ( V/ t)  
AC Devices  
40 C to 85 C  
VO VCC 0.5V  
DC Output Voltage (VO)  
DC Output Source  
0.5V to VCC 0.5V  
V
IN from 30% to 70% of VCC  
or Sink Current (IO)  
50 mA  
VCC @ 3.3V, 4.5V, 5.5V  
Minimum Input Edge Rate ( V/ t)  
ACT Devices  
125 mV/ns  
125 mV/ns  
DC VCC or Ground Current  
per Output Pin (ICC or IGND  
)
50 mA  
Storage Temperature (TSTG  
Junction Temperature (TJ)  
PDIP  
)
65 C to 150 C  
VIN from 0.8V to 2.0V  
VCC @ 4.5V, 5.5V  
140 C  
Note 2: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, with-  
out exception, to ensure that the system design is reliable over its power  
supply, temperature, and output/input loading variables. Fairchild does not  
recommend operation of FACT circuits outside databook specifications.  
DC Electrical Characteristics for AC  
V
T
25 C  
T
A
40 C to 85 C  
CC  
A
Symbol  
Parameter  
Units  
Conditions  
(V)  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
Typ  
1.5  
Guaranteed Limits  
V
V
V
Minimum HIGH Level  
Input Voltage  
2.1  
2.1  
3.15  
3.85  
0.9  
V
0.1V  
IH  
OUT  
2.25  
2.75  
1.5  
3.15  
3.85  
0.9  
V
or V  
0.1V  
CC  
Maximum LOW Level  
Input Voltage  
V
0.1V  
0.1V  
IL  
OUT  
2.25  
2.75  
2.99  
4.49  
5.49  
1.35  
1.65  
2.9  
1.35  
1.65  
2.9  
V
V
or V  
CC  
Minimum HIGH Level  
Output Voltage  
OH  
4.4  
4.4  
I
50 A  
OUT  
5.4  
5.4  
V
V or V  
IL IH  
IN  
OH  
OH  
OH  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
2.56  
3.86  
4.86  
0.1  
2.46  
3.76  
4.76  
0.1  
I
I
I
12 mA  
24 mA  
V
V
24 mA (Note 3)  
V
Maximum LOW Level  
Output Voltage  
0.002  
0.001  
0.001  
OL  
0.1  
0.1  
I
50  
A
OUT  
0.1  
0.1  
V
V
or V  
IH  
IN  
OL  
OL  
OL  
IL  
3.0  
4.5  
5.5  
5.5  
5.5  
5.5  
5.5  
0.36  
0.36  
0.36  
0.1  
0.44  
0.44  
0.44  
1.0  
I
I
I
12 mA  
24 mA  
V
24 mA (Note 3)  
V , GND  
CC  
I
I
I
I
I
Maximum Input Leakage Current  
Dynamic Output  
A
mA  
mA  
A
V
V
V
V
IN (Note 5)  
OLD  
I
75  
1.65V Max  
3.85V Min  
OLD  
OHD  
IN  
Current Minimum (Note 4)  
75  
OHD  
(Note 5) Maximum Quiescent Supply Current  
4.0  
0.3  
40.0  
V
or GND  
CC  
CC  
Maximum I/O  
V (OE)  
V , V  
IL IH  
OZT  
I
Leakage Current  
5.5  
3.0  
A
V
V
V
, GND  
I
CC  
V
, GND  
O
CC  
Note 3: All outputs loaded; thresholds on input associated with output under test.  
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.  
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .  
CC  
IN  
CC  
3
www.fairchildsemi.com  
DC Characteristics for ACT  
V
T
25 C  
T
A
40 C to 85 C  
CC  
A
Symbol  
Parameter  
Units  
Conditions  
(V)  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
Typ  
1.5  
1.5  
1.5  
1.5  
Guaranteed Limits  
V
Minimum HIGH Level  
Input Voltage  
2.0  
2.0  
2.0  
0.8  
0.8  
4.4  
5.4  
V
0.1V  
0.1V  
0.1V  
0.1V  
IH  
OUT  
V
V
V
2.0  
0.8  
0.8  
4.4  
5.4  
or V  
CC  
V
Maximum LOW Level  
Input Voltage  
V
IL  
OUT  
or V  
CC  
V
Minimum HIGH Level  
Output Voltage  
4.49  
5.49  
I
50 A  
OH  
OUT  
V
V or V  
IL IH  
IN  
OH  
OH  
4.5  
5.5  
4.5  
5.5  
3.86  
4.86  
0.1  
3.76  
4.76  
0.1  
I
I
I
24 mA  
24 mA (Note 6)  
V
V
V
Maximum LOW Level  
Output Voltage  
0.001  
0.001  
50  
A
OL  
OUT  
0.1  
0.1  
V
V
or V  
IH  
IN  
OL  
OL  
IL  
4.5  
5.5  
5.5  
0.36  
0.36  
0.1  
0.44  
0.44  
1.0  
V
A
I
I
24 mA  
24 mA (Note 6)  
I
I
Maximum Input  
Leakage Current  
Maximum  
V
V
, GND  
IN  
I
CC  
V
V
2.1V  
CCT  
I
CC  
5.5  
0.6  
1.5  
mA  
I
/Input  
CC  
I
I
I
Dynamic Output  
5.5  
5.5  
75  
75  
mA  
mA  
V
V
V
1.65V Max  
3.85V Min  
OLD  
OHD  
CC  
OLD  
OHD  
IN  
Current Minimum (Note 7)  
Maximum Quiescent  
Supply Current  
V
CC  
5.5  
4.0  
0.3  
40.0  
A
or GND  
V (OE) V , V  
IL IH  
I
Maximum I/O  
OZT  
I
Leakage Current  
5.5  
3.0  
A
V
V
V
, GND  
I
CC  
V
, GND  
O
CC  
Note 6: All outputs loaded; thresholds on input associated with output under test.  
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.  
AC Electrical Characteristics for AC  
V
T
25 C  
T
40 C to 85 C  
50 pF  
Min Max  
CC  
A
A
C
50 pF  
C
L
Symbol  
Parameter  
(V)  
(Note 8)  
3.3  
Units  
L
Min  
1.5  
1.5  
1.5  
1.5  
2.5  
1.5  
2.5  
1.5  
2.0  
1.5  
2.0  
1.5  
Typ  
Max  
8.5  
t
t
t
t
t
t
Propagation Delay  
to B or B to A  
5.0  
3.5  
5.0  
3.5  
7.0  
5.0  
7.5  
5.5  
6.5  
5.5  
7.0  
5.5  
1.0  
1.0  
1.0  
1.0  
2.0  
1.0  
2.0  
1.0  
1.0  
1.0  
1.5  
1.0  
9.0  
7.0  
PLH  
ns  
ns  
ns  
ns  
ns  
ns  
A
5.0  
6.5  
n
n
n
n
Propagation Delay  
to B or B to A  
3.3  
8.5  
9.0  
PHL  
PZH  
PZL  
PHZ  
PLZ  
A
5.0  
6.0  
7.0  
n
n
n
n
Output Enable Time  
Output Enable Time  
Output Disable Time  
Output Disable Time  
3.3  
11.5  
8.5  
12.5  
9.0  
5.0  
3.3  
12.0  
9.0  
13.5  
9.5  
5.0  
3.3  
12.0  
9.0  
12.5  
10.0  
13.0  
10.0  
5.0  
3.3  
11.5  
9.0  
5.0  
Note 8: Voltage Range 3.3 is 3.3V 0.3V  
Voltage Range 5.0 is 5.0V 0.5V  
www.fairchildsemi.com  
4
AC Electrical Characteristics for ACT  
V
T
25 C  
T
40 C to 85 C  
50 pF  
Min Max  
CC  
A
A
C
50 pF  
C
L
Symbol  
Parameter  
(V)  
(Note 9)  
5.0  
Units  
ns  
L
Min  
Typ  
Max  
t
t
Propagation Delay  
to B or B to A  
1.5  
4.0  
7.5  
1.5  
8.0  
PLH  
A
n
n
n
n
Propagation Delay  
to B or B to A  
5.0  
1.5  
4.0  
8.0  
1.0  
9.0  
ns  
PHL  
A
n
n
n
n
t
t
t
t
Output Enable Time  
Output Enable Time  
Output Disable Time  
Output Disable Time  
5.0  
5.0  
5.0  
5.0  
1.5  
1.5  
1.5  
2.0  
5.0  
5.5  
5.5  
5.0  
10.0  
10.0  
10.0  
10.0  
1.5  
1.5  
1.0  
1.5  
11.0  
12.0  
11.0  
11.0  
ns  
ns  
ns  
ns  
PZH  
PZL  
PHZ  
PLZ  
Note 9: Voltage Range 5.0 is 5.0V 0.5V  
Capacitance  
Symbol  
Parameter  
Typ  
4.5  
Units  
pF  
Conditions  
C
Input Capacitance  
V
V
V
OPEN  
5.0V  
IN  
CC  
CC  
CC  
C
C
Input/Output Capacitance  
Power Dissipation Capacitance  
15.0  
45.0  
pF  
I/O  
PD  
pF  
5.0V  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Package Number MSA20  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
9
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Package Number N20A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
10