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INTEGRATED CIRCUITS  
DATA SHEET  
74AHC573; 74AHCT573  
Octal D-type transparent latch;  
3-state  
Product specification  
2003 Dec 08  
Supersedes data of 1999 Sep 27  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
FEATURES  
The 74AHC/AHCT573 are octal D-type transparent  
latches featuring separate D-type inputs for each latch and  
3-state outputs for bus oriented applications. A Latch  
Enable (LE) input and an Output Enable (OE) input are  
common to all latches.  
• ESD protection:  
HBM EIA/JESD22-A114-A exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
• Balanced propagation delays  
The 74AHC/AHCT573 consists of eight D-type transparent  
latches with 3-state true outputs. When pin LE is HIGH,  
data at the Dn inputs enters the latches. In this condition  
the latches are transparent, i.e. a latch output will change  
state each time its corresponding D-input changes.  
• All inputs have Schmitt-trigger actions  
• Common 3-state output enable input  
• Functionally identical to the 74AHC/AHCT563 and  
74AHC/AHCT373  
• Inputs accepts voltages higher than VCC  
When pin LE is LOW the latches store the information that  
was present at the D-inputs a set-up time preceding the  
HIGH-to-LOW transition of LE. When pin OE is LOW, the  
contents of the 8 latches are available at the outputs.  
When pin OE is HIGH, the outputs go to the  
• For AHC only: operates with CMOS input levels  
• For AHCT only: operates with TTL input levels  
• Specified from −40 to +85 °C and −40 to +125 °C.  
high-impedance OFF-state. Operation of the OE input  
does not affect the state of the latches.  
DESCRIPTION  
The 74AHC/AHCT573 is functionally identical to the  
74AHC/AHCT533, 74AHC/AHCT563 and  
74AHC/AHCT373, but the 74AHC/AHCT533 and  
74AHC/AHCT563 have inverted outputs and the  
74AHC/AHCT563 and 74AHC/AHCT373 have a different  
pin arrangement.  
The 74AHC/AHCT573 are high-speed Si-gate CMOS  
devices and are pin compatible with low power Schottky  
TTL (LSTTL). They are specified in compliance with  
JEDEC standard No. 7A.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
AHC  
AHCT  
tPHL/tPLH  
propagation delay Dn to Qn; CL = 15 pF; VCC = 5 V  
LE to Qn  
3.9  
3.5  
ns  
CI  
input capacitance  
output capacitance  
VI = VCC or GND  
3.0  
4.0  
12  
3.0  
4.0  
18  
pF  
pF  
pF  
CO  
CPD  
power dissipation  
capacitance  
CL = 50 pF; f = 1 MHz;  
notes 1 and 2  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
N = total load switching outputs;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
2. The condition is VI = GND to VCC  
.
2003 Dec 08  
2
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
FUNCTION TABLE  
See note 1.  
INPUT  
OUTPUT  
INTERNAL  
LATCH  
OPERATING MODE  
OE  
LE  
Dn  
Q0 to Q7  
Enable and read register  
(transparent mode)  
L
L
H
H
L
L
L
L
L
H
I
L
H
L
L
H
L
Latch and read register  
L
L
h
l
H
L
H
Z
Z
Latch register and disable  
outputs  
H
H
h
H
Note  
1. H = HIGH voltage level;  
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;  
L = LOW voltage level;  
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;  
Z = high-impedance OFF-state.  
ORDERING INFORMATION  
PACKAGE  
TYPE NUMBER  
PINS  
20  
PACKAGE  
SO20  
MATERIAL  
plastic  
CODE  
74AHC573D  
SOT163-1  
SOT163-1  
SOT360-1  
SOT360-1  
74AHCT573D  
74AHC573PW  
74AHCT573PW  
20  
SO20  
plastic  
20  
TSSOP20  
TSSOP20  
plastic  
20  
plastic  
2003 Dec 08  
3
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
PINNING  
PIN  
SYMBOL  
DESCRIPTION  
1
OE  
3-state output enable input (active  
LOW)  
2
3
4
5
6
7
8
9
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
GND  
LE  
data input  
handbook, halfpage  
data input  
OE  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
V
CC  
data input  
Q0  
Q1  
Q2  
Q3  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
data input  
data input  
data input  
data input  
573  
15 Q4  
14 Q5  
13 Q6  
data input  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
ground (0 V)  
latch enable input (active HIGH)  
3-state latch output  
3-state latch output  
3-state latch output  
3-state latch output  
3-state latch output  
3-state latch output  
3-state latch output  
3-state latch output  
supply voltage  
Q7  
Q6  
Q5  
Q4  
Q3  
Q2  
Q1  
Q0  
VCC  
12  
11  
Q7  
LE  
GND 10  
MNA388  
Fig.1 Pin configuration SO20 and TSSSOP20.  
handbook, halfpage  
11  
1
C1  
EN  
handbook, halfpage  
11  
LE  
19  
2
3
4
5
6
7
8
9
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
18  
17  
16  
15  
14  
13  
12  
2
19  
1D  
3
4
5
18  
17  
16  
6
7
8
9
15  
14  
13  
12  
OE  
1
MNA389  
MNA390  
Fig.2 Logic symbol.  
Fig.3 IEC logic symbol.  
2003 Dec 08  
4
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
handbook, halfpage  
Q0  
19  
2
3
4
5
6
7
8
9
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Q1 18  
Q2 17  
Q3 16  
Q4 15  
Q5 14  
Q6 13  
LATCH  
1 to 8  
3-STATE  
OUTPUTS  
12  
Q7  
LE  
11  
1
OE  
MNA391  
Fig.4 Functional diagram.  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH  
1
LATCH  
2
LATCH  
3
LATCH  
4
LATCH  
5
LATCH  
6
LATCH  
7
LATCH  
8
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
OE  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
MNA392  
Fig.5 Logic diagram.  
5
2003 Dec 08  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
RECOMMENDED OPERATING CONDITIONS  
74AHC  
74AHCT  
SYMBOL  
PARAMETER  
supply voltage  
CONDITIONS  
UNIT  
MIN. TYP. MAX. MIN. TYP. MAX.  
VCC  
VI  
2.0  
0
5.0  
−
5.5  
4.5  
0
5.0  
−
5.5  
V
input voltage  
5.5  
5.5  
V
VO  
output voltage  
0
−
VCC  
+85  
0
−
VCC  
+85  
V
Tamb  
operating ambient  
temperature  
see DC and AC  
characteristics per device  
−40  
−40  
−
+25  
+25  
−
−40  
+25  
+25  
−
°C  
+125 −40  
+125 °C  
tr, tf  
input rise and fall rates  
VCC = 3.3 V ±0.3 V  
VCC = 5 V ±0.5 V  
100  
20  
−
−
−
ns/V  
ns/V  
−
−
−
20  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).  
SYMBOL  
PARAMETER  
supply voltage  
CONDITIONS  
MIN. MAX. UNIT  
VCC  
VI  
−0.5 +7.0  
−0.5 +7.0  
V
input voltage  
V
IIK  
input diode current  
output diode current  
VI < −0.5 V; note 1  
−
−
−
−20  
±20  
±25  
mA  
mA  
mA  
IOK  
IO  
VO < −0.5 V or VO > VCC + 0.5 V; note 1  
−0.5 V < VO < VCC + 0.5 V  
output source or sink  
current  
ICC  
Tstg  
Ptot  
VCC or GND current  
storage temperature  
power dissipation  
−
±75  
mA  
−65  
−
+150 °C  
500 mW  
Tamb = −40 to +125 °C; note 2  
Notes  
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. For SO20packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.  
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.  
2003 Dec 08  
6
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
DC CHARACTERISTICS  
74AHC type  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
TEST CONDITIONS  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
OTHER  
VCC (V)  
Tamb = 25 °C  
VIH  
HIGH-level input voltage  
LOW-level input voltage  
2.0  
1.5  
−
−
−
−
−
−
−
−
−
V
3.0  
5.5  
2.0  
3.0  
5.5  
2.1  
3.85  
−
V
V
V
V
V
VIL  
0.5  
−
0.9  
−
1.65  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = −50 µA  
IO = −50 µA  
IO = −50 µA  
IO = −4.0 mA  
IO = −8.0 mA  
VI = VIH or VIL  
IO = 50 µA  
2.0  
3.0  
4.5  
3.0  
4.5  
1.9  
2.0  
3.0  
4.5  
−
−
−
−
−
−
V
V
V
V
V
2.9  
4.4  
2.58  
3.94  
−
VOL  
LOW-level output  
voltage  
2.0  
3.0  
4.5  
3.0  
4.5  
5.5  
5.5  
−
−
−
−
−
−
−
0
0
0
−
−
−
−
0.1  
V
IO = 50 µA  
0.1  
V
IO = 50 µA  
0.1  
V
IO = 4.0 mA  
IO = 8.0 mA  
VI = VCC or GND  
0.36  
0.36  
0.1  
V
V
ILI  
input leakage current  
µA  
µA  
IOZ  
3-state output OFF  
current  
VI = VIH or VIL;  
VO = VCC or GND  
±0.25  
ICC  
CI  
quiescent supply current VI = VCC or GND; IO = 0 5.5  
input capacitance  
−
−
−
4.0  
10  
µA  
−
3
pF  
2003 Dec 08  
7
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
TEST CONDITIONS  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
OTHER  
VCC (V)  
Tamb = −40 to +85 °C  
VIH HIGH-level input voltage  
2.0  
3.0  
5.5  
2.0  
3.0  
5.5  
1.5  
−
−
−
−
−
−
−
−
−
V
2.1  
3.85  
−
V
V
V
V
V
VIL  
LOW-level input voltage  
0.5  
−
0.9  
−
1.65  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = −50 µA  
IO = −50 µA  
IO = −50 µA  
IO = −4.0 mA  
IO = −8.0 mA  
VI = VIH or VIL  
IO = 50 µA  
2.0  
3.0  
4.5  
3.0  
4.5  
1.9  
2.9  
4.4  
2.48  
3.8  
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
VOL  
LOW-level output  
voltage  
2.0  
3.0  
4.5  
3.0  
4.5  
5.5  
5.5  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1  
V
IO = 50 µA  
0.1  
V
IO = 50 µA  
0.1  
V
IO = 4.0 mA  
IO = 8.0 mA  
VI = VCC or GND  
0.44  
0.44  
1.0  
V
V
ILI  
input leakage current  
µA  
µA  
IOZ  
3-state output OFF  
current  
VI = VIH or VIL;  
VO = VCC or GND  
±2.5  
ICC  
CI  
quiescent supply current VI = VCC or GND; IO = 0 5.5  
input capacitance  
−
−
−
−
40  
10  
µA  
−
pF  
2003 Dec 08  
8
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
TEST CONDITIONS  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
OTHER  
VCC (V)  
Tamb = −40 to +125 °C  
VIH HIGH-level input voltage  
2.0  
3.0  
5.5  
2.0  
3.0  
5.5  
1.5  
−
−
−
−
−
−
−
−
−
V
2.1  
3.85  
−
V
V
V
V
V
VIL  
LOW-level input voltage  
0.5  
−
0.9  
−
1.65  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = −50 µA  
IO = −50 µA  
IO = −50 µA  
IO = −4.0 mA  
IO = −8.0 mA  
VI = VIH or VIL  
IO = 50 µA  
2.0  
3.0  
4.5  
3.0  
4.5  
1.9  
2.9  
4.4  
2.48  
3.8  
1.9  
2.9  
4.4  
2.48  
3.8  
−
−
−
−
−
V
V
V
V
V
VOL  
LOW-level output  
voltage  
2.0  
3.0  
4.5  
3.0  
4.5  
5.5  
5.5  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
V
IO = 50 µA  
0.1  
0.1  
0.1  
0.44  
2.0  
±10.0  
V
IO = 50 µA  
V
IO = 4.0 mA  
IO = 8.0 mA  
VI = VCC or GND  
V
V
ILI  
input leakage current  
µA  
µA  
IOZ  
3-state output OFF  
current  
VI = VIH or VIL;  
VO = VCC or GND  
ICC  
CI  
quiescent supply current VI = VCC or GND; IO = 0 5.5  
input capacitance  
−
−
−
−
80  
10  
µA  
−
pF  
2003 Dec 08  
9
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
74AHCT type  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
TEST CONDITIONS  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
OTHER  
VCC (V)  
Tamb = 25 °C  
VIH  
VIL  
HIGH-level input voltage  
LOW-level input voltage  
4.5 to 5.5  
4.5 to 5.5  
2.0  
−
−
−
V
−
0.8  
V
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = −50 µA  
4.5  
4.5  
4.4  
4.5  
−
−
V
V
IO = −8.0 mA  
3.94  
−
VOL  
LOW-level output voltage VI = VIH or VIL  
IO = 50 µA  
4.5  
4.5  
5.5  
5.5  
−
−
−
−
0
−
−
−
0.1  
V
IO = 8.0 mA  
0.36  
0.1  
V
ILI  
input leakage current  
VI = VIH or VIL  
µA  
µA  
IOZ  
3-state output OFF  
current  
VI = VIH or VIL;  
±0.25  
VO = VCC or GND per  
input pin; other inputs at  
VCC or GND; IO = 0  
ICC  
quiescent supply current VI = VCC or GND; IO = 0 5.5  
additional quiescent VI = VCC − 2.1 V; other 4.5 to 5.5  
supply current per input inputs at VCC or GND;  
−
−
−
−
4.0  
µA  
∆ICC  
1.35  
mA  
pin  
IO = 0  
CI  
input capacitance  
−
−
3
10  
pF  
Tamb = −40 to +85 °C  
VIH  
VIL  
HIGH-level input voltage  
4.5 to 5.5  
4.5 to 5.5  
2.0  
−
−
−
V
V
LOW-level input voltage  
−
0.8  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = −50 µA  
IO = −8.0 mA  
4.5  
4.5  
4.4  
3.8  
−
−
−
−
V
V
VOL  
LOW-level output voltage VI = VIH or VIL  
IO = 50 µA  
4.5  
4.5  
5.5  
5.5  
−
−
−
−
−
−
−
−
0.1  
V
IO = 8.0 mA  
0.44  
1.0  
V
ILI  
input leakage current  
VI = VIH or VIL  
µA  
µA  
IOZ  
3-state output OFF  
current  
VI = VIH or VIL;  
±2.5  
VO = VCC or GND per  
input pin; other inputs at  
VCC or GND; IO = 0  
ICC  
quiescent supply current VI = VCC or GND; IO = 0 5.5  
additional quiescent VI = VCC − 2.1 V; other 4.5 to 5.5  
supply current per input inputs at VCC or GND;  
−
−
−
−
40  
µA  
∆ICC  
1.5  
mA  
pin  
IO = 0  
CI  
input capacitance  
−
−
−
10  
pF  
2003 Dec 08  
10  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
TEST CONDITIONS  
OTHER  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
V
CC (V)  
Tamb = −40 to +125 °C  
VIH  
VIL  
HIGH-level input voltage  
4.5 to 5.5  
4.5 to 5.5  
2.0  
−
−
−
V
LOW-level input voltage  
−
0.8  
V
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = −50 µA  
4.5  
4.5  
4.4  
−
−
−
−
V
V
IO = −8.0 mA  
3.70  
VOL  
LOW-level output voltage VI = VIH or VIL  
IO = 50 µA  
4.5  
4.5  
5.5  
5.5  
−
−
−
−
−
−
−
−
0.1  
V
IO = 8.0 mA  
0.55  
2.0  
V
ILI  
input leakage current  
VI = VIH or VIL  
µA  
µA  
IOZ  
3-state output OFF  
current  
VI = VIH or VIL;  
±10.0  
VO = VCC or GND per  
input pin; other inputs at  
VCC or GND; IO = 0  
ICC  
quiescent supply current VI = VCC or GND; IO = 0 5.5  
additional quiescent VI = VCC − 2.1 V; other 4.5 to 5.5  
supply current per input inputs at VCC or GND;  
−
−
−
−
80  
µA  
∆ICC  
1.5  
mA  
pin  
IO = 0  
CI  
input capacitance  
−
−
−
10  
pF  
2003 Dec 08  
11  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
AC CHARACTERISTICS  
74AHC573  
GND = 0 V; tr = tf ≤ 3.0 ns.  
TEST CONDITIONS  
WAVEFORMS CL (pF)  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
VCC = 3.0 to 3.6 V  
Tamb = 25 °C; note 1  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
−
−
−
−
−
−
−
−
5.5  
11.0  
ns  
5.8  
5.8  
6.8  
7.8  
8.3  
8.3  
9.7  
−
11.9  
11.5  
11.0  
14.5  
15.4  
15.0  
14.5  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH/tPZL  
tPHZ/tPLZ  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
tPZH/tPZL  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHZ/tPLZ  
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 10  
see Fig.8  
5.0  
3.5  
1.5  
−
−
see Fig.8  
−
−
Tamb = −40 to +85 °C  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
5.0  
3.5  
1.5  
−
−
−
−
−
−
−
−
−
−
−
13.0  
14.0  
13.5  
13.0  
16.5  
17.5  
17.0  
16.5  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH/tPZL  
tPHZ/tPLZ  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
tPZH/tPZL  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHZ/tPLZ  
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 10  
see Fig.8  
−
see Fig.8  
−
2003 Dec 08  
12  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
TEST CONDITIONS  
WAVEFORMS CL (pF)  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
Tamb = −40 to +125 °C  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
1.0  
−
−
−
−
−
−
−
−
−
−
−
14.0  
ns  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
5.0  
3.5  
1.5  
15.0  
14.5  
14.0  
18.5  
19.5  
19.0  
18.5  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH/tPZL  
PHZ/tPLZ  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
t
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
tPZH/tPZL  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHZ/tPLZ  
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 10  
see Fig.8  
−
see Fig.8  
−
VCC = 4.5 to 5.5 V  
Tamb = 25 °C; note 2  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
−
3.9  
4.2  
4.4  
4.6  
5.5  
5.9  
6.3  
7.4  
−
6.8  
7.7  
7.7  
7.7  
8.8  
9.7  
9.7  
9.7  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
−
tPZH/tPZL  
tPHZ/tPLZ  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
−
−
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
−
−
tPZH/tPZL  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
−
tPHZ/tPLZ  
−
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 10  
see Fig.8  
5.0  
3.5  
1.5  
−
−
see Fig.8  
−
−
Tamb = −40 to +85 °C  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
5.0  
3.5  
1.5  
−
−
−
−
−
−
−
−
−
−
−
8.0  
9.0  
9.0  
9.0  
10.0  
11.0  
11.0  
11.0  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH/tPZL  
tPHZ/tPLZ  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
tPZH/tPZL  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHZ/tPLZ  
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 10  
see Fig.8  
−
see Fig.8  
−
2003 Dec 08  
13  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
TEST CONDITIONS  
WAVEFORMS CL (pF)  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
Tamb = −40 to +125 °C  
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
1.0  
−
−
−
−
−
−
−
−
−
−
−
8.5  
ns  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
5.0  
3.5  
1.5  
10.0  
10.0  
10.0  
11.0  
12.5  
12.5  
12.5  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH/tPZL  
PHZ/tPLZ  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
t
tPHL/tPLH propagation delay Dn to Qn2 see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
tPZH/tPZL  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
tPHZ/tPLZ  
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 10  
see Fig.8  
−
see Fig.8  
−
Notes  
1. Typical values at VCC = 3.3 V.  
2. Typical values at VCC = 5.0 V.  
2003 Dec 08  
14  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
74AHCT573  
GND = 0 V; tr = tf ≤ 3.0 ns.  
TEST CONDITIONS  
WAVEFORMS CL (pF)  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
VCC = 4.5 to 5.5 V; note 1  
Tamb = 25 °C  
tPHL/tPLH  
propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
−
−
−
−
−
−
−
−
3.5  
5.5  
ns  
3.9  
4.1  
4.5  
4.9  
5.5  
5.9  
6.4  
−
6.0  
6.5  
6.5  
7.5  
8.5  
8.5  
9.0  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH/tPZL  
tPHZ/tPLZ  
tPHL/tPLH  
tPZH/tPZL  
tPHZ/tPLZ  
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 9  
see Fig.8  
5.0  
3.5  
1.5  
−
−
see Fig.8  
−
−
Tamb = −40 to +85 °C  
tPHL/tPLH  
propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
1
−
−
−
−
−
−
−
−
−
−
−
6.5  
7.0  
7.5  
7.5  
8.5  
9.5  
10.0  
10.0  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
tPZH/tPZL  
tPHZ/tPLZ  
tPHL/tPLH  
1
1
1
1
tPZH/tPZL  
1
tPHZ/tPLZ  
1
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 9  
see Fig.8  
5.0  
3.5  
1.5  
−
see Fig.8  
−
2003 Dec 08  
15  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
TEST CONDITIONS  
WAVEFORMS CL (pF)  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
Tamb = −40 to +125 °C  
tPHL/tPLH  
propagation delay Dn to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay Don to Qn see Figs 6 and 10  
propagation delay LE to Qn see Figs 7 and 10  
propagation delay OE to Qn see Figs 9 and 10  
propagation delay OE to Qn see Figs 9 and 10  
15  
15  
15  
15  
50  
50  
50  
50  
50  
50  
50  
1
1
1
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
7.0  
ns  
7.5  
8.5  
8.5  
9.5  
11.0  
11.0  
11.5  
−
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH/tPZL  
tPHZ/tPLZ  
tPHL/tPLH  
tPZH/tPZL  
tPHZ/tPLZ  
tW  
tsu  
th  
enable pulse width HIGH  
set-up time Dn to LE  
hold time Dn to LE  
see Figs 7 and 9  
see Fig.8  
5.0  
3.5  
1.5  
−
see Fig.8  
−
Note  
1. Typical values at VCC = 5.0 V.  
2003 Dec 08  
16  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
AC WAVEFORMS  
V
handbook, halfpage  
Dn input  
I
V
M
GND  
t
t
PHL  
PLH  
V
OH  
V
Qn output  
M
V
OL  
MNA811  
VI INPUT  
REQUIREMENTS  
VM  
INPUT  
VM  
OUTPUT  
FAMILY  
AHC  
GND to VCC  
50% VCC 50% VCC  
1.5 V 50% VCC  
AHCT  
GND to 3.0 V  
Fig.6 The data input (Dn) to output (Qn) propagation delays.  
1/f  
max  
V
I
LE input  
V
M
t
GND  
t
W
t
PHL  
PLH  
V
OH  
V
Qn output  
M
V
OL  
MNA812  
VI INPUT  
REQUIREMENTS  
VM  
INPUT  
VM  
OUTPUT  
FAMILY  
AHC  
GND to VCC  
50% VCC 50% VCC  
1.5 V 50% VCC  
AHCT  
GND to 3.0 V  
Fig.7 The latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays.  
2003 Dec 08  
17  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
V
I
V
Dn input  
M
GND  
t
t
h
h
t
t
su  
su  
V
I
LE input  
V
M
GND  
MNA814  
VI INPUT  
REQUIREMENTS  
FAMILY  
VM INPUT  
AHC  
GND to VCC  
50% VCC  
1.5 V  
AHCT  
GND to 3.0 V  
The shaded areas indicate when the input is permitted to change for predictable output performance.  
Fig.8 Data set-up and hold times for the Dn input to the LE input.  
V
I
(1)  
V
OE input  
M
GND  
t
t
PZL  
PLZ  
V
CC  
output  
LOW-to-OFF  
OFF-to-LOW  
(2)  
V
M
V
+ 0.3 V  
V
OL  
V
OL  
t
t
PHZ  
PZH  
V
OH  
− 0.3 V  
OH  
output  
(2)  
V
HIGH-to-OFF  
OFF-to-HIGH  
M
GND  
outputs  
enabled  
outputs  
enabled  
outputs  
disabled  
MNA450  
(1)  
(2)  
VI INPUT  
REQUIREMENTS  
VM  
INPUT  
VM  
OUTPUT  
FAMILY  
AHC  
GND to VCC  
50% VCC 50% VCC  
1.5 V 50% VCC  
AHCT  
GND to 3.0 V  
Fig.9 The 3-state enable and disable times.  
18  
2003 Dec 08  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
S1  
V
CC  
open  
GND  
V
CC  
R
=
L
1 kΩ  
V
I
V
O
PULSE  
D.U.T.  
GENERATOR  
C
R
T
L
MNA183  
TEST  
S1  
Definitions for test circuit:  
L = Load resistor.  
t
PLH/tPHL  
open  
VCC  
R
tPLZ/tPZL  
tPHZ/tPZH  
CL = Load capacitance including jig and probe capacitance.  
GND  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.  
Fig.10 Load circuitry for switching times.  
2003 Dec 08  
19  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
PACKAGE OUTLINES  
SO20: plastic small outline package; 20 leads; body width 7.5 mm  
SOT163-1  
D
E
A
X
c
y
H
E
v
M
A
Z
20  
11  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
10  
w
detail X  
e
M
b
p
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
max.  
(1)  
(1)  
(1)  
UNIT  
mm  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3  
0.1  
2.45  
2.25  
0.49  
0.36  
0.32  
0.23  
13.0  
12.6  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.1  
1.0  
0.9  
0.4  
2.65  
0.1  
0.25  
0.01  
1.27  
0.05  
1.4  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.019 0.013 0.51  
0.014 0.009 0.49  
0.30  
0.29  
0.419  
0.394  
0.043 0.043  
0.016 0.039  
0.035  
0.016  
inches  
0.055  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT163-1  
075E04  
MS-013  
2003 Dec 08  
20  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm  
SOT360-1  
D
E
A
X
c
H
v
M
A
y
E
Z
11  
20  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
1
10  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
6.6  
6.4  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.5  
0.2  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT360-1  
MO-153  
2003 Dec 08  
21  
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74AHC573; 74AHCT573  
DATA SHEET STATUS  
DATA SHEET  
STATUS(1)  
PRODUCT  
STATUS(2)(3)  
LEVEL  
DEFINITION  
I
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
II  
Preliminary data Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Relevant changes will  
be communicated via a Customer Product/Process Change Notification  
(CPCN).  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes in the products -  
including circuits, standard cells, and/or software -  
described or contained herein in order to improve design  
and/or performance. When the product is in full production  
(status ‘Production’), relevant changes will be  
Application information  
Applications that are  
communicated via a Customer Product/Process Change  
Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these  
products, conveys no licence or title under any patent,  
copyright, or mask work right to these products, and  
makes no representations or warranties that these  
products are free from patent, copyright, or mask work  
right infringement, unless otherwise specified.  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2003 Dec 08  
22  
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.  
© Koninklijke Philips Electronics N.V. 2003  
SCA75  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
R44/02/pp23  
Date of release: 2003 Dec 08  
Document order number: 9397 750 12156