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INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications  
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information  
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines  
74HC/HCT299  
8-bit universal shift register; 3-state  
December 1990  
Product specification  
File under Integrated Circuits, IC06  
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
The 74HC/HCT299 contain eight edge-triggered D-type  
flip-flops and the interstage logic necessary to perform  
synchronous shift-right, shift-left, parallel load and hold  
operations. The type of operation is determined by the  
mode select inputs (S0 and S1), as shown in the mode  
select table.  
All flip-flop outputs have 3-state buffers to separate these  
outputs (I/O0 to I/O7) such, that they can serve as data  
inputs in the parallel load mode. The serial outputs (Q0 and  
Q7) are used for expansion in serial shifting of longer  
words.  
FEATURES  
• Multiplexed inputs/outputs provide improved bit density  
• Four operating modes:  
– shift left  
– shift right  
– hold (store)  
– load data  
• Operates with output enable or at high-impedance  
OFF-state (Z)  
A LOW signal on the asynchronous master reset input  
(MR) overrides the Sn and clock (CP) inputs and resets the  
flip-flops. All other state changes are initiated by the rising  
edge of the clock pulse. Inputs can change when the clock  
is either state, provided that the recommended set-up and  
hold times, relative to the rising edge of CP, are observed.  
• 3-state outputs drive bus lines directly  
• Can be cascaded for n-bits word length  
• Output capability: bus driver (parallel I/Os),  
standard (serial outputs)  
• ICC category: MSI  
A HIGH signal on the 3-state output enable inputs (OE1 or  
OE2) disables the 3-state buffers and the I/On outputs are  
set to the high-impedance OFF-state. In this condition, the  
shift, hold, load and reset operations can still occur. The  
3-state buffers are also disabled by HIGH signals on both  
S0 and S1, when in preparation for a parallel load  
operation.  
GENERAL DESCRIPTION  
The 74HC/HCT299 are high-speed Si-gate CMOS devices  
and are pin compatible with low power Schottky TTL  
(LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
HC  
HCT  
tPHL/ tPLH  
propagation delay  
CL = 15 pF; VCC = 5 V  
CP to Q0, Q7  
20  
19  
ns  
CP to I/On  
20  
19  
ns  
tPHL  
fmax  
CI  
MR to Q0, Q7 or I/On  
maximum clock frequency  
input capacitance  
20  
23  
ns  
50  
46  
MHz  
pF  
pF  
pF  
3.5  
10  
3.5  
10  
CI/O  
CPD  
input/output capacitance  
power dissipation capacitance per package  
notes 1 and 2  
120  
125  
Notes  
1. CPD is used to determine the dynamic power  
2. For HC the condition is VI = GND to VCC  
dissipation (PD in µW):  
For HCT the condition is VI = GND to VCC − 1.5 V  
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:  
fi = input frequency in MHz  
ORDERING INFORMATION  
fo = output frequency in MHz  
∑ (CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
See “74HC/HCT/HCU/HCMOS Logic Package  
Information”.  
December 1990  
2
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
PIN DESCRIPTION  
PIN NO.  
1, 19  
SYMBOL  
S0, S1  
NAME AND FUNCTION  
mode select inputs  
2, 3  
OE1, OE2  
3-state output enable inputs (active LOW)  
7, 13, 6, 14, 5, 15, 4, 16 I/O0 to I/O7  
parallel data inputs or 3-state parallel outputs (bus driver)  
serial outputs (standard output)  
asynchronous master reset input (active LOW)  
ground (0 V)  
8, 17  
9
Q0, Q7  
MR  
10  
11  
GND  
DSR  
CP  
serial data shift-right input  
12  
18  
20  
clock input (LOW-to-HIGH, edge-triggered)  
serial data shift-left input  
DSL  
VCC  
positive supply voltage  
Fig.1 Pin configuration.  
Fig.2 Logic symbol.  
Fig.3 IEC logic symbol.  
December 1990  
3
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
Fig.4 Functional diagram.  
MODE SELECT TABLE  
INPUTS  
RESPONSE  
asynchronous reset; Q0−Q7 = LOW  
MR  
S1  
S0  
CP  
L
X
X
X
H
H
H
H
H
L
H
L
H
H
L
↑
↑
↑
X
parallel load; I/On → Qn  
shift right; DSR → Q0, Q0 → Q1 etc.  
shift left; DSL → Q7, Q7 → Q6 etc.  
hold  
L
Notes  
1. H = HIGH voltage level  
L = LOW voltage level  
X = don’t care  
↑ = LOW-to-HIGH CP transition  
December 1990  
4
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
Fig.5 Logic diagram.  
December 1990  
5
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
DC CHARACTERISTICS FOR 74HC  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: bus driver (parallel I/Os)  
standard (serial outputs)  
ICC category: MSI  
AC CHARACTERISTICS FOR 74HC  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HC  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
−40 to +85 −40 to +125  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
CP to Q0, Q7  
66 200  
24 40  
19 34  
250  
50  
43  
300  
60  
51  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2.0 Fig.6  
4.5  
6.0  
t
PHL/ tPLH propagation delay  
CP to I/On  
66 200  
24 40  
19 34  
250  
50  
43  
300  
60  
51  
2.0 Fig.6  
4.5  
6.0  
tPHL  
/
propagation delay  
66 200  
24 40  
19 34  
250  
50  
43  
300  
60  
51  
2.0 Fig.7  
4.5  
6.0  
MR to Q0, Q7 or I/On  
tPZH  
tPZL  
tPHZ  
tPLZ  
3-state output enable time  
OEn to I/On  
50 155  
18 31  
14 26  
195  
39  
33  
235  
47  
40  
2.0 Fig.9  
4.5  
6.0  
3-state output enable time  
OEn to I/On  
41 130  
15 26  
12 22  
165  
33  
28  
195  
39  
33  
2.0 Fig.9  
4.5  
6.0  
3-state output disable time  
OEn to I/On  
66 185  
24 37  
19 31  
230  
46  
39  
280  
56  
48  
2.0 Fig.9  
4.5  
6.0  
3-state output disable time  
OEn to I/On  
55 155  
20 31  
16 26  
195  
39  
33  
235  
47  
40  
2.0 Fig.9  
4.5  
6.0  
t
t
THL/ tTLH output transition time  
bus driver (I/On)  
14 60  
75  
15  
13  
90  
18  
15  
2.0 Fig.6  
4.5  
6.0  
5
4
12  
10  
THL/ tTLH output transition time  
standard (Q0, Q7)  
19 75  
95  
19  
16  
110  
22  
19  
2.0 Fig.6  
4.5  
6.0  
7
6
15  
13  
tW  
clock pulse width  
HIGH or LOW  
80  
16  
14  
17  
6
5
100  
20  
17  
120  
24  
20  
2.0 Fig.6  
4.5  
6.0  
tW  
master reset pulse width  
LOW  
80  
16  
14  
19  
7
6
100  
20  
17  
120  
24  
20  
2.0 Fig.7  
4.5  
6.0  
December 1990  
6
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
Tamb (°C)  
TEST CONDITIONS  
74HC  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
−40 to +85 −40 to +125  
min. typ. max. min. max. min. max.  
trem  
tsu  
tsu  
tsu  
th  
removal time  
MR to CP  
5
5
5
−14  
−5  
−4  
5
5
5
5
5
5
ns  
ns  
ns  
ns  
ns  
ns  
2.0 Fig.7  
4.5  
6.0  
set-up time  
DSR, DSL to CP  
100 33  
20  
17  
125  
25  
21  
150  
30  
26  
2.0 Fig.6  
4.5  
6.0  
12  
10  
set-up time  
S0, S1 to CP  
100 33  
20  
17  
125  
25  
21  
150  
30  
26  
2.0 Fig.8  
4.5  
6.0  
12  
10  
set-up time  
I/On to CP  
125 39  
25  
21  
155  
31  
26  
190  
38  
32  
2.0 Fig.6  
4.5  
6.0  
14  
11  
hold time  
I/On, DSR, DSL to CP  
0
0
0
−14  
−5  
−4  
0
0
0
0
0
0
2.0 Fig.6  
4.5  
6.0  
th  
hold time  
S0, S1 to CP  
0
0
0
−28  
−10  
−8  
0
0
0
0
0
0
2.0 Fig.8  
4.5  
6.0  
fmax  
maximum clock pulse  
frequency  
5.0 15  
4.0  
20  
24  
3.4  
17  
20  
MHz 2.0 Fig.6  
25  
29  
45  
54  
4.5  
6.0  
December 1990  
7
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: bus driver (parallel I/Os)  
standard (serial outputs)  
ICC category: MSI  
Note to HCT types  
The value of additional quiescent supply current (∆ICC) for unit load of 1 is given in the family specifications.  
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
I/On  
0.25  
0.25  
0.60  
0.25  
0.30  
DSR, DSL  
CP, S0  
MR, S1  
OEn  
December 1990  
8
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
−40 to +85 −40 to +125  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
CP to Q0, Q7  
22  
22  
27  
19  
24  
20  
5
37  
37  
46  
30  
37  
32  
12  
15  
46  
46  
58  
38  
46  
40  
15  
19  
56  
56  
69  
45  
56  
48  
18  
22  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4.5 Fig.6  
4.5 Fig.6  
4.5 Fig.7  
4.5 Fig.9  
4.5 Fig.9  
4.5 Fig.9  
4.5 Fig.6  
4.5 Fig.6  
4.5 Fig.6  
4.5 Fig.7  
4.5 Fig.7  
4.5 Fig.6  
4.5 Fig.8  
4.5 Fig.6  
4.5 Fig.8  
t
PHL/ tPLH propagation delay  
CP to I/On  
tPHL  
propagation delay  
MR to Q0, Q7 or I/On  
tPZH/ tPZL 3-state output enable time  
OEn to I/On  
tPHZ  
3-state output disable time  
OEn to I/On  
tPLZ  
3-state output disable time  
OEn to I/On  
t
t
THL/ tTLH output transition time  
bus driver (I/On)  
THL/ tTLH output transition time  
standard (Q0, Q7)  
7
tW  
clock pulse width  
HIGH or LOW  
20  
20  
10  
25  
32  
0
10  
11  
2
25  
25  
9
30  
30  
11  
38  
48  
0
tW  
master reset pulse width  
LOW  
trem  
tsu  
tsu  
th  
removal time  
MR to CP  
set-up time  
I/On, DSR, DSL to CP  
14  
18  
−11  
−17  
42  
31  
40  
0
set-up time  
S0, S1 to CP  
hold time  
I/On, DSR, DSL to CP  
th  
hold time  
0
0
0
S0, S1 to CP  
fmax  
maximum clock pulse  
frequency  
25  
20  
17  
MHz 4.5 Fig.6  
December 1990  
9
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
AC WAVEFORMS  
I/O ,D ,D  
SR SL  
n
(1)  
V
M
INPUTS  
t
t
su  
su  
t
t
h
h
1/ f  
max  
(1)  
CP INPUT  
V
M
t
t
W
t
PHL  
PLH  
The shaded areas indicate when the input is  
permitted to change for predictable output  
performance.  
I/O ,Q ,Q  
7
n
0
(1)  
V
M
OUTPUTS  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT : VM = 1.3 V; VI = GND to 3 V.  
t
t
MBA335  
THL  
TLH  
Fig.6 Waveforms showing the clock (CP) to output (I/On, Q0, Q7) propagation delays, the clock pulse width, the  
I/On, DSR and DSL to CP set-up and hold times, the output transition times and the maximum clock  
frequency.  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT : VM = 1.3 V; VI = GND to 3 V.  
Fig.7 Waveforms showing the master reset (MR) pulse width (LOW), the master reset to output (I/On, Q0, Q7)  
propagation delays and the master reset to clock (CP) removal time.  
December 1990  
10  
Philips Semiconductors  
Product specification  
8-bit universal shift register; 3-state  
74HC/HCT299  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT : VM = 1.3 V; VI = GND to 3 V.  
Fig.8 Waveforms showing the set-up and hold times from the mode control inputs (S0, S1) to the clock (CP).  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT : VM = 1.3 V; VI = GND to 3 V.  
Fig.9 Waveforms showing the 3-state enable and disable times for OEn inputs.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
December 1990  
11