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6812  
DABiC-IV, 20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
The A6812– devices combine a 20-bit CMOS shift register,  
accompanying data latches and control circuitry with bipolar sourcing  
outputs and pnp active pull downs. Designed primarily to drive  
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also  
allow these devices to be used in many other peripheral power driver  
applications. The A6812– features an increased data input rate (com-  
pared with the older UCN/UCQ5812-F) and a controlled output slew  
rate.  
A6812xA  
LOGIC  
SUPPLY  
LOAD  
SUPPLY  
28  
27  
1
2
3
V
V
DD  
BB  
SERIAL  
DATA IN  
SERIAL  
DATA OUT  
26 OUT  
25 OUT  
24 OUT  
23 OUT  
OUT  
20  
1
2
3
4
5
4
OUT  
19  
The CMOS shift register and latches allow direct interfacing with  
microprocessor-based systems. With a 3.3 V or 5 V logic supply, they  
will operate to at least 10 MHz.  
5
6
OUT  
18  
OUT  
17  
OUT  
16  
22  
21  
20  
19  
18  
OUT  
OUT  
OUT  
OUT  
OUT  
7
8
A CMOS serial data output permits cascade connections in applica-  
tions requiring additional drive lines. Similar devices are available as  
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32  
bits).  
OUT  
15  
6
7
8
9
OUT  
14  
9
10  
11  
12  
13  
14  
OUT  
13  
The A6812– output source drivers are npn Darlingtons, capable of  
sourcing up to 40 mA. The controlled output slew rate reduces electro-  
magnetic noise, which is an important consideration in systems that  
include telecommunications and/or microprocessors and to meet  
government emissions regulations. For inter-digit blanking, all output  
drivers can be disabled and all sink drivers turned on with a BLANK-  
ING input high. The pnp active pull-downs will sink at least 2.5 mA.  
OUT  
OUT  
12  
11  
17 OUT  
10  
16  
BLANKING  
GROUND  
BLNK  
STROBE  
ST  
15 CLOCK  
CLK  
Dwg. PP-029-7  
Two temperature ranges are available for optimum performance in  
commercial (suffix S-) or industrial (suffix E-) applications. Package  
styles are provided for through-hole DIP (suffix -A), surface-mount  
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix  
-EP). Copper lead frames, low logic-power dissipation, and low  
output-saturation voltages allow these drivers to source 25 mA from all  
outputs continuously to more than +43°C (suffix -LW), +61°C (suffix  
-EP), or +77°C (suffix -A).  
ABSOLUTE MAXIMUM RATINGS  
at TA = 25°C  
Logic Supply Voltage, VDD ................... 7.0 V  
Driver Supply Voltage, VBB ................... 60 V  
Continuous Output Current Range,  
I
OUT ......................... -40 mA to +15 mA  
Input Voltage Range,  
VIN ....................... -0.3 V to VDD + 0.3 V  
Package Power Dissipation,  
PD ........................................ See Graph  
Operating Temperature Range, TA  
(Suffix ‘E–’) .................. -40°C to +85°C  
(Suffix ‘S–’) .................. -20°C to +85°C  
Storage Temperature Range,  
TS ............................... -55°C to +125°C  
FEATURES  
I Controlled Output Slew Rate  
I High-Speed Data Storage  
I 60 V Minimum  
Output Breakdown  
I High Data Input Rate  
I PNP Active Pull-Downs  
I Low Output-Saturation Voltages  
I Low-Power CMOS Logic  
and Latches  
I Improved Replacements  
for TL5812–, UCN5812–,  
and UCQ5812–  
Caution: These CMOS devices have input static  
protection (Class 2) but are still susceptible to  
damage if exposed to extremely high static  
electrical charges.  
Complete part number includes a suffix to identify operating  
temperature range (E- or S-) and package type (-A, -EP, or -LW).  
Always order by complete part number, e.g., A6812SLW .  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
A6812xEP  
A6812xLW  
LOGIC  
SUPPLY  
LOAD  
SUPPLY  
28  
27  
1
2
3
V
V
DD  
BB  
SERIAL  
DATA IN  
SERIAL  
DATA OUT  
26 OUT  
25 OUT  
24 OUT  
23 OUT  
22 OUT  
OUT  
20  
1
2
3
4
5
4
25  
OUT  
19  
5
6
7
8
OUT  
2
OUT  
18  
5
6
OUT  
18  
24  
23  
OUT  
17  
OUT  
16  
7
8
22  
21  
20  
19  
OUT  
15  
21  
20  
19  
18  
OUT  
OUT  
OUT  
OUT  
9
6
7
8
9
OUT  
14  
9
10  
10  
11  
12  
13  
14  
OUT  
13  
11  
OUT  
8
OUT  
12  
OUT  
OUT  
12  
11  
17 OUT  
10  
16  
BLANKING  
GROUND  
BLNK  
STROBE  
ST  
Dwg. PP-059-1  
15 CLOCK  
CLK  
TYPICAL INPUT CIRCUIT  
Dwg. PP-029-8  
V
DD  
2.5  
2.0  
1.5  
1.0  
0.5  
IN  
S
U
F
F
IX  
'LW  
', R  
= 66  
Dwg. EP-010-5  
θ
JA  
°
C
/W  
TYPICAL OUTPUT DRIVER  
V
BB  
OUT  
N
0
25  
50  
75  
100  
125  
150  
AMBIENT TEMPERATURE IN °C  
Dwg. GP-024-2  
Dwg. EP-021-19  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
Copyright © 2000, Allegro MicroSystems, Inc.  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
FUNCTIONAL BLOCK DIAGRAM  
LOGIC  
SUPPLY  
V
DD  
CLOCK  
SERIAL  
DATA IN  
SERIAL  
DATA OUT  
SERIAL-PARALLEL SHIFT REGISTER  
LATCHES  
STROBE  
BLANKING  
MOS  
BIPOLAR  
LOAD  
SUPPLY  
V
BB  
GROUND  
OUT OUT OUT  
OUT  
N
Dwg. FP-013-1  
1
2
3
TRUTH TABLE  
Serial  
Shift Register Contents  
Serial  
Latch Contents  
Output Contents  
Data Clock  
Input Input I  
Data Strobe  
Output Input  
I
I
...  
I
I
I
I
I
...  
I
I
Blanklng  
I
I
I
... I  
I
N-1 N  
1
2
3
N-1  
N
1
2
3
N-1  
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...  
...  
...  
...  
...  
R
R
R
X
R
R
R
X
R
R
R
X
1
1
2
2
2
3
N-2  
N-2  
N-1  
N-1  
N-1  
N
N-1  
N-1  
N
X
R
X
1
L
R
R
R
...  
...  
...  
R
R
1
2
3
N-1  
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
L
P
L
P
L
... P  
... L  
P
L
1
2
3
N-1  
N
N
1
2
3
N-1  
N
1
2
3
N-1  
N
X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State  
www.allegromicro.com  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
ELECTRICAL CHARACTERISTICS at T = +25°C (A6812S-) or over operating temperature  
A
range (A6812E-), V  
= 60 V unless otherwise noted.  
BB  
Limits @ V  
= 3.3 V Limits @ V  
= 5 V  
DD  
DD  
Characteristic  
Symbol  
Test Conditions  
Mln.  
—
Typ.  
Max.  
-15  
—
Min. Typ. Max.  
<-0.1 -15  
Units  
µA  
V
Output Leakage Current  
Output Voltage  
I
V
= 0 V  
<-0.1  
58.3  
1.0  
—
CEX  
OUT  
OUT  
OUT  
V
V
I
I
= -25 mA  
= 1 mA  
57.5  
—
57.5 58.3  
—
1.5  
—
OUT(1)  
OUT(0)  
OUT(0)  
1.5  
—
—
2.5  
3.3  
—
1.0  
5.0  
—
V
Output Pull-Down Current  
Input Voltage  
I
V
= 5 V to V  
2.5  
2.2  
—
5.0  
mA  
V
OUT  
BB  
V
—
—
—
IN(1)  
IN(0)  
IN(1)  
IN(0)  
V
—
1.1  
1.0  
—
1.7  
V
Input Current  
I
I
V
V
= V  
—
<0.01  
—
<0.01 1.0  
<-0.01 -1.0  
µA  
µA  
V
IN  
DD  
= 0 V  
—
<-0.01 -1.0  
—
IN  
Input Clamp Voltage  
V
I
I
I
= -200 µA  
—
-0.8  
3.05  
0.15  
—
-1.5  
—
—
-0.8  
4.75  
0.15  
—
-1.5  
—
IK  
IN  
Serial Data Output Voltage  
V
V
= -200 µA  
= 200 µA  
2.8  
—
4.5  
—
V
OUT(1)  
OUT(0)  
OUT  
OUT  
0.3  
—
0.3  
—
V
Maximum Clock Frequency  
Logic Supply Current  
f
10*  
—
10*  
—
MHz  
mA  
mA  
mA  
µA  
µs  
µs  
µs  
µs  
µs  
µs  
c
I
All Outputs High  
0.25  
0.25  
3.0  
0.2  
0.7  
1.8  
0.7  
1.8  
—
0.75  
0.75  
6.0  
20  
0.3  
0.3  
3.0  
0.2  
0.7  
1.8  
0.7  
1.8  
—
1.0  
1.0  
6.0  
20  
DD(1)  
DD(0)  
I
All Outputs Low  
—
—
Load Supply Current  
I
I
All Outputs High, No Load  
All Outputs Low  
—
—
BB(1)  
BB(0)  
—
—
Blanking-to-Output Delay  
Strobe-to-Output Delay  
t
C = 30 pF, 50% to 50%  
—
2.0  
3.0  
2.0  
3.0  
12  
—
2.0  
3.0  
2.0  
3.0  
12  
dis(BQ)  
L
t
C = 30 pF, 50% to 50%  
—
—
en(BQ)  
L
t
R = 2.3 kΩ, C ≤ 30 pF  
—
—
p(STH-QL)  
L
L
t
R = 2.3 kΩ, C ≤ 30 pF  
—
—
p(STH-QH)  
L
L
Output Fall Time  
Output Rise Time  
t
t
R = 2.3 kΩ, C ≤ 30 pF  
2.4  
2.4  
2.4  
2.4  
f
L
L
R = 2.3 kΩ, C ≤ 30 pF  
—
12  
—
12  
r
L
L
Output Slew Rate  
dV/dt  
R = 2.3 kΩ, C ≤ 30 pF  
4.0  
—
20  
4.0  
—
20  
V/µs  
L
L
Clock-to-Serial Data Out Delay t  
I
=
200 µA  
—
50  
—
—
50  
—
ns  
p(CH-SQX)  
OUT  
Negative current is defined as coming out of (sourcing) the specified device terminal.  
Typical data is is for design information only and is at TA = +25°C.  
* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
TIMING REQUIREMENTS and SPECIFICATIONS  
(Logic Levels are VDD and Ground)  
C
50%  
B
CLOCK  
A
SERIAL  
DATA IN  
DATA  
50%  
t
p(CH-SQX)  
SERIAL  
DATA OUT  
DATA  
50%  
D
E
50%  
STROBE  
BLANKING  
LOW = ALL OUTPUTS ENABLED  
t
p(STH-QH)  
t
p(STH-QL)  
90%  
DATA  
OUT  
N
10%  
Dwg. WP-029  
HIGH = ALL OUTPUTS BLANKED (DISABLED)  
50%  
BLANKING  
t
dis(BQ)  
t
t
t
f
en(BQ)  
r
90%  
OUT  
N
DATA  
10%  
Dwg. WP-030  
data information towards the SERIAL DATA OUTPUT. The  
SERIAL DATA must appear at the input prior to the rising edge  
of the CLOCK input waveform.  
A. Data Active Time Before Clock Pulse  
(Data Set-Up Time), tsu(D) ...................................... 25 ns  
B. Data Active Time After Clock Pulse  
(Data Hold Time), th(D) ............................................ 25 ns  
C. Clock Pulse Width, tw(CH) ............................................ 50 ns  
Information present at any register is transferred to the  
respective latch when the STROBE is high (serial-to-parallel  
conversion). The latches will continue to accept new data as  
long as the STROBE is held high. Applications where the  
latches are bypassed (STROBE tied high) will require that the  
BLANKING input be high during serial data entry.  
D. Time Between Clock Activation and Strobe, tsu(C) .... 100 ns  
E. Strobe Pulse Width, tw(STH) .......................................... 50 ns  
NOTE – Timing is representative of a 10 MHz clock. Higher  
speeds may be attainable with increased supply voltage;  
operation at high temperatures will reduce the specified  
maximum clock frequency.  
When the BLANKING input is high, the output source  
drivers are disabled (OFF); the pnp active pull-down sink  
drivers are ON. The information stored in the latches is not  
affected by the BLANKING input. With the BLANKING input  
low, the outputs are controlled by the state of their respective  
latches.  
Serial Data present at the input is transferred to the shift  
register on the logic “0” to logic “1” transition of the CLOCK  
input pulse. On succeeding CLOCK pulses, the registers shift  
www.allegromicro.com  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
A6812EA & A6812SA  
Dimensions in Inches  
(controlling dimensions)  
0.015  
0.008  
28  
15  
0.700  
MAX  
0.580  
0.485  
0.600  
BSC  
1
2
14  
0.100  
BSC  
3
4
0.005  
MIN  
0.070  
0.030  
1.565  
1.380  
0.250  
MAX  
0.200  
0.115  
0.015  
MIN  
0.022  
0.014  
Dwg. MA-003-28 in  
Dimensions in Millimeters  
(for reference only)  
0.381  
0.204  
28  
15  
17.78  
MAX  
14.73  
12.32  
15.24  
BSC  
1
2
14  
2.54  
BSC  
3
4
0.13  
1.77  
MIN  
0.77  
39.7  
35.1  
6.35  
MAX  
0.39  
MIN  
5.08  
2.93  
0.558  
0.356  
Dwg. MA-003-28 mm  
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.  
2. Lead spacing tolerance is non-cumulative.  
3. Lead thickness is measured at seating plane or below.  
4. Supplied in standard sticks/tubes of 12 devices.  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
A6812EEP & A6812SEP  
(add “TR” to part number for tape and reel)  
Dimensions in Inches  
(controlling dimensions)  
18  
12  
0.013  
0.021  
19  
11  
0.219  
0.191  
0.026  
0.032  
0.456  
0.450  
INDEX AREA  
0.495  
0.485  
0.050  
BSC  
0.219  
0.191  
25  
5
26  
28  
1
4
0.020  
MIN  
0.456  
0.450  
0.165  
0.180  
0.495  
0.485  
Dwg. MA-005-28A in  
Dimensions in Millimeters  
(for reference only))  
18  
12  
0.331  
0.533  
19  
11  
5.56  
4.85  
0.812  
0.661  
11.58  
11.43  
12.57  
12.32  
INDEX AREA  
1.27  
BSC  
5.56  
4.85  
25  
5
26  
28  
1
4
0.51  
MIN  
11.582  
11.430  
4.57  
4.20  
12.57  
12.32  
Dwg. MA-005-28A mm  
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.  
2. Lead spacing tolerance is non-cumulative.  
3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel.  
www.allegromicro.com  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
A6812ELW & A6812SLW  
(add “TR” to part number for tape and reel)  
Dimensions in Inches  
(for reference only)  
28  
15  
0.0125  
0.0091  
0.419  
0.394  
0.2992  
0.2914  
0.050  
0.016  
0.020  
0.013  
1
2
0.050  
BSC  
3
0° TO 8°  
0.7125  
0.6969  
0.0926  
0.1043  
Dwg. MA-008-28A in  
0.0040 MIN.  
Dimensions in Millimeters  
(controlling dimensions)  
28  
15  
0.32  
0.23  
10.65  
10.00  
7.60  
7.40  
1.27  
0.40  
0.51  
0.33  
1
2
1.27  
3
BSC  
0° TO 8°  
18.10  
17.70  
2.65  
2.35  
Dwg. MA-008-28A mm  
0.10 MIN.  
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.  
2. Lead spacing tolerance is non-cumulative.  
3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
The products described here are manufactured under one or more  
U.S. patents or U.S. patents pending.  
Allegro MicroSystems, Inc. reserves the right to make, from time to  
time, such departures from the detail specifications as may be  
required to permit improvements in the performance, reliability, or  
manufacturability of its products. Before placing an order, the user is  
cautioned to verify that the information being relied upon is current.  
Allegro products are not authorized for use as critical components  
in life-support devices or systems without express written approval.  
The information included herein is believed to be accurate and  
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-  
bility for its use; nor for any infringement of patents or other rights of  
third parties which may result from its use.  
www.allegromicro.com  
6812  
20-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
POWER  
INTERFACE DRIVERS  
†
Function  
Output Ratings*  
SERIAL-INPUT LATCHED DRIVERS  
Part Number  
8-Bit (saturated drivers)  
8-Bit  
8-Bit  
8-Bit  
-120 mA  
350 mA  
350 mA  
350 mA  
350 mA  
75 mA  
250 mA  
350 mA  
100 mA  
50 V‡  
50 V  
80 V  
50 V‡  
80 V‡  
17 V  
50 V  
50 V‡  
50 V  
5895  
5821  
5822  
5841  
5842  
6275  
6595  
6A595  
6B595  
8-Bit  
8-Bit (constant-current LED driver)  
8-Bit (DMOS drivers)  
8-Bit (DMOS drivers)  
8-Bit (DMOS drivers)  
10-Bit (active pull-downs)  
-25 mA  
-25 mA  
75 mA  
-25 mA  
60 V  
60 V  
17 V  
60 V  
5810-F and 6809/10  
5811 and 6811  
6276  
12-Bit (active pull-downs)  
16-Bit (constant-current LED driver)  
20-Bit (active pull-downs)  
5812-F and 6812  
32-Bit (active pull-downs)  
32-Bit  
32-Bit (saturated drivers)  
-25 mA  
100 mA  
100 mA  
60 V  
30 V  
40 V  
5818-F and 6818  
5833  
5832  
PARALLEL-INPUT LATCHED DRIVERS  
4-Bit  
350 mA  
50 V‡  
5800  
8-Bit  
8-Bit  
-25 mA  
350 mA  
100 mA  
250 mA  
60 V  
50 V‡  
50 V  
50 V  
5815  
5801  
6B273  
6273  
8-Bit (DMOS drivers)  
8-Bit (DMOS drivers)  
SPECIAL-PURPOSE DEVICES  
Unipolar Stepper Motor Translator/Driver  
Addressable 8-Bit Decoder/DMOS Driver  
Addressable 8-Bit Decoder/DMOS Driver  
Addressable 8-Bit Decoder/DMOS Driver  
Addressable 28-Line Decoder/Driver  
1.25 A  
250 mA  
350 mA  
100 mA  
450 mA  
50 V‡  
5804  
6259  
6A259  
6B259  
6817  
50 V  
50 V‡  
50 V  
30 V  
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.  
Negative current is defined as coming out of (sourcing) the output.  
†
‡
Complete part number includes additional characters to indicate operating temperature range and package style.  
Internal transient-suppression diodes included for inductive-load protection.  
115 Northeast Cutoff, Box 15036  
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