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November 2006  
rev 1.6  
ASM1232LP/LPS  
5V µP Power Supply Monitor and Reset Circuit  
•
Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin  
DIP and 8-pin Micro SO packages  
Wide operating temperature -40°C to +85°C (N suffixed  
devices)  
General Description  
The ASM1232LP/LPS is a fully integrated microprocessor  
supervisor. It can halt and restart a “hung-up” microprocessor,  
restart a microprocessor after a power failure. It has a  
watchdog timer and external reset override.  
•
Applications  
•
•
•
•
•
•
Microprocessor Systems  
Computers  
Controllers  
Portable Equipment  
Intelligent Instuments  
Automotive Systems  
A
precision temperature-compensated reference and  
comparator circuits monitor the 5V, VCC input voltage status.  
During power-up or when the VCC power supply falls outside  
selectable tolerance limits, both RESET and RESET become  
active. When VCC rises above the threshold voltage, the reset  
signals remain active for an additional 250ms minimum,  
allowing the power supply and system microprocessor to  
stabilize. The trip point tolerance signal, TOL, selects the trip  
level tolerance to be either 5% or 10%.  
Typical Operating Circuit  
+5V  
Each device has both a push-pull, active HIGH reset output and  
an open drain active LOW reset output. A debounced manual  
reset input, PBRST, activates the reset outputs for a minimum  
period of 250ms.  
10kΩ  
µP  
ASM1232LP/LPS  
I/O  
RESET  
ST  
There is a watchdog timer to stop and restart a microprocessor  
that is “hung-up”. The watchdog timeouts periods are  
selectable: 150ms, 610ms and 1200ms. If the ST input is not  
strobed LOW before the time-out period expires, a reset is  
generated.  
RESET  
TD  
TOL  
GND  
Devices are available in 8-pin DIP, 16-pin SO and compact 8-  
pin MicroSO packages.  
Block Diagram  
ASM1232LP/LPS  
V
TOL  
RESET  
RESET  
CC  
Key Features  
Tolerance Selection  
•
•
•
•
5V supply monitor  
Selectable watchdog period  
Debounce manual push-button reset input  
+
-
Reference  
VCC  
Precision temperature-compensated voltage reference and  
40kΩ  
Push Button  
Debounce  
PBRST  
comparator.  
•
•
•
Power-up, power-down and brown out detection  
250ms minimum reset time  
Active LOW open drain reset output and active HIGH  
push-pull output  
Reset &  
Watchdog Timer  
Voltage Sense  
Comparators  
TD  
ST  
Watchdog Transition  
Detector  
•
Selectable trip point tolerance: 5% or 10%  
GND  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
Pin Configuration  
DIP/SO/MicroSO  
SO  
1
8
VCC  
16 NC  
NC  
PBRST  
1
7
6
5
2
3
VCC  
15  
ST  
ASM1232LP  
ASM1232LPS-2  
ASM1232LPU  
TD  
2
3
PBRST  
NC  
TOL  
NC  
14  
RESET  
RESET  
4
GND  
13 ST  
4
TD  
NC  
ASM1232LPS  
NC  
5
6
12  
11  
10  
9
RESET  
NC  
TOL  
NC  
7
8
RESET  
GND  
Pin Description  
Pin #  
8-Pin Package  
Pin #  
16-Pin Package  
Pin  
Name  
Function  
1
2
2
PBRST  
TD  
Debounced manual pushbutton RESET input.  
Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms  
for TD=Open, and tTD = 1200ms for TD = VCC).  
4
Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC  
trip point tolerance.  
)
3
4
6
8
TOL  
GND  
Ground.  
Active HIGH reset output. RESET is active:  
1. If VCC falls below the reset voltage trip point.  
2. If PBRST is LOW.  
5
9
RESET  
3. If ST is not strobed LOW before the timeout period set by TD expires.  
4. During power-up.  
6
7
8
11  
13  
15  
RESET  
ST  
Active LOW reset output. (See RESET).  
Strobe input.  
VCC  
5V power.  
1,3,5,7,  
10,12,14,16  
-
NC  
No internal connection.  
2 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
Detailed Description  
tR  
The ASM1232LP/LPS monitors the microprocessor or  
microcontroller power supply and generates reset signal,  
both active HIGH and Active LOW, that halt processor  
operation whenever the power supply voltage levels are  
outside a predetermined tolerance.  
V
VCCTP  
CCTP(MAX)  
VCCTP(MIN)  
tRPU  
VCC  
RESET  
RESET  
RESET and RESET outputs  
RESET is an active HIGH signal developed by a CMOS  
push-pull output stage and is the logical opposite to RESET.  
VOH  
VOL  
RESET is an active LOW signal. It is developed with an open  
drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is  
required to connect with the output.  
Figure 1: Timing Diagram : Power Up  
Trip Point Tolerance Selection  
The TOL input is used to determine the level VCC can vary  
tF  
VCC  
below 5V without asserting a reset. With TOL conected to  
VCC, RESET and RESET become active whenever VCC falls  
V
(MAX)  
CCTP  
V
CCTP  
below 4.5V. RESET and RESET become active when the  
VCC falls below 4.75V if TOL is connected to ground.  
V
(MIN)  
CCTP  
After VCC has risen above the trip point set by TOL, RESET  
RESET  
RESET  
tRPD  
and RESET remain active for a minimum time period of  
250ms. On power-down, once VCC falls below the reset  
VOH  
VOL  
threshold RESET stays LOW and is guaranteed to be 0.4V or  
less until VCC drops below 1.2V. The active HIGH reset signal  
Figure 2: Timing Diagram : Power Down  
is valid down to a VCC level of 1.2V also.  
TRIP Point Voltage  
Tolerance  
Select  
(V)  
Tolerance  
Min  
Nom  
Max  
Application Information  
TOL = VCC  
TOL = GND  
Manual Reset Operation  
10%  
5%  
4.25 4.37  
4.5 4.62  
4.49  
4.74  
Push-button switch input, PBRST, allows the user to override  
the internal trip point detection circuits and issue reset  
signals. The pushbutton input is debounced and is pulled  
HIGH through an internal 40kΩ resistor.  
3 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
When PBRST is held LOW for the minimum time tPB, both  
power-up after the supply voltage returns to an in-tolerance  
condition, the reset signal remains active for 250ms  
minimum, allowing the power supply and system  
microprocessor to stabilize. ST pulses as short as 20ns can  
be detected.  
resets become active and remain active for a minimum time  
period of 250ms after PBRST returns HIGH.  
The debounced input is guaranteed to recognize pulses  
greater than 20ms. No external pull-up resistor is required,  
since PBRST is pulled HIGH by an internal 40kΩ resistor.  
Valid  
Strobe  
Valid  
Strobe  
Invalid  
Strobe  
ST  
t
ST  
The PBRST can be driven from a TTL or CMOS logic line or  
shorted to ground with a mechanical switch.  
t
RST  
t
(min)  
t
(max)  
TD  
TD  
t
RESET  
PB  
PBRST  
Note: ST is ignored whenever a reset is active  
V
IH  
t
Figure 5: Timing Diagram: Strobe Input  
PDLY  
V
IL  
Timeouts periods of approximately 150ms, 610ms or  
1,200ms are selected through the TD pin.  
t
RST  
RESET  
RESET  
VOH  
VOL  
Watchdog Time-out Period  
TD Voltage level  
(ms)  
Min  
Nom  
Max  
Figure 3: Timing Diagram: Pushbutton Reset  
GND  
62.5  
250  
500  
150  
610  
250  
1000  
2000  
Floating  
VCC  
5V  
1200  
ASM1232LP/LPS  
1
2
8
7
V
CC  
PBRST  
TD  
The watchdog timer can not be disabled. It must be strobed  
with a high-to-low transition to avoid watchdog timeout and  
reset.  
I/O  
ST  
µP  
3
4
6
TOL  
RESET  
RESET  
5
GND  
RESET  
5V  
ASM1232 LP/LPS  
MREQ  
Figure 4: Application Circuit: Pushbutton Reset  
1
2
8
7
V
CC  
PBRST  
10kΩ  
T
D
ST  
µP  
Watchdog Timer and ST Input  
Decoder  
3
4
6
A watchdog timer stops and restarts a microprocessor that is  
“hung-up”. The µP must toggle the ST input within a set  
period (as selectable through TD input) to verify proper  
software execution. If the ST is not toggled low within the  
minimum timeout period, reset signals become active. In  
TOL  
RESET  
Address  
Bus  
RESET  
5
GND  
Figure 6: Application Circuit: Watchdog Timer  
4 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
Absolute Maximum Ratings  
Parameter  
Min  
-0.5  
-0.5  
Max  
Unit  
V
Voltage on VCC  
7
VCC + 0.5  
VCC + 0.5  
Voltage on ST, TD  
V
Voltage on PBRST, RESET, RESET  
Operating Temperature Range (N suffixed devices)  
Operating Temperature Range (others)  
Soldering Temperature (for 10 sec)  
Storage Temperature  
-0.5  
-40  
0
V
+85  
70  
°C  
°C  
°C  
°C  
+260  
+125  
-55  
ESD rating  
HBM  
MM  
2
200  
KV  
V
Note:  
1. Voltages are measured with respect to ground  
2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended  
periods may affect device reliability.  
DC Electrical Characteristics  
Unless otherwise stated, 4.5V <= VCC<= 5.5V and over the operating temperature range of 0°C to 70°C (-40°C to +85°C. for N devices). All  
voltages are referenced to ground.  
Parameter  
Supply Voltage  
Symbol  
VCC  
VIH  
Conditions  
Min  
Typ  
Max  
Unit  
V
4.5  
2
5.5  
VCC + 0.3  
ST and PBRST Input High Level  
ST and PBRST Input Low Level  
V
VIL  
-0.3  
4.50  
4.25  
62.5  
500  
0.8  
4.74  
4.49  
250  
V
V
CC Trip Point (TOL = GND)  
CC Trip Point (TOL = VCC  
VCCTP  
VCCTP  
tTD  
4.62  
4.37  
V
V
)
V
TD = GND  
Watchdog Timeout Period  
Watchdog Timeout Period  
Watchdog Timeout Period  
Output Voltage  
150  
ms  
ms  
ms  
V
tTD  
TD = VCC  
1200  
610  
2000  
1000  
tTD  
TD Floating  
250  
VOH  
IOH  
V
CC - 0.5  
VCC - 0.1  
I=-500µA, Note 3  
Output = 2.4V, Note 2  
Output = 0.4V  
Output Current  
-8  
-10  
mA  
mA  
IOL  
Output Current  
10  
5 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
Parameter  
Symbol  
IIL  
Conditions  
Min  
Typ  
Max  
1.0  
Unit  
Input Leakage  
Note 1  
Note 3  
Note 1  
-1.0  
µA  
V
VOL  
RESET Low Level  
0.4  
Internal Pull-up Resistor  
Operating Current (CMOS)  
Input Capacitance  
40  
kΩ  
µA  
pF  
pF  
ICC1  
CIN  
30  
5
COUT  
Output Capacitance  
10  
PBRST Manual Reset  
Minimum Low Time  
tPB  
PBRST = VIL  
Note 4  
20  
ms  
tRST  
tST  
Reset Active Time  
ST Pulse Width  
250  
20  
610  
5
1000  
8
ms  
ns  
VCC Fail Detect to RESET or  
RESET  
tRPD  
tF  
µs  
µs  
VCC Slew Rate  
4.75V to 4.25V  
300  
PBRST Stable LOW to RESET and  
RESET Active  
tPDLY  
20  
ms  
V
CC Detect to RESET or RESET  
tRPU  
tR  
tRISE = 5µs  
250  
0
610  
1000  
ms  
ns  
inactive  
VCC Slew Rate  
4.25V to 4.75V  
Notes  
1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor.  
2. RESET is an open drain output.  
3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC  
falls below 2.0V.  
4. Must not exceed the minimum watchdog time-out period (tTD). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.  
6 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
Package Information  
MicroSO (8-Pin)  
Inches  
Millimeteres  
Min  
Max  
Min  
Max  
MicroSO (8-Pin)  
0.044  
A
A1  
A2  
b
0.032  
0.002  
0.030  
0.81  
0.05  
0.76  
1.10  
0.15  
0.97  
0.006  
0.038  
0.012 BSC  
0.30 BSC  
0.65 BSC  
C
0.004  
0.114  
0.008  
0.122  
0.10  
2.90  
0.20  
3.10  
D
e
0.0256 BSC  
0.184  
E
0.200  
0.122  
0.026  
4.67  
2.90  
0.41  
5.08  
3.10  
0.66  
E1  
L
0.114  
0.016  
S
0.0206 BSC  
0.52 BSC  
a
0°  
6°  
0°  
6°  
SO (8-Pin)  
0.069  
0.010  
0.059  
0.020  
0.010  
SO (8-Pin)  
A
A1  
A2  
B
0.053  
0.004  
0.049  
0.012  
0.007  
1.35  
0.10  
1.25  
0.31  
0.18  
1.75  
0.25  
1.50  
0.51  
0.25  
H
E
C
D
E
0.193 BSC  
0.154 BSC  
0.050 BSC  
0.236 BSC  
4.90 BSC  
3.91 BSC  
1.27 BSC  
6.00 BSC  
D
e
H
L
A2  
A
0.016  
0°  
0.050  
8°  
0.41  
0°  
1.27  
8°  
C
θ
e
θ
A1  
L
B
Plastic DIP (8-Pin)  
A
A1  
A2  
b
-
0.210  
-
-
5.33  
-
0.015  
0.115  
0.014  
0.045  
0.008  
0.355  
0.300  
0.240  
0.38  
2.92  
0.36  
1.14  
0.20  
9.02  
7.62  
6.10  
Plastic DIP (8-Pin)  
0.195  
0.022  
0.070  
0.014  
0.400  
0.325  
0.280  
4.95  
0.56  
1.78  
0.36  
10.16  
8.26  
7.11  
b2  
C
D
E
E1  
e
0.100 BSC  
2.54 BSC  
eB  
L
-
0.430  
0.150  
-
10.92  
3.81  
0.115  
2.92  
7 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
SO (16-Pin)  
PIN 1 ID  
1
8
H
E
9
16  
h
D
Seating Plane  
A2  
A
C
θ
0.004  
e
L
A1  
B
SO (16-Pin)*  
Inches  
Millimeter  
Min  
Max  
Min  
Max  
A
A1  
A2  
B
0.053  
0.004  
0.049  
0.013  
0.008  
0.386  
0.150  
0.069  
0.010  
0.059  
0.022  
0.012  
0.394  
0.157  
1.35  
0.10  
1.25  
0.33  
0.19  
9.80  
3.80  
1.75  
0.25  
1.50  
0.53  
0.27  
10.01  
4.00  
C
D
E
e
0.050 BSC  
1.27 BSC  
H
h
0.228  
0.010  
0.016  
0°  
0.244  
0.016  
0.035  
8°  
5.80  
0.25  
0.40  
0°  
6.20  
0.41  
0.89  
8°  
L
θ
* JEDEC Drawing MS-013AA  
8 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
Ordering Information  
Operating  
Temperature  
Range  
Maximum  
Supply  
Current (µA)  
Voltage  
Monitoring  
Application  
Part Number  
Package  
Package Marking  
TIN-LEAD DEVICES  
ASM1232LP  
8L PDIP  
8L PDIP  
0°C to +70°C  
-40° C to +85°C  
0°C to +70°C  
0°C to +70° C  
-40°C to +85°C  
-40°C to +85°C  
0°C to +70°C  
-40°C to +85°C  
30  
30  
30  
30  
30  
30  
30  
30  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
ASM1232LP  
ASM1232LPN  
ASM1232LPS  
ASM1232LPS-2  
ASM1232LPSN  
ASM1232LPSN-2  
ASM1232LP  
ASM1232LPN  
ASM1232LPS  
16L SOIC  
8L SOIC  
16L SOIC  
8L SOIC  
8L MSOP  
8L MSOP  
ASM1232LPS-2  
ASM1232LPSN  
ASM1232LPSN-2  
ASM1232LPU  
ASM1232LPUN  
LEAD FREE DEVICES  
ASM1232LPF  
ASM1232LPN  
8L PDIP  
8L PDIP  
0°C to +70°C  
-40°C to +85°C  
0°C to +70°C  
0°C to +70°C  
-40°C to +85°C  
-40°C to +85°C  
0°C to +70°C  
-40°C to +85°C  
30  
30  
30  
30  
30  
30  
30  
30  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
5V  
ASM1232LPF  
ASM1232LPNF  
ASM1232LPS-2F  
ASM1232LPSF  
ASM1232LPSN-2F  
ASM1232LPSNF  
ASM1232LPF  
ASM1232LPNF  
ASM1232LPS-2F  
ASM1232LPSF  
ASM1232LPSN-2F  
ASM1232LPSNF  
ASM1232LPUF  
ASM1232LPUNF  
8L SOIC  
16L SOIC  
8L SOIC  
16L SOIC  
8L MSOP  
8L MSOP  
ASM1232LPNF  
Note: For parts to be packed in Tape and Reel, add “-T” at the end of the part number.  
9 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice  
November 2006  
rev 1.6  
ASM1232LP/LPS  
Copyright © PulseCore Semiconductor  
All Rights Reserved  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200  
Campbell, CA 95008  
Part Number: ASM1232LP/LPS  
Document Version: 1.6  
Tel: 408-879-9077  
Fax: 408-879-9018  
www.pulsecoresemi.com  
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or  
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of  
their respective companies. PulseCore reserves the right to make changes to this document and its products at any  
time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data  
contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the  
right to change or correct this data at any time, without notice. If the product described herein is under development,  
significant changes to these specifications are possible. The information in this product data sheet is intended to be  
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any  
guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out  
of the application or use of any product described herein, and disclaims any express or implied warranties related to  
the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose,  
merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms  
and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively  
according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey  
a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights  
of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-  
supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the  
user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes  
all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.  
10 of 10  
5V µP Power Supply Monitor and Reset Circuit  
Notice: The information in this document is subject to change without notice