550PK013M450DG--Datasheet/数据表在线中文翻译

Si550

REVISION D

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 MHZ TO 1.4 GHZ

Features

ꢀ

Available with any-rate output ꢀ Internal fixed crystal frequency

Si5602

frequencies from 10 to 945 MHz

and selected frequencies to

1.4 GHz

ensures high reliability and low

aging

ꢀ

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

®

ꢀ

3rd generation DSPLL with

ꢀ

superior jitter performance

3x better frequency stability than

SAW-based oscillators

ꢀ

Lead-free/RoHS-compliant

Ordering Information:

Applications

See page 8.

ꢀ

SONET/SDH

xDSL

10 GbE LAN/WAN

ꢀ

Low-jitter clock generation

Optical modules

Clock and data recovery

ꢀ

Pin Assignments:

See page 7.

Description

(Top View)

®

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike traditional VCXOs, where a different crystal is required for

each output frequency, the Si550 uses one fixed crystal to provide a wide

range of output frequencies. This IC-based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems. The Si550 IC-based VCXO is

factory-configurable for a wide variety of user specifications, including

frequency, supply voltage, output format, tuning slope, and temperature

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating the long lead times associated with custom oscillators.

V_C

V_DD

1

2

3

6

5

4

OE

CLK–

CLK+

GND

Functional Block Diagram

CLK– CLK+

V_DD

Any-rate

10-1400 MHz

DSPLL^®

Fixed

Frequency

XO

Clock Synthesis

ADC

Vc

OE

GND

Rev. 0.6 6/07

Si550

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Min

2.97

2.25

1.71

Typ

3.3

2.5

1.8

Max

3.63

2.75

1.89

Units

1

V

DD

Supply Voltage

V

Supply Current

I

Output enabled

LVPECL

CML

DD

—

130

117

108

98

120

108

99

mA

LVDS

CMOS

90

tristate mode

—

0.75 x V

—

60

—

75

—

2

Output Enable (OE)

V

IH

DD

V

0.5

85

IL

Operating Temperature Range

T

–40

°C

A

Notes:

1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further details.

2. OE pin includes a 17 kΩ resistor to V_DD

.

Table 2. V_CControl Voltage Input

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

1,2,3

Control Voltage Tuning Slope

K

10 to 90% of V

—

33

45

—

ppm/V

V

DD

90

135

180

356

4

Control Voltage Linearity

L

BSL

–5

–10

9.3

500

—

±1

±5

+5

+10

10.7

—

VC

%

Incremental

Modulation Bandwidth

BW

10.0

—

kHz

kΩ

V

V Input Impedance

Z

C

VC

Nominal Control Voltage

V

@ f

V /2

DD

—

CNOM

O

Control Voltage Tuning Range

V

0

V

C

DD

Notes:

1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 8.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. K_Vvariation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with V_Cranging from 10 to 90% of V_DD. Incremental slope

determined with V_Cranging from 10 to 90% of V_DD

.

2

Rev. 0.6

Si550

Table 3. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

LVDS/CML/LVPECL

CMOS

Min

10

Typ

—

Max

Units

1,2,3

f

945

160

O

Nominal Frequency

MHz

10

—

1,4

Temperature Stability

T = –40 to +85 ºC

–20

–50

–100

—

+20

+50

+100

A

ppm

1,4

Absolute Pull Range

Aging

APR

t_OSC

±25

—

±375

±3

ppm

ms

Frequency drift over first year.

Frequency drift over 15 year life.

—

±10

10

5

Power up Time

—

Notes:

1. See Section 3. "Ordering Information" on page 8 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Nominal output frequency set by V_CNOM= V_DD/2.

4. Selectable parameter specified by part number.

5. Time from power up or tristate mode to f_O.

Table 4. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

V

1

LVPECL Output Option

V

O

V_OD

V_SE

swing (diff)

—

V_PP

swing (single-ended)

mid-level

0.55

—

0.95

2

LVDS Output Option

V

1.125

0.5

1.20

0.7

1.275

0.9

V

O

swing (diff)

V_OD

V_PP

2

V_O

CML Output Option

mid-level

—

0.70

0.8 x V_DD

—

V

– 0.75

—

1.20

V_DD

0.4

V

DD

V_OD

V_OH

V_OL

swing (diff)

0.95

—

V_PP

3

CMOS Output Option

I

= 32 mA

OH

V

I_OL= 32 mA

—

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

t

LVPECL/LVDS/CML

—

350

—

ps

ns

CMOS with C = 15 pF

—

1

L

SYM

LVPECL:

LVDS:

CMOS:

V

– 1.3 V (diff)

DD

1.25 V (diff)

/2

45

—

55

%

V

DD

Notes:

1. 50 Ω to V_DD– 2.0 V.

2. R_term= 100 Ω (differential).

3. C_L= 15 pF

Rev. 0.6

3

Si550

Table 5. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Units

1,2,3

Phase Jitter (RMS)

for F > 500 MHz

φ_J

ps

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.26

—

OUT

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.27

0.26

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.32

0.26

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.40

0.27

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.49

0.28

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.87

0.33

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4

Rev. 0.6

Si550

Table 5. CLK± Output Phase Jitter (Continued)

Parameter

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Units

1,2,3

Phase Jitter (RMS)

for F of 125 to 500 MHz

φ_J

ps

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

OUT

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.43

0.34

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.50

0.34

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.59

0.35

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

1.00

0.39

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

Table 6. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

2

Max

—

Units

J

ps

PER

Peak-to-Peak

—

14

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Rev. 0.6

5

Si550

Table 7. CLK± Output Phase Noise (Typical)

Offset Frequency

74.25 MHz

90 ppm/V

LVPECL

491.52 MHz

45 ppm/V

LVPECL

622.08 MHz

135 ppm/V

LVPECL

Units

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–87

–114

–132

–142

–148

–150

n/a

–75

–65

–90

–100

–116

–124

–135

–146

–147

–109

–121

–134

–146

–147

dBc/Hz

10 MHz

100 MHz

Table 8. Absolute Maximum Ratings¹

Parameter

Maximum Operating Temperature

Supply Voltage

Symbol

Rating

Units

T

85

ºC

Volts

ºC

AMAX

V

–0.5 to +3.8

DD

Input Voltage

V

–0.5 to V + 0.3

I

DD

Storage Temperature

T

–55 to +125

2500

S

ESD Sensitivity (HBM, per JESD22-A114)

ESD

Volts

ºC

2

Soldering Temperature (Pb-free profile)

T

260

PEAK

2

Soldering Temperature Time @ T

(Pb-free profile)

t

20–40

seconds

PEAK

P

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from

www.silabs.com/VCXO for further information, including soldering profiles.

Table 9. Environmental Compliance

The Si550 meets the following qualification test requirements.

Parameter

Conditions/Test Method

MIL-STD-883F, Method 2002.3 B

MIL-STD-883F, Method 2007.3 A

MIL-STD-883F, Method 203.8

MIL-STD-883F, Method 1014.7

MIL-STD-883F, Method 2016

Mechanical Shock

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solvents

6

Rev. 0.6

Si550

2. Pin Descriptions

(Top View)

V_C

V_DD

1

2

3

6

5

4

OE

CLK–

CLK+

GND

Table 10. Si550 Pin Descriptions

Type

Name

Function

1

V

Analog Input

Control Voltage

C

Output Enable (Polarity = High):

0 = clock output disabled (outputs tri-stated)

1 = clock output enabled

2

OE*

Input

3

4

GND

Ground

Output

Electrical and Case Ground

Oscillator Output

CLK+

CLK–

(N/A for CMOS)

Complementary Output

(N/C for CMOS)

5

6

V

Power

Power Supply Voltage

DD

*Note: OE includes 17 kΩ pullup resistor to V_DD. See Section 3. "Ordering Information" on page 8 for details on OE polarity

ordering options.

Rev. 0.6

7

Si550

3. Ordering Information

The Si550 supports a variety of options including frequency, temperature stability, tuning slope, output format, and

V

.

Specific device configurations are programmed into the Si550 at time of shipment. Configurations are

DD

specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part

number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool

and for further ordering instructions. The Si550 VCXO series is supplied in an industry-standard, RoHS compliant,

lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.

X

D

G

R

550

XXXMXXX

R = Tape & Reel

Blank = Trays

550 VCXO

Product Family

Operating Temp Range (°C)

–40 to +85 °C

G

Device Revision Letter

Frequency (e.g. 622M080 is 622.080 MHz)

Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213 to

1417 MHz. The position of “M” shifts to denote higher or lower

frequencies. If the frequency of interest requires greater than 6 digit

resolution, a six digit code will be assigned for the specific frequency.

1^stOption Code

V_DDOutput Format Output Enable Polarity

2^ndOption Code

Temperature

Stability

± ppm (max)

Tuning Slope

Minimum APR

A

B

C

D

E

F

G

H

J

K

M

N

P

Q

R

S

T

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

High

Low

Kv

ppm/V (typ)

180

(±ppm) for VDD @

Code

A

B

C

D

E

F

G

H

J

K

M

3.3 V

100

30

2.5 V

75

Note 6

125

30

Note 6

75

300

145

104

220

1.8 V

25

Note 6

75

25

Note 6

50

235

105

70

155

100

50

20

50

20

90

180

90

45

135

356

180

135

150

80

25

100

375

185

130

295

12

100

20

356

33

Note 6

Notes:

1. For best jitter and phase noise performance, always choose the smallest Kv that meets

the application’s minimum APR requirements. Unlike SAW-based solutions which

require higher higher Kv values to account for their higher temperature dependence,

the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-

world PLL designs. See AN255 and AN266 for more information.

2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an

APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all

operating conditions.

U

V

W

Note:

CMOS available to 160 MHz.

3. Nominal Pull range (±) = 0.5 x V_DDx tuning slope.

4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

=0.5 x V_DDx tuning slope – stability – 10 ppm

5. Minimum APR values noted above include worst case values for all parameters.

6. Combination not available.

Example Part Number: 550AF622M080DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with a 3.3 V supply,

LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part

is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.

Figure 1. Part Number Convention

8

Rev. 0.6

Si550

4. Si55x Mark Specification

Figure 2 illustrates the mark specification for the Si550. Table 11 lists the line information.

6

4

5

SiLabs 123

1 2 3 4 5 6 7 8 9 0

R T T T T Y W W +

1

2

3

Figure 2. Mark Specification

Table 11. Si55x Top Mark Description

Description

Line

Position

1–10

1

2

“SiLabs”+ Part Family Number, 5xx (First 3 characters in part number)

1–10

Si550: Option1+Option2+Freq(7)+Temp

Si552, Si554, Si550 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp

3

Trace Code

Position 1

Pin 1 orientation mark (dot)

Product Revision (D)

Position 2

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 3–6

Position 7

Position 8–9

Position 10

Rev. 0.6

9

Si550

5. Outline Diagram and Suggested Pad Layout

Figure 3 illustrates the package details for the Si550. Table 12 lists the values for the dimensions shown in the

illustration.

Figure 3. Si550 Outline Diagram

Table 12. Package Diagram Dimensions (mm)

Dimension

Min

1.45

1.2

Nom

1.65

Max

1.85

1.6

A

b

1.4

c

0.60 TYP.

7.00 BSC.

6.2

D

D1

e

6.10

6.30

2.54 BSC.

5.00 BSC.

4.40

E

E1

L

4.30

1.07

4.50

1.47

1.27

S

1.815 BSC.

0.7 REF.

—

R

aaa

bbb

ccc

ddd

—

0.15

0.10

—

10

Rev. 0.6

Si550

6. 6-Pin PCB Land Pattern

Figure 4 illustrates the 6-pin PCB land pattern for the Si550. Table 13 lists the values for the dimensions shown in

the illustration.

Figure 4. Si550 PCB Land Pattern

Table 13. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

D2

e

5.08 REF

2.54 BSC

4.15 REF

E2

GD

GE

VD

VE

X

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

Y

ZD

ZE

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Rev. 0.6

11

Si550

DOCUMENT CHANGE LIST

Revision 0.3 to Revision 0.4

ꢀ Updated Table 1, “Recommended Operating

Conditions,” on page 2.

ꢁ Added maximum supply current specifications.

ꢁ Specified relationship between temperature at startup

and operation temperature.

ꢀ Added Output Enable active polarity as an option in

Figure 1, “Part Number Convention,” on page 8.

Revision 0.4 to Revision 0.5

ꢀ Updated Note 3 in Table 1, “Recommended

Operating Conditions,” on page 2.

ꢀ Updated Figure 1, “Part Number Convention,” on

page 8.

Revision 0.5 to Revision 0.6

ꢀ Updated Table 1, “Recommended Operating

Conditions,” on page 2.

ꢁ Device maintains stable operation over –40 to +85 ºC

operating temperature range.

ꢁ Supply current specifications updated for revision D.

ꢀ Updated Table 4, “CLK± Output Levels and

Symmetry,” on page 3.

ꢁ Updated LVDS differential peak-peak swing

specifications.

ꢀ Updated Table 5, “CLK± Output Phase Jitter,” on

page 4.

ꢀ Updated Table 6, “CLK± Output Period Jitter,” on

page 5.

ꢁ Revised period jitter specifications.

1

ꢀ Updated Table 8, “Absolute Maximum Ratings ,” on

page 6 to reflect the soldering temperature time at

260 ºC is 20–40 sec per JEDEC J-STD-020C.

ꢀ Updated 3. "Ordering Information" on page 8.

ꢁ Changed ordering instructions to revision D.

ꢀ Added 4. "Si55x Mark Specification" on page 9.

12

Rev. 0.6

Si550

NOTES:

Rev. 0.6

13

Si550

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: VCXOinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

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14

Rev. 0.6