S25FL004D0LMAI013--Datasheet/数据表在线中文翻译

S25FL Family (Serial Peripheral Interface)

S25FL004D

4 Megabit CMOS 3.0 Volt Flash Memory

with 50 Mhz SPI Bus Interface

ADVANCE

INFORMATION

Distinctive Characteristics

ARCHITECTURAL ADVANTAGES

PERFORMANCE CHARACTERISTICS

Single power supply operation

Speed

— 50 MHz clock rate (maximum)

Power Saving Standby Mode

— Standby Mode 1 µA (typical)

— Full voltage range: 2.7 to 3.6 V read and program

operations

Memory Architecture

— Eight sectors with 512 Kb each

Program

— Page Program (up to 256 bytes) in 1.5 ms (typical)

— Program cycles are on a page by page basis

Erase

Memory Protection Features

Memory Protection

— W# pin works in conjunction with Status Register Bits

to protect specified memory areas

— Status Register Block Protection bits (BP1, BP0) in

status register configure parts of memory as read-

only

— 0.5 s typical sector erase time

— 4 s typical bulk erase time

Endurance

— 100,000 cycles per sector typical

Data Retention

SOFTWARE FEATURES

SPI Bus Compatible Serial Interface

— 20 years typical

Device ID

— Electronic signature

Process Technology

— Manufactured on 0.25 µm process technology

Package Option

— Industry Standard Pinouts

— 8-pin SO (208mil) package

— 8-contact WSON leadless package (6x5mm)

Publication Number S25FL004D_00 Revision A Amendment 0 Issue Date June 28, 2004

A d v a n c e I n f o r m a t i o n

General Description

The S25FL004D device is a 3.0 Volt (2.7 V to 3.6 V) single power supply Flash memory

device. S25FL004D consists of eight sectors, each with 512 Kb memory.

Data appears on SI input pin when inputting data into the memory and on the SO output

pin when outputting data from the memory. The devices are designed to be programmed

in-system with the standard system 3.0 Volt V_CCsupply.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program in-

struction.

The memory supports Sector Erase and Bulk Erase instructions.

Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V) for both read and write

functions. Internally generated and regulated voltages are provided for the program op-

erations. This device does not require V_PPsupply.

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Table of Contents

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 5

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .6

Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . .7

SPI Modes ...................................................................................................7

Figure 1. Bus Master and Memory Devices on the SPI Bus....... 8

Figure 2. SPI Modes Supported............................................ 8

Operating Features . . . . . . . . . . . . . . . . . . . . . . . . .9

Page Programming .................................................................................. 9

Sector Erase, or Bulk Erase ................................................................. 9

Polling During a Write, Program, or Erase Cycle ........................ 9

Status Register ......................................................................................... 9

Page Program (PP) .................................................................................19

Figure 11. Page Program (PP) Instruction Sequence .............. 20

Sector Erase (SE) ..................................................................................20

Figure 12. Sector Erase (SE) Instruction Sequence................ 21

Bulk Erase (BE) .......................................................................................21

Figure 13. Bulk Erase (BE) Instruction Sequence................... 22

Deep Power Down (DP) ....................................................................22

Figure 14. Deep Power Down (DP) Instruction Sequence........ 23

Release from Deep Power Down (RES) ....................................... 23

Figure 15. Release from Deep Power Down I

nstruction Sequence.......................................................... 24

Release from Deep Power Down and Read Electronic

Signature (RES) ......................................................................................24

Figure 16. Release from Deep Power Down and Read Electronic

Signature (RES) Instruction Sequence ................................. 25

Protection Modes ..................................................................................10

Table 1. Protected Area Sizes (S25FL004D). .........................10

Hold Condition Modes ........................................................................10

Figure 3. Hold Condition Activation...................................... 11

Memory Organization . . . . . . . . . . . . . . . . . . . . . . 12

Table 2. Sector Address Table – S25FL004D .........................12

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Instruction Set. ....................................................13

Write Enable (WREN) .........................................................................14

Figure 4. Write Enable (WREN) Instruction Sequence............. 14

Write Disable (WRDI) ........................................................................14

Figure 5. Write Disable (WRDI) Instruction Sequence ............ 14

Read Status Register (RDSR) ............................................................. 15

Figure 6. Read Status Register (RDSR)

Instruction Sequence ........................................................ 15

Figure 7. Status Register Format......................................... 15

Write Status Register (WRSR) ..........................................................16

Figure 8. Write Status Register (WRSR)

Instruction Sequence ........................................................ 17

Table 4. Protection Modes ..................................................17

Power-up and Power-down . . . . . . . . . . . . . . . . . . 26

Figure 17. Power-Up Timing ............................................... 27

Figure 18. Power-Down and Voltage Drop ............................ 27

Table 5. Power-Up Timing ................................................. 28

Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . 28

Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 28

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6. DC Characteristics ............................................... 29

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 19. AC Measurements I/O Waveform ......................... 30

Table 7. Test Specifications ............................................... 30

Table 8. AC Characteristics ................................................ 31

Figure 20. SPI Mode 0 (0,0) Input Timing............................. 32

Figure 21. SPI Mode 0 (0,0) Output Timing .......................... 32

Figure 22. HOLD# Timing .................................................. 33

Figure 23. Write Protect Setup and Hold Timing during WRSR when

SRWD=1 ......................................................................... 33

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .34

S08 wide—8-pin Plastic Small Outline 208mils Body Width

Package ................................................................................................... 34

8-Contact WSON (6mm x 5mm) Leadless Package .................35

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read Data Bytes (READ) ....................................................................18

Figure 9. Read Data Bytes (READ) Instruction Sequence ........ 18

Read Data Bytes at Higher Speed (FAST_READ) .......................18

Figure 10. Read Data Bytes at Higher Speed

(FAST_READ) Instruction Sequence..................................... 19

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

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A d v a n c e I n f o r m a t i o n

Block Diagram

SRAM

PS

X

D

E

Array - L

Array - R

C

Logic

RD

DATA PATH

IO

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Connection Diagrams

8-contact WSON Package

8-pin Plastic Small Outline Package (SO)

V

8

7

V

1

2

8

7

CS#

SO

1

2

CS#

SO

CC

HOLD#

6

5

SCK

SI

3

4

SCK

SI

3

4

6

5

W#

GND

Input/Output Descriptions

SCK

SI

SO

CS#

W#

HOLD#

=

Serial Clock Input

Serial Data Input

Serial Data Output

Chip Select Input

Write Protect Input

Hold Input

V

Supply Voltage Input

Ground Input

CC

GND

Logic Symbol

V

CC

SO

SI

SCK

CS#

W#

HOLD#

GND

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A d v a n c e I n f o r m a t i o n

Ordering Information

The order number (Valid Combination) is formed by the following:

S25FL

004

D

0L 01

M

A

I

PACKING TYPE

1

3

=

Tube (standard) (Note 1)

13” Tape and Reel (Note 2)

MODEL NUMBER (Additional Ordering Options)

01

= S0-8 Wide (208mil) Package

TEMPERATURE RANGE

I

=

Industrial (–40

°

C to +85 C)

°

PACKAGE MATERIALS

A

F

=

Standard

Lead (Pb) -free (Note 2)

PACKAGE TYPE

M

N

=

8 pin Plastic Small Outline Package

WSON (Note 2)

SPEED

0L

=

50 MHz

DEVICE TECHNOLOGY

D

= 0.25 µm process technology

DENSITY

004

= 4 Mb

DEVICE FAMILY

S25FL

Spansion^TMMemory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory

S25FL Valid Combinations

Base

Ordering

Part Number Option

Speed

Package &

Temperature

Model

Number

Packing

Type

Package Marking

MAI, MFI, NFI

1, 3

FL004D + (Temp) + (Last Digit of Model Number)

(Note 4)

S25FL004D

0L

01

(Note 1)

Notes:

1. Type 1 is standard. Specify other options as required.

2. Contact your local sales office for availability.

3. Package marking omits leading “S25” and speed, package, and leading digit of model number from ordering part

number.

4. If “Last Digit of Model Number” is 3, this signifies a S08-Wide body Lead (Pb)-free package. For example: FL004DI3.

If “Last Digit of Model Number” is 1, this signifies a S08-Wide body standard package. For example: FL004DI1.

Valid Combinations

Valid Combination configuration planned to be supported for this device. Note: Ordering

part number and package marking is pending final product introduction. Contact your sales

representative for further information.

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Signal Description

Signal Data Output (SO): This output signal is used to transfer data serially out

of the device. Data is shifted out on the falling edge of Serial Clock (SCK).

Serial Data Input (SI): This input signal is used to transfer data serially into

the device. It receives instructions, addresses, and the data to be programmed.

Values are latched on the rising edge of Serial Clock (SCK).

Serial Clock (SCK): This input signal provides the timing of the serial interface.

Instructions, addresses, and data present at the Serial Data input (SI) are latched

on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes

after the falling edge of Serial Clock (SCK).

Chip Select (CS#): When this input signal is High, the device is deselected and

Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase

or Write Status Register cycle is in progress, the device will be in Standby mode.

Driving Chip Select (CS#) Low enables the device, placing it in the active power

mode.

After Power-up, a falling edge on Chip Select (CS#) is required prior to the start

of any instruction.

Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communi-

cations with the device without deselecting the device.

During the Hold instruction, the Serial Data Output (SO) is high impedance, and

Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (CS#)

driven Low.

Write Protect (W#): The main purpose of this input signal is to freeze the size

of the area of memory that is protected against program or erase instructions (as

specified by the values in the BP1 and BP0 bits of the Status Register).

SPI Modes

These devices can be driven by a microcontroller with its SPI peripheral running

in either of the two following modes:

CPOL = 0, CPHA = 0

CPOL = 1, CPHA = 1

For these two modes, input data is latched in on the rising edge of Serial Clock

(SCK), and output data is available from the falling edge of Serial Clock (SCK).

The difference between the two modes, as shown in Figure 2, is the clock polarity

when the bus master is in Standby and not transferring data:

SCK remains at 0 for (CPOL = 0, CPHA = 0)

SCK remains at 1 for (CPOL = 1, CPHA = 1)

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

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A d v a n c e I n f o r m a t i o n

SO

SI

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SCK

SCK SO SI

Bus Master

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

CS3 CS2 CS1

CS#

W# HOLD#

CS#

W# HOLD#

CS#

W# HOLD#

Figure 1. Bus Master and Memory Devices on the SPI Bus

Note: The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.

CS#

CPOL CPHA

SCK

0

1

0

1

SCK

SI

MSB

SO

MSB

Figure 2. SPI Modes Supported

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Operating Features

All data into and out of the device is shifted in 8-bit chunks.

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN),

which is one byte, and a Page Program (PP) sequence, which consists of four

bytes plus data. This is followed by the internal Program cycle. To spread this

overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), provided that they lie in

consecutive addresses on the same page of memory.

Sector Erase, or Bulk Erase

The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Be-

fore this can be applied, the bytes of the memory need to be first erased to all

1’s (FFh) before any programming. This can be achieved in two ways: 1) a sector

at a time using the Sector Erase (SE) instruction, or 2) throughout the entire

memory, using the Bulk Erase (BE) instruction.

Polling During a Write, Program, or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP)

or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The

Write in Progress (WIP) bit is provided in the Status Register so that the applica-

tion program can monitor its value, polling it to establish when the previous Write

cycle, Program cycle, or Erase cycle is complete.

Active Power and Standby Power Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power

mode. When Chip Select (CS#) is High, the device is disabled, but could remain

in the Active Power mode until all internal cycles have completed (Program,

Erase, Write Status Register). The device then goes into the Standby Power

mode. The device consumption drops to I . This can be used as an extra Deep

SB

Power Down on mechanism, when the device is not in active use, to protect the

device from inadvertent Write, Program, or Erase instructions.

Status Register

The Status Register contains a number of status and control bits, as shown in Fig-

ure 7, that can be read or set (as appropriate) by specific instructions

WIP bit: The Write In Progress (WIP) bit indicates whether the memory is

busy with a Write Status Register, Program or Erase cycle.

WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal

Write Enable Latch.

BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile.

They define the size of the area to be software protected against Program and

Erase instructions.

SRWD bit: The Status Register Write Disable (SRWD) bit is operated in con-

junction with the Write Protect (W#) signal. The Status Register Write Disable

(SRWD) bit and Write Protect (W#) signal allow the device to be put in the

Hardware Protected mode. In this mode, the non-volatile bits of the Status

Register (SRWD, BP2, BP1, BP0) become read-only bits.

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

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A d v a n c e I n f o r m a t i o n

Protection Modes

The SPI memory device boasts the following data protection mechanisms:

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its

reset state by the following events:

— Power-up

— Write Disable (WRDI) instruction completion

— Write Status Register (WRSR) instruction completion

— Page Program (PP) instruction completion

— Sector Erase (SE) instruction completion

— Bulk Erase (BE) instruction completion

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be con-

figured as read-only. This is the Software Protected Mode (SPM).

The Write Protect (W#) signal works in cooperation with the Status Register

Write Disable (SRWD) bit to enable write-protection. This is the Hardware

Protected Mode (HPM).

Program, Erase and Write Status Register instructions are checked to verify

that they consist of a number of clock pulses that is a multiple of eight, before

they are accepted for execution.

Table 1. Protected Area Sizes (S25FL004D).

Protected

Memory

Area

(Top Level)

Status Register Content

Memory Content

Unprotected Area

BP2 Bit

BP1 Bit

BP0

0

Protected Area

none

0

1

0

1

0

1

00000–7FFFF

00000–6FFFF

00000–5FFFF

00000–3FFFF

none

1/8

1/4

1/2

All

1

70000–7FFFF

60000–7FFFF

40000–7FFFF

00000-7FFFF

0

1

0

All

1

none

All

0

none

All

1

none

Hold Condition Modes

The Hold (HOLD#) signal is used to pause any serial communications with the

device without resetting the clocking sequence. Hold (HOLD#) signal gates the

clock input to the device. However, taking this signal Low does not terminate any

Write Status Register, Program or Erase Cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (CS#)

Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal,

provided that this coincides with Serial Clock (SCK) being Low (as shown in Figure

3).

The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided

that this coincides with Serial Clock (SCK) being Low.

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold

condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising

edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends

after Serial Clock (SCK) next goes Low (Figure 3). During the Hold condition, the

Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial

Clock (SCK) are Don’t Care.

Normally, the device remains selected, with Chip Select (CS#) driven Low, for the

entire duration of the Hold condition. This ensures that the state of the internal

logic remains unchanged from the moment of entering the Hold condition.

If Chip Select (CS#) goes High while the device is in the Hold condition, this has

the effect of resetting the internal logic of the device. To restart communication

with the device, it is necessary to drive Hold (HOLD#) High, and then to drive

Chip Select (CS#) Low. This prevents the device from going back to the Hold

condition.

SCK

HOLD#

Hold

Condition

(standard use)

(non-standard use)

Figure 3. Hold Condition Activation

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

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A d v a n c e I n f o r m a t i o n

Memory Organization

The memory is organized as:

S25FL004D: Eight sectors of 512 Kbit each

Each page can be individually programmed (bits are programmed from 1 to

0).

The device is Sector or Bulk erasable (bits are erased from 0 to 1).

Table 2. Sector Address Table – S25FL004D

Sector

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

Address Range

70000h

60000h

50000h

40000h

30000h

20000h

10000h

00000h

7FFFFh

6FFFFh

5FFFFh

4FFFFh

3FFFFh

2FFFFh

1FFFFh

0FFFFh

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Instructions

All instructions, addresses, and data are shifted in and out of the device, starting

with the most significant bit. Serial Data Input (SI) is sampled on the first rising

edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one-

byte instruction code must be shifted in to the device, most significant bit first,

on Serial Data Input (SI), each bit being latched on the rising edges of Serial

Clock (SCK). The instruction set is listed in Table 3.

Every instruction sequence starts with a one-byte instruction code. Depending on

the instruction, this might be followed by address bytes, or by data bytes, or by

both or none. Chip Select (CS#) must be driven High after the last bit of the in-

struction sequence has been shifted in.

In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read

(FAST_READ) or Release from Deep Power Down and Read Electronic Signature

(RES) instruction, the shifted-in instruction sequence is followed by a data-out

sequence. Chip Select (CS#) can be driven High after any bit of the data-out se-

quence is being shifted out to terminate the transaction.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write

Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc-

tion, Chip Select (CS#) must be driven High exactly at a byte boundary,

otherwise the instruction is rejected, and is not executed. That is, Chip Select

(CS#) must driven High when the number of clock pulses after Chip Select (CS#)

being driven Low is an exact multiple of eight.

All attempts to access the memory array during a Write Status Register cycle,

Program cycle or Erase cycle are ignored, and the internal Write Status Register

cycle, Program cycle or Erase cycle continues unaffected

Table 3. Instruction Set.

One-Byte Instruction

Code

Address

Bytes

Dummy

Byte

Instruction

Description

Data Bytes

Status Register Operations

06H (0000 0110)

WREN

WRDI

RDSR

WRSR

Write Enable

Write Disable

0

04H (0000 0100)

0

Read from Status Register

Write to Status Register

05H (0000 0101)

1 to Infinity

1

01H (0000 0001)

Read Operations

03H (0000 0011)

READ

Read Data Bytes

3

0

1

1 to Infinity

FAST_READ

Read Data Bytes at Higher Speed

0BH (0000 1011)

Erase Operations

SE

BE

Sector Erase

D8H (1101 1000)

C7H (1100 0111)

3

0

Bulk (Chip) Erase

Program Operations

02H (0000 0010)

PP

Page Program

3

0

1 to 256

Deep Power Down Savings Mode Operations

DP

Deep Power Down

B9H (1011 1001)

ABH (1010 1011)

0

Release from Deep Power Down

RES

Release from Deep Power Down and

Read Electronic Signature

ABH (1010 1011)

0

3

1 to Infinity

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S25FL Family (Serial Peripheral Interface) S25FL004D

13

A d v a n c e I n f o r m a t i o n

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 4) sets the Write Enable Latch (WEL)

bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program

(PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The Write

Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending

the instruction code, and then driving Chip Select (CS#) High.

CS#

6

5

7

0

1

2

3

4

SCK

SI

Instruction

High Impedance

SO

Figure 4. Write Enable (WREN) Instruction Sequence

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 5) resets the Write Enable Latch

(WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select

(CS#) Low, sending the instruction code, and then driving Chip Select (CS#)

High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Page Program (PP) instruction completion

Sector Erase (SE) instruction completion

Bulk Erase (BE) instruction completion

CS#

0

3

4

7

6

1 2

5

SCK

SI

Instruction

High Impedance

SO

Figure 5. Write Disable (WRDI) Instruction Sequence

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be

read. The Status Register may be read at any time, even while a Program, Erase,

or Write Status Register cycle is in progress. When one of these cycles is in

progress, it is recommended to check the Write In Progress (WIP) bit before

sending a new instruction to the device. It is also possible to read the Status Reg-

ister continuously, as shown in Figure 6.

CS#

SCK

7

0

2

3

4

5

6

9

11

12 13 14

15

1

8

10

Instruction

SI

Status Register Out

High Impedance

SO

6

4

2

6

7

5

7

5

3

1

0

4

2

7

0

3

1

MSB

Figure 6. Read Status Register (RDSR) Instruction Sequence

b7

b0

WEL

SRWD

0

BP2

BP1

BP0

WIP

Status Register

Write Disable

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

Figure 7. Status Register Format

The status and control bits of the Status Register are as follows:

SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunc-

tion with the Write Protect (W#) signal. The Status Register Write Disable

(SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hard-

ware Protected mode (when the Status Register Write Disable (SRWD) bit is set

to 1, and Write Protect (W#) is driven Low). In this mode, the non-volatile bits

of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the

Write Status Register (WRSR) instruction is no longer accepted for execution.

BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile.

They define the size of the area to be software protected against Program and

Erase instructions. These bits are written with the Write Status Register (WRSR)

instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to

1, the relevant memory area (as defined in Table 1) becomes protected against

Page Program (PP), and Sector Erase (SE) instructions. The Block Protect (BP2,

BP1, BP0) bits can be written provided that the Hardware Protected mode has not

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

15

A d v a n c e I n f o r m a t i o n

been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Pro-

tect (BP2, BP1, BP0) bits are 0.

WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal

Write Enable Latch. When set to 1, the internal Write Enable Latch is set; when

set to 0, the internal Write Enable Latch is reset and no Write Status Register, Pro-

gram or Erase instruction is accepted.

WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy

with a Write Status Register, Program or Erase cycle. This bit is a read only bit

and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in

progress, if it is 0, no such cycle is in progress.

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to

the Status Register. Before it can be accepted, a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable (WREN) instruction

has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select

(CS#) Low, followed by the instruction code and the data byte on Serial Data

Input (SI).

The instruction sequence is shown in Figure 8.

The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b1 and

b0 of the Status Register. Bits b6, b5 are always read as 0.

Chip Select (CS#) must be driven High after the eighth bit of the data byte has

been latched in. If not, the Write Status Register (WRSR) instruction is not exe-

cuted. As soon as Chip Select (CS#) is driven High, the self-timed Write Status

Register cycle (whose duration is t ) is initiated. While the Write Status Register

W

cycle is in progress, the Status Register may still be read to check the value of

the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the

self-timed Write Status Register cycle, and is 0 when it is completed. At some un-

specified time before the cycle is completed, the Write Enable Latch (WEL) is

reset.

The Write Status Register (WRSR) instruction allows the user to change the val-

ues of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that

is to be treated as read-only, as defined in Table 1. The Write Status Register

(WRSR) instruction also allows the user to set or reset the Status Register Write

Disable (SRWD) bit in accordance with the Write Protect (W#) signal. The Status

Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device

to be put in the Hardware Protected Mode (HPM). The Write Status Register

(WRSR) instruction cannot be executed once the Hardware Protected Mode (HPM)

is entered.

16

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

CS#

8

9

10

12 13 14 15

11

4 6

5

7

0

1

2

3

SCK

Status

Register In

Instruction

SI

MSB

High Impedance

SO

Figure 8. Write Status Register (WRSR) Instruction Sequence

Table 4. Protection Modes

Write Protection of the Status

Register

Protected Area

(Note 1)

Unprotected Area

(Note 1)

W# Signal SRWD Bit

Mode

1

0

Status Register is Writeable (if the

WREN instruction has set the WEL ProtectedagainstPage Ready to accept Page

Protected bit)

Software

Program and Erase

(SE, BE)

Program and Sector

Erase Instructions

(SPM)

The values in the SRWD, BP2, BP1

and BP0 bits can be changed

0

Status Register is Hardware write

protected

The values in the SRWD, BP2, BP1

and BP0 bits cannot be changed

Hardware

Protected

(HPM)

ProtectedagainstPage Ready to accept Page

0

1

Program and Erase

(SE, BE)

Program and Sector

Erase Instructions

5. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

The protection features of the device are summarized in Table 4.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its

initial delivery state), it is possible to write to the Status Register provided that

the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction, regardless of the whether Write Protect (W#) is driven High

or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set

to 1, two cases need to be considered, depending on the state of Write Protect

(W#):

If Write Protect (W#) is driven High, it is possible to write to the Status Reg-

ister provided that the Write Enable Latch (WEL) bit has previously been set

by a Write Enable (WREN) instruction.

If Write Protect (W#) is driven Low, it is not possible to write to the Status

Register even if the Write Enable Latch (WEL) bit has previously been set by

a Write Enable (WREN) instruction. (Attempts to write to the Status Register

are rejected, and are not accepted for execution). As a consequence, all the

data bytes in the memory area that are software protected (SPM) by the

Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware

protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM)

can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write

Protect (W#) Low

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

17

A d v a n c e I n f o r m a t i o n

or by driving Write Protect (W#) Low after setting the Status Register Write

Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull

Write Protect (W#) High.

If Write Protect (W#) is permanently tied High, the Hardware Protected Mode

(HPM) can never be activated, and only the Software Protected Mode (SPM),

using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.

Read Data Bytes (READ)

The READ instruction reads the memory at the specified SCK frequency (f

)

SCK

with a maximum speed of 33 MHz.

The device is first selected by driving Chip Select (CS#) Low. The instruction code

for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-

A0), each bit being latched-in during the rising edge of Serial Clock (SCK). Then

the memory contents, at that address, are shifted out on Serial Data Output

(SO), each bit being shifted out, at a frequency f

Serial Clock (SCK).

, during the falling edge of

SCK

The instruction sequence is shown in Figure 9. The first byte addressed can be at

any location. The address is automatically incremented to the next higher ad-

dress after each byte of data is shifted out. The whole memory can, therefore, be

read with a single Read Data Bytes (READ) instruction. When the highest address

is reached, the address counter rolls over to 00000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select

(CS#) High. Chip Select (CS#) can be driven High at any time during data output.

Any Read Data Bytes (READ) instruction, while a Program, Erase, or Write cycle

is in progress, is rejected without having any effect on the cycle that is in

progress.

CS#

0

1

2

3

4

5

6

7

8

9

10

28 23 30 31 32 33 34 35 36 37 38 39

SCK

Instruction

24-Bit Address

2

0

1

22

23

21

3

SI

MSB

Data Out 1

Data Out 2

High Impedance

SO

6

4

2

7

0

7

5

3

1

MSB

Figure 9. Read Data Bytes (READ) Instruction Sequence

Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction reads the memory at the specified SCK frequency

(f ) with a maximum speed of 50 MHz. The device is first selected by driving

SCK

Chip Select (CS#) Low. The instruction code for (FAST_READ) instruction is fol-

lowed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-

in during the rising edge of Serial Clock (SCK). Then the memory contents, at that

18

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

address, are shifted out on Serial Data Output (SO), each bit being shifted out,

at a maximum frequency F

, during the falling edge of Serial Clock (SCK).

SCK

The instruction sequence is shown in Figure 10. The first byte addressed can be

at any location. The address is automatically incremented to the next higher ad-

dress after each byte of data is shifted out. The whole memory can, therefore, be

read with a single (FAST_READ) instruction. When the highest address is

reached, the address counter rolls over to 00000h, allowing the read sequence to

be continued indefinitely.

The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High.

Chip Select (CS#) can be driven High at any time during data output. Any

(FAST_READ) instruction, while an Erase, Program or Write cycle is in progress,

is rejected without having any effects on the cycle that is in progress.

CS#

SCK

33

0

1

2

5

6

7

8

9

29 30

32

38 39 40 41

44 45 46

31

34 35 36 37

Dummy Byte

3

4

10

28

42 43

47

24-Bit

Address

Instruction

23

3

2

22 21

1

0

6

5

4

2

0

1

7

3

SI

DATA OUT 1

DATA OUT 2

High Impedance

3

7

6

4

2

1

0

5

7

SO

MSB

Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence

Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN)

instruction must previously have been executed. After the Write Enable (WREN)

instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low,

followed by the instruction code, three address bytes and at least one data byte

on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 11.

If more than 256 bytes are sent to the device, the addressing will wrap to the

beginning of the same page, previously latched data are discarded and the last

256 data bytes are guaranteed to be programmed correctly within the same

page. If fewer than 256 Data bytes are sent to device, they are correctly pro-

grammed at the requested addresses without having any effects on the other

bytes of the same page.

Chip Select (CS#) must be driven High after the eighth bit of the last data byte

has been latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle

(whose duration is t ) is initiated. While the Page Program cycle is in progress,

PP

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

19

A d v a n c e I n f o r m a t i o n

the Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,

and is 0 when it is completed. At some unspecified time before the cycle is com-

pleted, the Write Enable Latch (WEL) bit is reset.

A Page Program (PP) instruction applied to a page that is protected by the Block

Protect (BP2, BP1, BP0) bits (see Table 1) is not executed.

CS#

SCK

5

8

9

34

3738 39

3536

0

2

4

6

7

10

28 32 33

293031

1

3

24-Bit Address

Data Byte 1

Instruction

4

3

2

22 21

3

2

1

0

7

6

5

1

0

23

SI

MSB

CS#

SCK

5354 55

52

46

4950 51

40

44 45

4748

414243

Data Byte 2

Data Byte 3

Data Byte 256

0

7

6

0

7

6

5

4

3

2

1

0

6

5

4

3

2

1

5

4

3

2

1

SI

MSB

Figure 11. Page Program (PP) Instruction Sequence

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector.

Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN) instruction has been de-

coded, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low,

followed by the instruction code, and three address bytes on Serial Data Input

(SI). Any address inside the Sector (see Table 1) is a valid address for the Sector

Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire du-

ration of the sequence.

The instruction sequence is shown in Figure 12.

Chip Select (CS#) must be driven High after the eighth bit of the last address byte

has been latched in, otherwise the Sector Erase (SE) instruction is not executed.

As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle

(whose duration is tSE) is initiated. While the Sector Erase cycle is in progress,

the Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle,

20

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

and is 0 when it is completed. At some unspecified time before the cycle is com-

pleted, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to any memory area that is protected by

the Block Protect (BP2, BP1, BP0) bits (see Table 1) is not executed.

CS#

SCK

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Instruction

24 Bit Address

1

SI

23 22 21

MSB

Figure 12. Sector Erase (SE) Instruction Sequence

3

2

0

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory.

Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN) instruction has been de-

coded, the device sets the Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, fol-

lowed by the instruction code, on Serial Data Input (SI). No address is required

for the Bulk Erase (BE) instruction. Chip Select (CS#) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 13.

Chip Select (CS#) must be driven High after the eighth bit of the last address byte

has been latched in, otherwise the Bulk Erase (BE) instruction is not executed.

As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle

(whose duration is t ) is initiated. While the Bulk Erase cycle is in progress, the

BE

Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle,

and is 0 when it is completed. At some unspecified time before the cycle is com-

pleted, the Write Enable Latch (WEL) bit is reset.

A Bulk Erase (BE) instruction is executed only if all the Block Protect (BP2, BP1,

BP0) bits (see Table 1) are set to 0. The Bulk Erase (BE) instruction is ignored if

one or more sectors are protected.

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

21

A d v a n c e I n f o r m a t i o n

CS#

SCK

SI

0

1

2

3

4

5

6

7

Instruction

Figure 13. Bulk Erase (BE) Instruction Sequence

Deep Power Down (DP)

The Deep Power Down (DP) instruction puts the device in the lowest current

mode of 1 µA typical.

It is recommended that the standard Standby mode be used for the lowest power

current draw, as well as the Deep Power Down (DP) as an extra software protec-

tion mechanism when this device is not in active use. In this mode, the device

ignores all Write, Program and Erase instructions. Chip Select (CS#) must be

driven Low for the entire duration of the sequence.

The Deep Power Down (DP) instruction is entered by driving Chip Select (CS#)

Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

Driving Chip Select (CS#) High after the eighth bit of the instruction code has

been latched puts the device in Deep Power Down mode. The Deep Power Down

mode can only be entered by executing the Deep Power Down (DP) instruction to

reduce the standby current (from I to I as specified in Table 6). As soon as

SB

DP

Chip Select (CS#) is driven high, it requires a delay of t currently in progress

DP

before Deep Power Down mode is entered.

Once the device has entered the Deep Power Down mode, all instructions are ig-

nored except the Release from Deep Power Down (RES) and Read Electronic

Signature. This releases the device from the Deep Power Down mode. The Re-

lease from Deep Power Down and Read Electronic Signature (RES) instruction

also allows the Electronic Signature of the device to be output on Serial Data Out-

put (SO).

The Deep Power Down mode automatically stops at Power-down, and the device

always powers up in the Standby mode.

Any Deep Power Down (DP) instruction, while an Erase, Program or WRSR cycle

is in progress, is rejected without having any effect on the cycle in progress.

22

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

CS#

t

DP

0

1

2

3

4

5

6

7

SCK

SI

Instruction

Standby Mode

Deep Power Down Mode

Figure 14. Deep Power Down (DP) Instruction Sequence

Release from Deep Power Down (RES)

The Release from Deep Power Down (RES) instruction provides the only way to

exit the Deep Power Down mode. Once the device has entered the Deep Power

Down mode, all instructions are ignored except the Release from Deep Power

Down (RES) instruction. Executing this instruction takes the device out of Deep

Power Down mode.

The Release from Deep Power Down (RES) instruction is entered by driving Chip

Select (CS#) Low, followed by the instruction code on Serial Data Input (SI). Chip

Select (CS#) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Driving Chip Select (CS#) High after the 8-bit instruction byte has been received

by the device, but before the whole of the 8-bit Electronic Signature has been

transmitted for the first time, still insures that the device is put into Standby

mode. If the device was previously in the Deep Power Down mode, though, the

transition to the Stand-by Power mode is delayed by t

, and Chip Select (CS#)

RES

must remain High for at least t

, as specified in Table 8. Once in the Stand-

RES(max)

by Power mode, the device waits to be selected, so that it can receive, decode

and execute instructions.

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

23

A d v a n c e I n f o r m a t i o n

CS#

SCK

7

0

2

3

5

1

4

6

t

RES

Instruction

SI

Standby Mode

Deep Power Down Mode

Figure 15. Release from Deep Power Down Instruction Sequence

Release from Deep Power Down and Read Electronic Signature (RES)

Once the device has entered Deep Power Down mode, all instructions are ignored

except the RES instruction. The RES instruction can also be used to read the 8-

bit Electronic Signature of the device on the SO pin. The RES instruction always

provides access to the Electronic Signature of the device (except while an Erase,

Program or WRSR cycle is in progress), and can be applied even if DP mode has

not been entered. Any RES instruction executed while an Erase, Program or

WRSR cycle is in progress is not decoded, and has no effect on the cycle in

progress.

The device features an 8-bit Electronic Signature, whose value for the S25FL004D

is 12h. This can be read using RES instruction.

The device is first selected by driving Chip Select (CS#) Low. The instruction code

is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (SI)

during the rising edge of Serial Clock (SCK). Then, the 8-bit Electronic Signature,

stored in the memory, is shifted out on Serial Data Output (SO), each bit being

shifted out during the falling edge of Serial Clock (SCK).

The instruction sequence is shown in Figure 16.

The Release from Deep Power Down and Read Electronic Signature (RES) is ter-

minated by driving Chip Select (CS#) High after the Electronic Signature has

been read at least once. Sending additional clock cycles on Serial Clock (SCK),

while Chip Select (CS#) is driven Low, causes the Electronic Signature to be out-

put repeatedly.

When Chip Select is driven High, the device is put in the Stand-by Power mode.

If the device was not previously in the Deep Power Down mode, the transition to

the Stand-by Power mode is immediate. If the device was previously in the Deep

Power Down mode, though, the transition to the Standby mode is delayed by

t

, and Chip Select (CS#) must remain High for at lease t

, as specified

RES

RES(max)

in Table 8. Once in the Stand-by Power mode, the device waits to be selected, so

that it can receive, decode and execute instructions.

24

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

CS#

SCK

2

28 29 30

31 32 33 34

1

8

36 37

35 38

9

0

3

4

5

6

7

10

t

3 Dummy

Bytes

RES

Instruction

SI

3

1

0

2

23 22

21

Electronic ID

High Impedance

7

6

5

4

3

2

1

SO

0

MSB

Standby Mode

Deep Power Down Mode

Figure 16. Release from Deep Power Down and Read Electronic Signature (RES) Instruction Sequence

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

25

A d v a n c e I n f o r m a t i o n

Power-up and Power-down

The device must not be selected at power-up or power-down (that is, CS# must

follow the voltage applied on V ) until V reaches the correct value as follows:

CC

V

(min) at power-up, and then for a further delay of t (as described in

CC PU

Table 5)

V

at power-down

SS

A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe

and proper power-up and power-down.

The device ignores all instructions until a time delay of t (as described in Table

PU

5) has elapsed after the moment that V rises above the minimum V thresh-

CC

old. However, correct operation of the device is not guaranteed if by this time V

CC

is still below V

(min). No Write Status Register, Program or Erase instructions

CC

should be sent until t after V reaches the minimum V threshold (See Figure

PU

CC

17).

At power-up, the device is in Standby mode (not Deep Power Down mode) and

the WEL bit is reset.

During Power-down or voltage drops, the power down must drop below the V

CC

(low) for a period of minimum t for the device to initialize correctly on power

PD

up. (See Figure 18).

Normal precautions must be taken for supply rail decoupling to stabilize the V

CC

feed. Each device in a system should have the V rail decoupled by a suitable

CC

capacitor close to the package pins (this capacitor is generally of the order of 0.1

µF).

At power-down, when V drops from the operating voltage to below the mini-

CC

mum V threshold, all operations are disabled and the device does not respond

CC

to any instructions. (The designer needs to be aware that if a power-down occurs

while a Write, Program or Erase cycle is in progress, data corruption can result.)

26

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Vcc

Vcc^(max)

Vcc^(min)

t_PU

Full Device Access

time

Figure 17. Power-Up Timing

V

CC

V

CC

(max)

No Device Access Allowed

V

(min)

CC

t

Device Access Allowed

PU

V

CC

(low)

t

PD

Time

Figure 18. Power-Down and Voltage Drop

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

27

A d v a n c e I n f o r m a t i o n

Table 5. Power-Up Timing

Symbol

Parameter

(minimum)

Min

Max

Unit

V

2.7

CC(min)

CC

V

(low)

V

CC(low)

t

(min) to device operation

(low) duration

2

ms

ns

PU

PD

t

Initial Delivery State

The device is delivered with all bits set to 1 (each byte contains FFh). The Status

Register contains 00h (all Status Register bits are 0).

Maximum Rating

Stressing the device above the rating listed in the Absolute Maximum Ratings

section below may cause permanent damage to the device. These are stress rat-

ings only and operation of the device at these or any other conditions above those

indicated in the Operating sections of this specification is not implied. Exposure

to Absolute Maximum Rating conditions for extended periods may affect device

reliability

Absolute Maximum Ratings

Ambient Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Voltage with Respect to Ground:

All Inputs and I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to 4.5 V

Operating Ranges

Ambient Operating Temperature (T )

A

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Positive Power Supply

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which functionality of the device is guaranteed.

28

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

DC Characteristics

This section summarizes the DC and AC Characteristics of the device. Designers

should check that the operating conditions in their circuit match the measure-

ment conditions specified in the Test Specifications in Table 7, when relying on

the quoted parameters.

CMOS Compatible

Table 6. DC Characteristics

Parameter Description

Test Conditions

Min

Typ.

Max

Unit

V

Supply Voltage

2.7

3

3.6

V

CC

SCK = 0.1 V /0.9V

33 MHz

CC

mA

I

Active Read Current

CC1

V

= 3.0V

50 MHz

CC

SCK = 0.1 V /0.9V

9

12

CC

I

Active Page Program Current

Active WRSR Current

CS# = V

23

mA

CC2

CC3

CC4

CC5

CC

Active Sector Erase Current

Active Bulk Erase Current

V

= 3.0 V

CC

I

Standby Current

50

5

µA

SB

CS# = V

CC

V

= 3.0 V

CC

I

Deep Power Down Current

1

DP

CS# = V

CC

I

Input Leakage Current

Output Leakage Current

Input Low Voltage

V

= GND to V

1

µA

V

LI

IN

CC

I

V

LO

V

–0.3

0.3 V

CC

IL

IH

V

Input High Voltage

Output Low Voltage

Output High Voltage

0.7 V

V

+ 0.5

V

CC

V

I

= 1.6 mA, V = V

CC CC min

0.4

V

OL

OH

OL

V

= –0.1 mA

V

– 0.2

V

OH

CC

Notes:Typical values are at T_A= 25°C and 3.0 V.

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S25FL Family (Serial Peripheral Interface) S25FL004D

29

A d v a n c e I n f o r m a t i o n

Test Conditions

Input and Output

Timing Reference levels

Input Levels

0.8 V_CC

0.7 V_CC

0.5 V_CC

0.3 V_CC

0.2 V_CC

Figure 19. AC Measurements I/O Waveform

Table 7. Test Specifications

Symbol

Parameter

Load Capacitance

Min

Max

Unit

pF

C

30

L

Input Rise and Fall Times

Input Pulse Voltage

5

ns

0.2 V to 0.8 V

V

CC

Input and Output Timing

Reference Voltages

0.3 V to 0.7 V

V

CC

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

AC Characteristics

Table 8. AC Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

F

SCK Clock Frequency READ instruction

D.C.

33

MHz

SCK

CRT

SCK Clock Frequency for:

FAST_READ, PP, SE, BE, DP, RES, WREN,

WRDI, RDSR, WRSR

F

D.C.

50

MHz

t

Clock Rise Time (Slew Rate)

Clock Fall Time (Slew Rate)

SCK High Time

0.1

9

V/ns

ns

t

CFT

t

WH

t

SCK Low Time

9

WL

t

CS# High Time

100

5

CS

t

(Note 3)

CS# Setup Time

CSS

t

CS# HOLD Time

5

CSH

t

HOLD# Setup Time (relative to SCK)

HOLD# Hold Time (relative to SCK)

HOLD# Setup Time (relative to SCK)

HOLD# Hold Time (relative to SCK)

Output Valid

5

HD

t

5

CD

t

5

HC

CH

5

t

9

V

t

Output Hold Time

0

5

HO

t

Data in Hold Time

HD:DAT

SU:DAT

Data in Setup Time

t

Input Rise Time

5

9

R

t

Input Fall Time

F

t

(Note 3)

HOLD# to Output Low Z

HOLD# to Output High Z

Output Disable Time

LZ

t

HZ

t

DIS

t

(Note 3)

Write Protect Setup Time

Write Protect Hold Time

Release DP Mode

20

WPS

WPH

t

100

t

3

µ

s

RES

t

CS# High to Deep Power Down Mode

Write Status Register Time

Page Programming Time

Sector Erase Time

3

µ

DP

t

20 (Note 2)

2 (Note 2)

0.8 (Note 2)

ns

ms

sec

W

PP

SE

t

1.5 (Note 1)

0.5 (Note 1)

t

Bulk Erase Time

t

4 (Note 1)

7 (Note 2)

sec

BE

Note:

1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0V; 10, 000 cycles; checkerboard

data pattern

2. Under worst-case conditions of 90C; VCC = 2.7V; 100,000 cycles

3. Not 100% tested

June 28, 2004 S25FL004D_00A0

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A d v a n c e I n f o r m a t i o n

AC Characteristics

t_CS

CS#

t_CSS

t_CSH

SCK

t_CRT

t_SU:DAT

t_HD:DAT

t_CFT

SI

MSB IN

LSB IN

High Impedance

SO

Figure 20. SPI Mode 0 (0,0) Input Timing

CS#

t_WH

SCK

SO

t_V

t_WL

t_V

t_DIS

t_HO

LSB OUT

Figure 21. SPI Mode 0 (0,0) Output Timing

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S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

AC Characteristics

CS#

t_HC

t_HD

t_CH

SCK

t_CD

t_HZ

t_LZ

SO

SI

HOLD#

Figure 22. HOLD# Timing

W#

t_WPH

t_WPS

CS#

SCK

SI

High Impedance

SO

Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

33

A d v a n c e I n f o r m a t i o n

Physical Dimensions

S08 wide—8-pin Plastic Small Outline 208mils Body Width Package

34

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004

A d v a n c e I n f o r m a t i o n

Physical Dimensions

8-Contact WSON (6mm x 5mm) Leadless Package

June 28, 2004 S25FL004D_00A0

S25FL Family (Serial Peripheral Interface) S25FL004D

35

A d v a n c e I n f o r m a t i o n

Revision Summary

Revision A (June 28, 2004)

Initial release.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by

FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is

without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of

third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of

the information in this document.

Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this

publication are for identification purposes only and may be trademarks of their respective companies.

36

S25FL Family (Serial Peripheral Interface) S25FL004D

S25FL004D_00A0 June 28, 2004