AT90S1200A-4SI--Datasheet/数据表在线中文翻译

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 89 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Up to 12 MIPS Throughput at 12 MHz

• Data and Non-volatile Program Memory

– 1K Byte of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 64 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

8-bit

Microcontroller

with 1K Byte

of In-System

Programmable

Flash

– One 8-bit Timer/Counter with Separate Prescaler

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In-System Programming

• Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

– Selectable On-chip RC Oscillator for Zero External Components

• Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.0 mA

– Idle Mode: 0.4 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 15 Programmable I/O Lines

– 20-pin PDIP, SOIC and SSOP

• Operating Voltages

AT90S1200

Summary

– 2.7 - 6.0V (AT90S1200-4)

– 4.0 - 6.0V (AT90S1200-12)

• Speed Grades

– 0 - 4 MHz, (AT90S1200-4)

– 0 - 12 MHz, (AT90S1200-12)

Pin Configuration

Rev. 0838HS–AVR–03/02

Note: This is a summary document. A complete document is

available on our web site at www.atmel.com.

1

Description

The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S1200

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with the 32 general purpose working reg-

isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed in

one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

Block Diagram

Figure 1. The AT90S1200 Block Diagram

The architecture supports high-level languages efficiently as well as extremely dense

assembler code programs. The AT90S1200 provides the following features: 1K byte of

In-System Programmable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32

general purpose working registers, internal and external interrupts, programmable

watchdog timer with internal oscillator, an SPI serial port for program downloading and

two software selectable power-saving modes. The Idle Mode stops the CPU while allow-

2

AT90S1200

0838HS–AVR–03/02

AT90S1200

ing the Registers, Timer/Counter, Watchdog and Interrupt system to continue

functioning. The Power-down mode saves the register contents but freezes the Oscilla-

tor, disabling all other chip functions until the next External Interrupt or hardware Reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip In-System Programmable Flash allows the program memory to be repro-

grammed in-system through an SPI serial interface or by a conventional nonvolatile

memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-

grammable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful

microcontroller that provides a highly flexible and cost-effective solution to many embed-

ded control applications.

The AT90S1200 AVR is supported with a full suite of program and system development

tools including: macro assemblers, program debugger/simulators, in-circuit emulators,

and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

Ground pin.

GND

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the

negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out-

put buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7

are used as inputs and are externally pulled low, they will source current if the internal

pull-up resistors are activated. The Port B pins are tri-stated when a reset condition

becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S1200 as listed

on page 30.

Port D (PD6..PD0)

Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The

Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled

low will source current if the pull-up resistors are activated. The Port D pins are tri-stated

when a reset condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S1200 as listed

on page 34.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the

clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

3

0838HS–AVR–03/02

AT90S1200 Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F

$3E

$3D

$3C

$3B

$3A

$39

$38

$37

$36

$35

$34

$33

$32

$31

$30

$2F

$2E

$2D

$2C

$2B

$2A

$29

$28

$27

$26

$25

$24

$23

$22

$21

$20

$1F

$1E

$1D

$1C

$1B

$1A

$19

$18

$17

$16

$15

$14

$13

$12

$11

$10

$0F

...

SREG

Reserved

GIMSK

I

T

H

S

V

N

Z

C

page 11

-

INT0

-

page 15

Reserved

TIMSK

-

TOIE0

TOV0

-

page 16

TIFR

Reserved

MCUCR

Reserved

TCCR0

-

SE

SM

-

ISC01

CS01

ISC00

CS00

page 18

-

CS02

page 21

page 22

TCNT0

Timer/Counter0 (8 Bits)

Reserved

WDTCR

Reserved

EEAR

-

WDE

WDP2

WDP1

EEWE

WDP0

EERE

page 23

-

EEPROM Address Register

EEPROM Data Register

page 25

EEDR

EECR

-

Reserved

PORTB

PORTB7

DDB7

PORTB6

DDB6

PORTB5

DDB5

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

page 29

DDRB

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

Reserved

PORTD

-

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

page 34

DDRD

PIND

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

Reserved

ACSR

$09

$08

…

ACD

-

ACO

ACI

ACIE

-

ACIS1

ACIS0

page 27

Reserved

$00

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

4

AT90S1200

0838HS–AVR–03/02

AT90S1200

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

SUB

SUBI

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

Rd ← Rd v K

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Rd ← Rd • (FFh - K)

Rd ← Rd + 1

Rd ← Rd - 1

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,C,N,V,H

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

None

1

Add with Carry Two Registers

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

ORI

EOR

COM

NEG

SBR

CBR

INC

DEC

TST

CLR

SER

Rd

Rd, K

Rd

Test for Zero or Minus

Clear Register

Set Register

Rd

BRANCH INSTRUCTIONS

RJMP

RCALL

RET

k

Relative Jump

Relative Subroutine Call

Subroutine Return

PC ← PC + k + 1

PC ← STACK

None

I

2

3

4

RETI

Interrupt Return

CPSE

CP

CPC

Rd, Rr

Rd, K

Rr, b

P, b

s, k

k

Compare, Skip if Equal

Compare

Compare with Carry

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

Rd - Rr - C

None

Z,N,V,C,H

None

1/2

1

CPI

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Rd - K

1

SBRC

SBRS

SBIC

SBIS

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b)= 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ← PC + k + 1

if (SREG(s) = 0) then PC ← PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-Flag Set

Branch if T-Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

BRID

k

DATA TRANSFER INSTRUCTIONS

LD

ST

MOV

LDI

IN

Rd, Z

Z, Rr

Rd, Rr

Rd, K

Rd, P

P, Rr

Load Register Indirect

Store Register Indirect

Move between Registers

Load Immediate

In Port

Rd ← (Z)

(Z) ← Rr

Rd ← Rr

Rd ← K

Rd ← P

P ← Rr

None

2

1

OUT

Out Port

5

0838HS–AVR–03/02

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

LSL

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit Load from T to Register

Set Carry

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0) ← C,Rd(n+1) ← Rd(n),C ← Rd(7)

Rd(7) ← C,Rd(n) ← Rd(n+1),C ← Rd(0)

Rd(n) ← Rd(n+1), n = 0..6

Rd(3..0) ← Rd(7..4),Rd(7..4) ← Rd(3..0)

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

C ← 0

N ← 1

N ← 0

Z ← 1

Z ← 0

I ← 1

I ← 0

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

None

Z,C,N,V

None

SREG(s)

T

None

C

N

Z

I

S

V

T

H

None

2

1

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

s

Rr, b

Rd, b

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

Clear T in SREG

T ← 0

H ← 1

H ← 0

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

Sleep

Watchdog Reset

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

6

AT90S1200

0838HS–AVR–03/02

AT90S1200

Ordering Information⁽¹⁾

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

4

2.7 - 6.0V

AT90S1200-4PC

AT90S1200-4SC

AT90S1200-4YC

20P3

20S

Commercial

(0°C to 70°C)

20Y

AT90S1200-4PI

AT90S1200-4SI

AT90S1200-4YI

20P3

20S

Industrial

(-40°C to 85°C)

20Y

12

4.0 - 6.0V

AT90S1200-12PC

AT90S1200-12SC

AT90S1200-12YC

20P3

20S

Commercial

(0°C to 70°C)

20Y

AT90S1200-12PI

AT90S1200-12SI

AT90S1200-12YI

20P3

20S

Industrial

(-40°C to 85°C)

20Y

Note:

1. Order AT90S1200A-XXX for devices with the RCEN Fuse programmed.

Package Type

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

20-lead, 5.3 mm Wide, Plastic Shrink Small Outline Package (SSOP)

20P3

20S

20Y

7

0838HS–AVR–03/02

Packaging Information

20P3

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

C

MIN

–

MAX

5.334

–

NOM

NOTE

SYMBOL

eC

A

–

eB

A1

D

0.381

25.984

7.620

6.096

0.356

1.270

2.921

0.203

–

25.493 Note 2

8.255

E

E1

B

7.112 Note 2

0.559

B1

L

1.551

Notes:

1. This package conforms to JEDEC reference MS-001, Variation AD.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

3.810

C

0.356

eB

eC

e

10.922

0.000

1.524

2.540 TYP

09/28/01

DRAWING NO. REV.

20P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

8

AT90S1200

0838HS–AVR–03/02

AT90S1200

20S

20S, 20-lead, Plastic Gull Wing Small

Outline (SOIC), 0.300" body.

Dimensions in Millineters and (Inches)*

JEDEC STANDARD MS-013

0.51(0.020)

0.33(0.013)

10.65 (0.419)

7.60 (0.2992)

7.40 (0.2914)

10.00 (0.394)

PIN 1 ID

PIN 1

1.27 (0.050) BSC

13.00 (0.5118)

12.60 (0.4961)

2.65 (0.1043)

2.35 (0.0926)

0.30(0.0118)

0.10 (0.0040)

0.32 (0.0125)

0.23 (0.0091)

0º ~ 8º

1.27 (0.050)

0.40 (0.016)

*Controlling dimension: Inches

REV. A 04/11/2001

9

0838HS–AVR–03/02

20Y

20Y, 20-lead Plastic Shrink Small

Outline (SSOP), 5.3mm body Width.

Dimensions in Millimeters and (inches)*

0.38 (0.015)

0.25 (0.010)

5.38 (0.212) 7.90 (0.311)

7.65 (0.301)

5.20 (0.205)

PIN 1 ID

PIN 1

0.65 (0.0256) BSC

7.33 (0.289)

7.07 (0.278)

1.99 (0.078)

1.73 (0.068)

0.21 (0.008)

0.05 (0.002)

0.20 (0.008)

0.09 (0.004)

0º ~ 8º

0.95 (0.037)

0.63 (0.025)

*Controlling dimension: millimeters

REV. A 04/11/2001

10

AT90S1200

0838HS–AVR–03/02

Atmel Headquarters

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Corporate Headquarters

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FAX 1(408) 487-2600

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Printed on recycled paper.

0838HS–AVR–03/02

0M