SST30VR021-500-I-KH--Datasheet/数据表在线中文翻译

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

FEATURES:

1

•

Organized as 256K x8 ROM + 128K x8 SRAM

ROM/RAM combo on a monolithic chip

•

Low Power Dissipation:

– Standby

3.0V Operation: 3 µW (Typical)

– Operating

Equavalent ComboMemory (Flash + SRAM):

SST31LF021E for code development and

pre-production

2

3.0V Operation: 10 mW (Typical)

Fully Static Operation

– No clock or refresh required

Three state Outputs

3

•

Wide Operating Voltage Range: 2.7-3.3V

Chip Access Time

•

– 2.7V Operation: 500 ns (Max.)

Packages Available

4

– 32-Pin TSOP (8mm x 13.4mm)

– 32-Pin TSOP (8mm x 14mm)

5

PRODUCT DESCRIPTION

6

The SST30VR021 is a ROM/RAM combo chip consist-

ing of 2 Mbit Read Only Memory organized as 256

KBytes and a 1 Mbit Static Random Access Memory

organized as 128 KBytes.

TheSST30VR021hasanoutputenableinputforprecise

control of the data outputs. It also has two separate chip

enableinputsforselectionofeitherROMorRAMandfor

minimizing current drain during power-down mode.

7

The device is fabricated using SST’s advanced CMOS

low power processing technology.

The SST30VR021 is particularly well suited for use with

lowvoltagesupplies(2.7-3.3V)suchaspagers,organiz-

ers and other handheld applications.

8

9

F^UNCTIONALBLOCK DIAGRAM OF SST30VR021 ROM/RAM COMBO

10

11

12

13

14

15

16

RAMCS#

ROMCS#

OE#

WE#

RAM

DQ -DQ

7

0

ROMCS#

OE#

A

-A

0

MS

ROM

379 ILL B1.2

Note: A

= Most Significant Address

MS

379-04 2/00

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2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE#

2

A10

A8

3

ROMCS#

DQ7

A13

4

A14

5

DQ6

Standard Pinout

Top View

A17

6

DQ5

RAMCS#

7

DQ4

V

8

DQ3

DD

WE#

A16

A15

A12

A7

9

V

SS

Die Up

10

11

12

13

14

15

16

DQ2

DQ1

DQ0

A0

A6

A1

A5

A2

A4

A3

379 ILL F01.0

F^IGURE1: PIN ASSIGNMENTS

TABLE 1: PIN DESCRIPTION

Symbol

Pin Name

A

_MS-A₀

Address Inputs, A_MS= A₁₇for ROM, A₁₆for RAM

Write Enable Input

Output Enable

WE#

OE#

RAMCS#

ROMCS#

DQ₇-DQ₀

V_DD

RAM Enable Input

ROM Enable Input

Data Inputs/Outputs

Power Supply

Vss

Ground

379 PGM T1.1

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress

Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice

at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.

Exposure to absolute maximum stress rating conditions may affect device reliability.)

Voltage on Any Pin Relative to V_SS............................................................................................................................. -0.5V to V_DD+ 0.5V

Voltage on V_DDSupply Relative to V_SS..................................................................................................................................... -0.5 to 4.0V

Power Dissipation .............................................................................................................................................. 1.0W

Storage Temperature ...................................................................................................................... -65°C to +150°C

Operating Temperature ..................................................................................................................... -40°C to +85°C

Soldering Temperature (10 Seconds Lead Only)............................................................................................. 260°C

AC CONDITIONS OF TEST

OPERATING RANGE

Range

Input Pulse Level ........................0-V_DD

Ambient Temp

0 °C to +70 °C

-20 °C to +70 °C

-40 °C to +85 °C

V_DD

Commercial

Extended

2.7-3.3V

Input & Output Timing

Reference Levels..................V_DD/2

Industrial

Input Rise/Fall Time....................5 ns

Output Load................................C_L= 100 pF

379-04 2/00

2

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

TABLE 2: RECOMMENDED DC OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Units

1

V_DD

V_SS

V_IH

V_IL

Supply Voltage

Ground

2.7

0

3.3

0

V

Input High Voltage

Input Low Voltage

2.4

-0.3

V_DD+0.5

0.3

2

379 PGM T2.0

3

TABLE 3: DC OPERATING CHARACTERISTICS

V_DD= 3.0±0.3V

4

Symbol Parameter

Min

Max

Units Test Conditions

I_LI

Input Leakage Current

Output Leakage Current

-1

1

µA

V_IN=V_SSto V_DD

I_LO

ROMCS# = RAMCS# = V_IHor OE# = V_IHor

WE# = V_IL, V_I/O= V_SSto V_DD

5

I_DD1

I_DD2

I_SB

ROM Operating

Supply Current

4.0+1.1(f) mA

2.5+1(f) mA

ROMCS# = V_IL, RAMCS# = V_IH, V_IN= V_IHor V_IL

I_I/O= Opens

6

RAM Operating

Supply Current

ROMCS# = V_IH, RAMCS# = V_IL, I_I/O= Opens

Standby V_DDCurrent

10

µA

ROMCS# V_DD-0.2V, RAMCS# V_DD-0.2V

V_INV_DD-0.2V or V_IN0.2V

7

V_OL

V_OH

Output Low Voltage

Output High Voltage

0.4

V

I_OL= 1.0 mA

2.2

I_OH= -0.5 mA

8

379 PGM T3.1

Note: f = frequency of operation (MHz) = 1/cycle time

9

TABLE 4: CAPACITANCE (Ta = 25 °C, f=1 Mhz)

Parameter

Description

Test Condition

Maximum

10

11

12

13

14

15

16

C_I/O

C_IN

I/O Capacitance

V_I/O= 0V

V_IN= 0V

8 pF

6 pF

Input Capacitance

379 PGM T4.0

V

IHT

V

INPUT

REFERENCE POINTS

OUTPUT

OT

IT

V

ILT

379 ILL F08.0

AC test inputs are driven at V_IHT(0.9 V_DD) for a logic “1” and V_ILT(0.1 V_DD) for a logic “0”. Measurement reference points

for inputs and outputs are V_IT(0.5 V_DD) and V_OT(0.5 V_DD). Inputs rise and fall times (10%

90%) are <5 ns.

FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS

379-04 2/00

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2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

TO TESTER

TO DUT

C

L

379 ILL F09.0

FIGURE 3: A TEST LOAD EXAMPLE

AC CHARACTERISTICS

I. ROM Operation

T^ABLE5: READ CYCLE TIMING PARAMETERS V_DD= 3.0 V ± 0.3

Symbol

T_RC

T_AA

T_CO

T_OE

T_LZ

T_OLZ

T_HZ

T_OHZ

T_OH

Parameter

Read Cycle Time

Address Access Time

Chip Select to Output

Output Enable to Valid Output

Chip Select to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Min

500

Max

Unit

ns

500

250

25

30

15

379 PGM T5.0

T

RC

Address

T

AA

T

OH

Data Out

Previous Data Valid

Data Valid

379 ILL F02.0

FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = V_IL)

379-04 2/00

4

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

T

RC

Address

1

T

HZ(1,2)

AA

2

T

CO

ROMCS#

OE#

T

OHZ(1)

LZ(2)

3

T

OE

4

T

OLZ

OH

High-Z

Data Valid

Data Out

5

379 ILL F03.0

Notes: 1. T

HZ

and T

are defined as the time at which the outputs achieve the open circuit condition

OHZ

and are referenced to the V

or V

.

OH

OL

6

2. At any given temperature and voltage condition T (max) is less than T (min) both for a given

HZ LZ

device and from device to device.

FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# OR OE# CONTROLLED)

7

II. SRAM Operation (ROMCS# = VIH)

8

TABLE 6: READ CYCLE TIMING PARAMETERS V_DD=3.0 V ± 0.3

Symbol

T_RC

Parameter

Read Cycle Time

Min

500

Max

Unit

ns

9

T_AA

T_CO

T_OE

T_LZ

Address Access Time

500

ns

Chip Select to Output

10

11

12

13

14

15

16

Output Enable to Valid Output

Chip Select to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

25

T_HZ

T_OHZ

T_OH

30

15

ns

379 PGM T6.0

TABLE 7: WRITE CYCLE TIMING PARAMETERS V_DD=3.0 V ± 0.3

Symbol

T_WC

Parameter

Write Cycle Time

Min

500

Max

Unit

ns

T_CW

T_AW

T_AS

Chip Select to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

365

375

0

ns

T_WP

T_WR

T_WHZ

T_DW

T_DH

Write Pulse Width

375

0

Write Recovery Time

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

80

200

0

T_OW

15

ns

379 PGM T7.0

379-04 2/00

5

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

T

RC

Address

Data Out

T

AA

T

OH

Previous Data Valid

Data Valid

379 ILL F04.0

FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE# OR RAMCS# = V_IL, WE# = V_IH)

T

RC

Address

T

AA

T

OHZ(1)

T

OE

OE#

(1,2)

T

HZ

T

CO

RAMCS#

T

LZ(2)

T

OH

High-Z

Data Valid

Data Out

379 ILL F05.1

Notes: 1. T

and T

are defined as the time at which the outputs achieve the open circuit condition

OHZ

HZ

and are referenced to the V

or V

.

OH

OL

2. At any given temperature and voltage condition T (max) is less than T (min) both for a given

HZ LZ

device and from device to device.

3. WE# is high for Read cycle.

4. Address valid prior to coincidence with RAMCS# transition low.

FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE# OR RAMCS# CONTROLLED)

379-04 2/00

6

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

T

WC

1

Address

T

WR(4)

AW

2

T

CW(2)

OE#

3

RAMCS#

4

T

AS(3)

WP(1)

OH

5

WE#

T

DH

DW

6

High-Z

Data Valid

Data In

T

OW

WHZ(5)

7

(7)

(8)

High-Z (6)

Data Out

379 ILL F06.0

8

Notes: 1. A write occurs during the overlap (T

) of a low RAMCS# and low WE#. A write begins at the latest transition among

WP

RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,

T

2. T

3. T

4. T

is measured from the beginning of write to the end of write.

is measured from the later of RAMCS# going low to the end of write.

is measured from the address valid to the beginning of write.

is measured from the end of write to the address change.

WP

CW

AS

9

WR

5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.

10

11

12

13

14

15

16

Inputs of opposite phase of the output must not be applied because bus contention can occur.

6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.

7. D

8. D

is the same phase of the latest written data in this write cycle.

is the read data of new address

OUT

9. ROMCS# = V

IH

FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM (OE# CLOCK)

379-04 2/00

7

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

T

WC

Address

T

AW

T

WR(4)

T

CW(2)

RAMCS#

T

AS(3)

WP(1)

OH

WE#

Data In

T

DH

DW

High-Z

Data Valid

T

OW

WHZ(5)

(7)

(8)

High-Z (6)

Data Out

379 ILL F07.1

Notes: 1. A write occurs during the overlap (T

) of a low RAMCS# and low WE#. A write begins at the latest transition among

WP

RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,

T

2. T

3. T

4. T

is measured from the beginning of write to the end of write.

is measured from the later of RAMCS# going low to the end of write.

is measured from the address valid to the beginning of write.

is measured from the end of write to the address change.

WP

CW

AS

WR

5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.

Inputs of opposite phase of the output must not be applied because bus contention can occur.

6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.

7. D

8. D

is the same phase of the latest written data in this write cycle.

is the read data of new address

OUT

9. ROMCS# = V

IH

FIGURE 9: SRAM WRITE CYCLE TIMING DIAGRAM (OE# FIXED)

379-04 2/00

8

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE

Address Inputs

X

ROMCS#

RAMCS#

WE#

X

OE#

X

DQ -DQ

7

0

1

H

L

H

L

Z

Standby

Output Floating

ROM Read

A17-A0

X

H

A17-A0

L

X

L

Dout

Z

2

Only A16-A0 are valid *

H

Output Floating

RAM Read

L

H

L

Dout

Din

3

Only A16-A0 are valid *

L

H

RAM Write

379 PGM T9.2

* A17 must be fixed to “L” or “H”

4

Note: (1) It is forbidden that ROMCS# pin and RAMCS# pin will be “0” at the same time.

(2) X means Don’t Care.

5

6

7

8

9

10

11

12

13

14

15

16

379-04 2/00

9

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

Device

Speed Suffix1

- XXX

Suffix2

SST30VR021

-

X

-

XX - RXXXX

C-Spec Number

Package Modifier

H = 32 pins

Numeric = Die modifier

Package Type

W = TSOP (die up) 8mm x 14mm

K = TSOP (die up) 8mm x 13.4mm

U = Die only

Temperature Range

C = Commercial = 0° to 70°C

E = Extended = -20° to 70°C

I = Industrial = -40° to 85°C

Read Access Speed

500 = 500 ns

Density

021 = 2 Mbit ROM + 1 Mbit SRAM

Voltage Range

V = 2.7-3.3V

Device Family

30 = ROM/RAM Combo

SST30VR021 Valid combinations

SST30VR021-500-C-WH

SST30VR021-500-C-KH

SST30VR021-500-E-KH

SST30VR021-500-I-KH

SST30VR021-500-C-U1

SST30VR021-500-E-WH

SST30VR021-500-I-WH

Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

379-04 2/00

10

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

PACKAGING DIAGRAMS

.91

1.05

1

ALTERNATE

INDICATOR

PIN # 1

.50

BSC

2

3

.16

.27

7.90

8.30 †

4

5

0.05

0.20

11.70

11.90

6

7

0.70

0.30

13.20

13.60

32.TSOP-KH-ILL.4

8

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions (except as noted), although some dimensions may be more stringent.

† = JEDEC max is 8.1; SST max is less stringent

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

9

32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 13.4MM

SST PACKAGE CODE: KH

10

11

12

13

14

15

16

379-04 2/00

11

2 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo

SST30VR021

Data Sheet

1.05

0.95

PIN # 1 IDENTIFIER

.50

BSC

.270

.170

8.10

7.90

0.15

0.05

12.50

12.30

0.70

0.50

14.20

13.80

Note:

1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

32.TSOP-WH-ILL.3

3. Coplanarity: 0.1 (±.05) mm.

32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873

379-04 2/00

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