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PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS854S013I is a low skew, high • Two differential LVDS output banks  
ICS  
perfor- mance Dual 1-to-3 Differential-to-  
LVDS Fanout Buffer and a member of the  
HiPerClock S ™family of High Perfor-  
mance Clock Solutions from ICS. The  
• Two differential clock input pairs  
HiPerClockS™  
• PCLKx, nPCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, CML, SSTL  
PCLKx, nPCLKx pairs can accept most standard differ-  
ential input levels. The ICS854S013I is characterized  
to operate from a 3.3V power supply. Guaranteed  
output and bank skew characteristics make the  
ICS854S013I ideal for those clock distribution ap-  
plications demanding well defined performance  
and repeatability.  
• Maximum output frequency: >3GHz  
• Translates any single ended input signal to LVDS levels  
with resistor bias on nCLKx input  
• Output skew: <25ps (typical) design target  
• Bank skew: <50ps (typical) design target  
• Propagation delay: TBD  
• Additive phase jitter, RMS: 0.15ps (typical)  
• Full 3.3V power supply  
• -40°C to 85°C ambient operating temperature  
• Available in both standard and lead-free RoHS complaint  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
QA0  
QA1  
nQA1  
QA2  
nQA2  
VDD  
QB2  
nQB2  
QB1  
nQB1  
GND  
nQA0  
QA0  
VDD  
PCLKA  
nPCLKA  
PCLKB  
nPCLKB  
VDD  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
nQA0  
Pulldown  
PCLKA  
QA1  
nQA1  
Pullup  
nPCLKA  
QA2  
nQA2  
QB0  
nQB0  
nQB0  
QB0  
Pulldown  
Pullup  
PCLKB  
QB1  
nPCLKB  
nQB1  
ICS854S013I  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.92mm body package  
G Package  
QB2  
nQB2  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on  
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications  
without notice.  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
1
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
TABLE 1. PIN DESCRIPTIONS  
Number  
1, 2  
Name  
nQA0, QA0  
VDD  
Type  
Description  
Output  
Power  
Input  
Differential output pair. LVPECL interface levels.  
Power supply pins.  
3, 8, 16  
4
PCLKA  
Pulldown Non-inverting differential clock input.  
Pullup Inverting differential clock input. VDD/2 default when left floating.  
Pulldown Non-inverting differential clock input.  
5
nPCLKA  
PCLKB  
Input  
6
Input  
7
nPCLKB  
nQB0, QB0  
GND  
Input  
Pullup  
Inverting differential clock input. VDD/2 default when left floating.  
Differential output pair. LVPECL interface levels.  
Power supply ground  
9, 10  
11  
Output  
Power  
Output  
Output  
Output  
Output  
12, 13  
14, 15  
17, 18  
19, 20  
nQB1, QB1  
nQB2, QB2  
nQA2, QA2  
nQA1, QA1  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
4
RPULLUP  
51  
51  
kΩ  
RPULLDOWN Input Pulldown Resistor  
kΩ  
TABLE 3. CLOCK INPUT FUNCTION TABLE  
Inputs  
Outputs  
Input to Output Mode  
Polarity  
QA0:QA2,  
QB0:QB2  
nQA0:nQA2,  
nQB0:nQB2  
PCLKA, PCLKB nPCLKA, nPCLKB  
0
1
LOW  
HIGH  
LOW  
HIGH  
LOW  
LOW  
HIGH  
Differential to Differential  
Differential to Differential  
Single Ended to Differential  
Single Ended to Differential  
Single Ended to Differential  
Single Ended to Differential  
Non Inverting  
Non Inverting  
Non Inverting  
Non Inverting  
Inverting  
1
0
HIGH  
LOW  
HIGH  
HIGH  
LOW  
0
Biased; NOTE 1  
1
Biased; NOTE 1  
Biased; NOTE 1  
Biased; NOTE 1  
0
1
Inverting  
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
2
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
device. These ratings are stress specifications only. Functional  
operation of product at these conditions or any conditions be-  
yond those listed in the DC Characteristics or AC Characteris-  
tics is not implied. Exposure to absolute maximum rating con-  
ditions for extended periods may affect product reliability.  
DD  
Inputs, V  
-0.5V to VDD + 0.5 V  
I
Outputs, IO (LVDS)  
Continuous Current  
Surge Current  
10mA  
15mA  
Package Thermal Impedance, θJA  
73.2°C/W (0 lfpm)  
-65°C to 150°C  
Storage Temperature, T  
STG  
(Junction-to-Ambient)  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum Units  
VDD  
IDD  
Power Supply Voltage  
Power Supply Current  
3.135  
3.465  
V
135  
mA  
TABLE 4B. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
DD = VIN = 3.465  
Minimum Typical Maximum Units  
PCLKA, PCLKB  
nPCLKA, nPCLKB  
PCLKA, PCLKB  
nPCLKA, nPCLKB  
V
150  
5
µA  
µA  
µA  
µA  
V
Input  
IIH  
High Current  
VDD = VIN = 3.465  
V
DD = 3.465V, VIN = 0V  
-5  
Input  
IIL  
Low Current  
VDD = 3.465V, VIN = 0V  
-150  
0.15  
VPP  
Peak-to-Peak Input Voltage  
1.3  
Common Mode Input Voltage;  
NOTE 1, 2  
VCMR  
GND + 0.5  
VDD - 0.85  
V
NOTE 1: Common mode voltage is defined as VIH.  
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VDD + 0.3V.  
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
360  
Maximum Units  
VOD  
Differential Output Voltage  
mV  
mV  
V
∆ VOD  
VOS  
VOD Magnitude Change  
Offset Voltage  
50  
1.35  
50  
∆ VOS  
VOS Magnitude Change  
mV  
NOTE: Please refer to Parameter Measurement Information for output information.  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
3
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C  
Symbol Parameter  
fMAX Output Frequency  
tPD  
Test Conditions  
Minimum Typical Maximum Units  
>3  
GHz  
ns  
Propagation Delay; NOTE 1  
Output Skew; NOTE 2, 4  
TBD  
<25  
target  
<50  
tsk(o)  
tsk(b)  
tjit  
ps  
ps  
ps  
Bank Skew; NOTE 3, 4  
target  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter Section  
100MHz, Integration Range:  
12kHz - 20MHz  
0.15  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
200  
50  
ps  
%
All parameters measured at 500MHz unless noted otherwise.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured from at the output differential cross points.  
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
4
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
ADDITIVE PHASE JITTER  
ratio of the power in the 1Hz band to the power in the funda-  
mental. When the required offset is specified, the phase noise  
is called a dBc value, which simply means dBm at a specified  
offset from the fundamental. By investigating jitter in the fre-  
quency domain, we get a better understanding of its effects  
on the desired application over the entire time record of the  
signal. It is mathematically possible to calculate an expected  
bit error rate given a phase noise plot.  
The spectral purity in a band at a specific offset from the  
fundamental compared to the power of the fundamental is  
called the dBc Phase Noise. This value is normally expressed  
using a Phase noise plot and is most often the specified plot  
in many applications. Phase noise is defined as the ratio of  
the noise power present in a 1Hz band at a specified offset  
from the fundamental frequency to the power value of the  
fundamental. This ratio is expressed in decibels (dBm) or a  
0
-10  
-20  
-30  
Additive Phase Jitter, RMS  
@ 100MHz = 0.15ps typical  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
-150  
-160  
-170  
-180  
-190  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FROM CARRIER FREQUENCY (HZ)  
As with most timing specifications, phase noise measure- above. The device meets the noise floor of what is shown, but  
ments have issues. The primary issue relates to the limita- can actually be lower. The phase noise is dependant on the  
tions of the equipment. Often the noise floor of the equipment input source and measurement equipment.  
is higher than the noise floor of the device. This is illustrated  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
5
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PARAMETER MEASUREMENT INFORMATION  
VDD  
SCOPE  
Qx  
3.3V±5%  
nPCLKA, nPCLKB  
PCLKA, PCLKB  
POWER SUPPLY  
+
LVDS  
Float GND  
-
VPP  
VCMR  
Cross Points  
nQx  
GND  
3.3V CORE/3.3V OUTPUT LOAD ACTEST CIRCUIT  
DIFFERENTIAL INPUT LEVEL  
nQx  
Qx  
nQAx  
QAx  
nQy  
nQBy  
QBy  
Qy  
tsk(o)  
tsk(b)  
BANK SKEW  
OUTPUT SKEW  
nPCLKA,  
nPCLKB  
nQAx,  
nQBx  
PCLKA,  
PCLKB  
QAx,  
QBx  
tPW  
nQAx,  
nQBx  
tPERIOD  
tPW  
tPERIOD  
QAx,  
QBx  
odc =  
x 100%  
tPD  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
PROPAGATION DELAY  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
6
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
VDD  
out  
80%  
80%  
tR  
➤
DC Input  
LVDS  
VSWING  
20%  
Clock  
Outputs  
20%  
out  
VOS/∆ VOS  
tF  
➤
OUTPUT RISE/FALLT IME  
OFFSETVOLTAGE SETUP  
VDD  
➤
out  
out  
LVDS  
DC Input  
100  
V
OD/∆ VOD  
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
7
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
APPLICATION INFORMATION  
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS  
Figure 1 shows how the differential input can be wired to accept ratio of R1 and R2 might need to be adjusted to position the  
single ended levels. The reference voltage V_REF = VCC/2 is V_REF in the center of the input voltage swing. For example, if  
generated by the bias resistors R1, R2 and C1.This bias circuit the input clock swing is only 2.5V andVCC= 3.3V, V_REF should  
should be located as close as possible to the input pin. The be 1.25V and R2/R1 = 0.609.  
VCC  
R1  
1K  
Single Ended Clock Input  
PCLK  
V_REF  
nPCLK  
C1  
0.1u  
R2  
1K  
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT  
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS  
INPUTS:  
OUTPUTS:  
PCLK/nPCLK INPUT:  
LVDS OUTPUT  
For applications not requiring the use of a differential input, All unused LVDS output pairs can be either left floating or  
both the PCLK and nPCLK pins can be left floating. Though terminated with 100Ω across. If they are left floating, there  
not required, but for additional protection, a 1kΩ resistor can should be no trace attached.  
be tied from PCLK to ground.  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
8
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
LVPECL CLOCK INPUT INTERFACE  
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other faces suggested here are examples only. If the driver is  
differential signals. Both VSWING and VOH must meet the VPP from another vendor, use their termination recommenda-  
and VCMR input requirements. Figures 2A to 2E show inter- tion. Please consult with the vendor of the driver compo-  
face examples for the HiPerClockS PCLKx/nPCLKx input nent to confirm the driver termination requirements.  
driven by the most common driver types. The input inter-  
2.5V  
3.3V  
3.3V  
3.3V  
2.5V  
3.3V  
R3  
120  
R4  
120  
R1  
50  
R2  
50  
SSTL  
Zo = 60 Ohm  
Zo = 60 Ohm  
CML  
Zo = 50 Ohm  
Zo = 50 Ohm  
PCLK  
PCLK  
nPCLK  
HiPerClockS  
nPCLK  
PCLK/nPCLK  
HiPerClockS  
PCLK/nPCLK  
R1  
120  
R2  
120  
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A CML DRIVER  
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY AN SSTL DRIVER  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
R3  
125  
R4  
125  
3.3V  
Zo = 50 Ohm  
R3  
1K  
R4  
1K  
Zo = 50 Ohm  
Zo = 50 Ohm  
C1  
C2  
LVDS  
PCLK  
PCLK  
R5  
100  
nPCLK  
nPCLK  
Zo = 50 Ohm  
HiPerClockS  
PCLK/nPCLK  
HiPerClockS  
Input  
LVPECL  
R1  
1K  
R2  
1K  
R1  
84  
R2  
84  
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A 3.3V LVPECL DRIVER  
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A 3.3V LVDS DRIVER  
3.3V  
3.3V  
3.3V  
R3  
84  
R4  
84  
C1  
C2  
3.3V LVPECL  
Zo = 50 Ohm  
Zo = 50 Ohm  
PCLK  
nPCLK  
HiPerClockS  
PCLK/nPCLK  
R5  
100 - 200  
R6  
100 - 200  
R1  
125  
R2  
125  
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A 3.3V LVPECL DRIVER WITH AC COUPLE  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
9
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
3.3V LVDS DRIVER TERMINATION  
A general LVDS interface is shown in Figure 3. In a 100Ω receiver input. For a multiple LVDS outputs buffer, if only par-  
differential transmission line environment, LVDS drivers re- tial outputs are used, it is recommended to terminate the un-  
quire a matched load termination of 100Ω across near the used outputs.  
3.3V  
3.3V  
LVDS  
+
R1  
100  
-
100 Ohm Differential Transmission Line  
FIGURE 3. TYPICAL LVDS DRIVERT ERMINATION  
854S013AGI  
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REV.A JUNE 16, 2006  
10  
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
POWER CONSIDERATIONS  
This section provides information on power dissipation and junction temperature for the ICS854S013I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the ICS854S013I is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
·
Power_MAX = VDD_MAX * IDD_MAX = 3.465V * 135mA = 467.77mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of  
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming  
a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.468W * 66.6°C/W = 116.2°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air  
flow, and the type of board (single layer or multi-layer).  
TABLE 6. THERMAL RESISTANCE θJA FOR 20 LEADTSSOP, FORCED CONVECTION  
θJA by Velocity (Linear Feet per Minute)  
0
200  
500  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
114.5°C/W  
98.0°C/W  
88.0°C/W  
73.2°C/W  
66.6°C/W  
63.5°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.  
854S013AGI  
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REV.A JUNE 16, 2006  
11  
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
RELIABILITY INFORMATION  
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 20 LEAD TSSOP  
θJA by Velocity (Linear Feet per Minute)  
0
200  
500  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
114.5°C/W  
98.0°C/W  
88.0°C/W  
73.2°C/W  
66.6°C/W  
63.5°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.  
TRANSISTOR COUNT  
The transistor count for ICS854S013I is: 363  
854S013AGI  
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REV.A JUNE 16, 2006  
12  
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PACKAGE OUTLINE - G SUFFIX FOR 20 LEADTSSOP  
TABLE 8. PACKAGE DIMENSIONS  
Millimeters  
SYMBOL  
Minimum  
Maximum  
N
A
20  
--  
1.20  
0.15  
1.05  
0.30  
0.20  
6.60  
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
6.40  
c
D
E
6.40 BASIC  
0.65 BASIC  
E1  
e
4.30  
4.50  
L
0.45  
0°  
0.75  
8°  
α
aaa  
--  
0.10  
Reference Document: JEDEC Publication 95, MS-153  
854S013AGI  
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REV.A JUNE 16, 2006  
13  
PRELIMINARY  
ICS854S013I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, DUAL, 1-TO-3  
DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
TABLE 9.ORDERING INFORMATION  
Part/Order Number  
Marking  
Package  
Shipping Packaging Temperature  
ICS854S013I  
ICS854S013IT  
ICS854S013ILF  
ICS854S013ILFT  
ICS854S013AI  
ICS854S013AI  
ICS54S013AIL  
ICS54S013AIL  
20 lead TSSOP  
tube  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
20 lead TSSOP  
2500 tape & reel  
tube  
20 lead "Lead-Free" TSSOP  
20 lead "Lead-Free" TSSOP  
2500 tape & reel  
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use  
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use  
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product  
for use in life support devices or critical medical instruments.  
854S013AGI  
www.icst.com/products/hiperclocks.html  
REV.A JUNE 16, 2006  
14