ATTINY2313A-SUR--Datasheet/数据表在线中文翻译

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

• Data and Non-volatile Program and Data Memories

– 2/4K Bytes of In-System Self Programmable Flash

• Endurance 10,000 Write/Erase Cycles

– 128/256 Bytes In-System Programmable EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 128/256 Bytes Internal SRAM

8-bit

Microcontroller

with 2/4K Bytes

In-System

Programmable

Flash

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes

– Four PWM Channels

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– USI – Universal Serial Interface

– Full Duplex USART

ATtiny2313A

ATtiny4313

• Special Microcontroller Features

– debugWIRE On-chip Debugging

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low-power Idle, Power-down, and Standby Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

Summary

• I/O and Packages

– 18 Programmable I/O Lines

– 20-pin PDIP, 20-pin SOIC, 20-pad MLF/VQFN

• Operating Voltage

– 1.8 – 5.5V

• Speed Grades

– 0 – 4 MHz @ 1.8 – 5.5V

– 0 – 10 MHz @ 2.7 – 5.5V

– 0 – 20 MHz @ 4.5 – 5.5V

• Industrial Temperature Range: -40°C to +85°C

• Low Power Consumption

– Active Mode

• 190 µA at 1.8V and 1MHz

– Idle Mode

• 24 µA at 1.8V and 1MHz

– Power-down Mode

• 0.1 µA at 1.8V and +25°C

Rev. 8246BS–AVR–09/11

1. Pin Configurations

Figure 1-1. Pinout ATtiny2313A/4313

PDIP/SOIC

VCC

(PCINT10/RESET/dW) PA2

(PCINT11/RXD) PD0

1

2

3

4

5

6

7

8

9

10

20

19

18

PB7 (USCK/SCL/SCK/PCINT7)

PB6 (MISO/DO/PCINT6)

(PCINT12/TXD) PD1

17 PB5 (MOSI/DI/SDA/PCINT5)

(PCINT9/XTAL2) PA1

(PCINT8/CLKI/XTAL1) PA0

(PCINT13/CKOUT/XCK/INT0) PD2

(PCINT14/INT1) PD3

(PCINT15/T0) PD4

16

15

14

13

12

11

PB4 (OC1B/PCINT4)

PB3 (OC1A/PCINT3)

PB2 (OC0A/PCINT2)

PB1 (AIN1/PCINT1)

PB0 (AIN0/PCINT0)

PD6 (ICPI/PCINT17)

(PCINT16/OC0B/T1) PD5

GND

MLF/VQFN

(PCINT12/TXD) PD1

(PCINT9/XTAL2) PA1

1

2

3

4

5

15

14

13

12

11

PB5 (MOSI/DI/SDA/PCINT5)

PB4 (OC1B/PCINT4)

PB3 (OC1A/PCINT3)

PB2 (OC0A/PCINT2)

PB1 (AIN1/PCINT1)

(PCINT8/CLKI/XTAL1) PA0

(PCINT13/CKOUT/XCK/INT0) PD2

(PCINT14/INT1) PD3

NOTE: Bottom pad should be soldered to ground.

2

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

1.1.3

GND

Ground.

Port A (PA2..PA0)

Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability, except PA2 which has the RESET capability. To use pin PA2 as I/O pin, instead of

RESET pin, program (“0”) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low

will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATtiny2313A/4313 as listed on

page 61.

1.1.4

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny2313A/4313 as listed on

page 62.

1.1.5

Port D (PD6..PD0)

Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATtiny2313A/4313 as listed on

page 66.

1.1.6

1.1.7

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running and provided that the reset pin has not been disabled. The

minimum pulse length is given in Table 22-3 on page 201. Shorter pulses are not guaranteed to

generate a reset. The Reset Input is an alternate function for PA2 and dW.

The reset pin can also be used as a (weak) I/O pin.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1

is an alternate function for PA0.

3

8246BS–AVR–09/11

1.1.8

XTAL2

Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.

4

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

2. Overview

The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

XTAL1

XTAL2

PA0 - PA2

PORTA DRIVERS

DATA DIR.

REG. PORTA

DATA REGISTER

PORTA

INTERNAL

CALIBRATED

OSCILLATOR

VCC

GND

8-BIT DATA BUS

INTERNAL

OSCILLATOR

STACK

POINTER

TIMING AND

CONTROL

PROGRAM

COUNTER

WATCHDOG

TIMER

RESET

MCU CONTROL

REGISTER

PROGRAM

FLASH

SRAM

ON-CHIP

DEBUGGER

MCU STATUS

REGISTER

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTER

TIMER/

COUNTERS

INSTRUCTION

DECODER

INTERRUPT

UNIT

EEPROM

USI

CONTROL

LINES

ALU

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

USART

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD6

5

8246BS–AVR–09/11

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATtiny2313A/4313 provides the following features: 2/4K bytes of In-System Programmable

Flash, 128/256 bytes EEPROM, 128/256 bytes SRAM, 18 general purpose I/O lines, 32 general

purpose working registers, a single-wire Interface for On-chip Debugging, two flexible

Timer/Counters with compare modes, internal and external interrupts, a serial programmable

USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog

Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode

stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue func-

tioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling

all other chip functions until the next interrupt or hardware reset. In Standby mode, the crys-

tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast

start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit

RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel

ATtiny2313A/4313 is a powerful microcontroller that provides a highly flexible and cost effective

solution to many embedded control applications.

The ATtiny2313A/4313 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu-

lators, and Evaluation kits.

2.2

Comparison Between ATtiny2313A and ATtiny4313

The ATtiny2313A and ATtiny4313 differ only in memory sizes. Table 2-1 summarizes the differ-

ent memory sizes for the two devices.

Table 2-1.

Device

Memory Size Summary

Flash

EEPROM

128 Bytes

256 Bytes

RAM

ATtiny2313A

ATtiny4313

2K Bytes

128 Bytes

256 Bytes

4K Bytes

6

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

3. About

3.1

Resources

A comprehensive set of drivers, application notes, data sheets and descriptions on development

tools are available for download at http://www.atmel.com/avr.

3.2

Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically, this

means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all

AVR devices include an extended I/O map.

3.3

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

7

8246BS–AVR–09/11

4. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (ox42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

SREG

Reserved

SPL

I

–

T

–

H

–

S

–

V

–

N

–

Z

–

C

–

9

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

12

85

OCR0B

GIMSK

GIFR

Timer/Counter0 – Compare Register B

INT1

INTF1

TOIE1

TOV1

–

INT0

INTF0

OCIE1A

OCF1A

–

PCIE0

PCIF0

PCIE2

PCIF2

–

PCIE1

PCIF1

ICIE1

ICF1

–

50

–

51

TIMSK

OCIE1B

OCF1B

RSIG

OCIE0B

OCF0B

PGWRT

TOIE0

TOV0

PGERS

OCIE0A

OCF0A

SPMEN

86, 115

175

85

TIFR

–

SPMCSR

OCR0A

MCUCR

MCUSR

TCCR0B

TCNT0

OSCCAL

TCCR0A

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

Reserved

CLKPR

ICR1H

CTPB

RFLB

Timer/Counter0 – Compare Register A

PUD

–

SM1

–

SE

–

SM0

ISC11

WDRF

ISC10

BORF

CS02

ISC01

EXTRF

CS01

ISC00

PORF

CS00

36, 50, 68

44

–

FOC0A

FOC0B

–

WGM02

84

Timer/Counter0 (8-bit)

85

–

CAL6

COM0A0

COM1A0

ICES1

CAL5

COM0B1

COM1B1

–

CAL4

CAL3

CAL2

–

CAL1

WGM01

WGM11

CS11

CAL0

WGM00

WGM10

CS10

31

COM0A1

COM1A1

ICNC1

COM0B0

COM1B0

WGM13

–

81

–

110

112

114

WGM12

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Compare Register A High Byte

Timer/Counter1 – Compare Register A Low Byte

Timer/Counter1 – Compare Register B High Byte

Timer/Counter1 – Compare Register B Low Byte

–

CLKPCE

CLKPS3

CLKPS2

CLKPS1

CLKPS0

31

114

118

113

44

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

ICR1L

GTCCR

TCCR1C

WDTCSR

PCMSK0

Reserved

EEAR

–

FOC1A

WDIF

PCINT7

–

PSR10

–

FOC1B

WDIE

PCINT6

–

WDP3

PCINT5

–

WDCE

PCINT4

–

WDE

PCINT3

–

WDP2

PCINT2

–

WDP1

PCINT1

–

WDP0

PCINT0

–

53

–

EEPROM Address Register

EEPROM Data Register

23

EEDR

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

PORTA2

DDA2

EEPE

PORTA1

DDA1

EERE

PORTA0

DDA0

23

PORTA

DDRA

–

68

PINA

–

PINA2

PINA1

PINA0

69

PORTB

DDRB

PORTB7

DDB7

PINB7

PORTB6

DDB6

PINB6

PORTB5

DDB5

PINB5

PORTB4

DDB4

PINB4

PORTB3

DDB3

PINB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

69

PINB

PINB2

PINB1

PINB0

69

GPIOR2

GPIOR1

GPIOR0

PORTD

DDRD

General Purpose I/O Register 2

General Purpose I/O Register 1

General Purpose I/O Register 0

24

–

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

69

PIND

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

69

USIDR

USISR

USI Data Register

165

164

162

136

137

138

140

167

37

USISIF

USISIE

USIOIF

USIOIE

USIPF

USIDC

USICNT3

USICS1

USICNT2

USICS0

USICNT1

USICLK

USICNT0

USITC

USICR

UDR

USIWM1

USIWM0

UART Data Register (8-bit)

UCSRA

UCSRB

UBRRL

ACSR

RXC

TXC

UDRE

UDRIE

FE

DOR

UPE

U2X

MPCM

TXB8

RXCIE

TXCIE

RXEN

TXEN

UCSZ2

RXB8

UBRRH[7:0]

ACD

ACBG

ACO

ACI

ACIE

–

ACIC

–

ACIS1

BODS

ACIS0

BODSE

BODCR

PRR

–

PRTIM1

PCINT14

–

PRTIM0

PCINT13

PCINT10

UCSZ1

PRUSI

PRUSART

PCINT11

PCINT8

UCPOL

36

PCMSK2

PCMSK1

UCSRC

UBRRH

DIDR

–

PCINT17

PCINT16

PCINT15

PCINT12

PCINT9

UCSZ0

52

–

52

UMSEL1

UMSEL0

UPM1

UPM0

USBS

139

140

168

166

UBRRH[11:8]

AIN1D

–

AIN0D

USI Buffer Register

USIBR

8

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

9

8246BS–AVR–09/11

5. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

LSL

LSR

ROL

I/O(P,b) ← 0

None

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Logical Shift Right

Rotate Left Through Carry

10

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ROR

Rd

Rotate Right Through Carry

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

1

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd

s

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

11

8246BS–AVR–09/11

6. Ordering Information

6.1

ATtiny2313A

Speed (MHz) ⁽¹⁾

Supply Voltage (V)

Temperature Range

Package ⁽²⁾

Ordering Code ⁽³⁾

ATtiny2313A-PU

ATtiny2313A-SU

ATtiny2313A-SUR

ATtiny2313A-MU

ATtiny2313A-MUR

ATtiny2313A-MMH

ATtiny2313A-MMHR

20P3

20S

20M1

Industrial

20

1.8 – 5.5

(-40°C to +85°C) ⁽⁴⁾

20M2 ⁽⁵⁾⁽⁶⁾

Notes: 1. For speed vs. supply voltage, see section 22.3 “Speed” on page 199.

2. All packages are Pb-free, halide-free and fully green, and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. Code indicators:

– H: NiPdAu lead finish

– U or N: matte tin

– R: tape & reel

4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.

5. NiPdAu finish

6. Topside markings :

– 1st Line: T2313

– 2nd Line: Axx

– 3rd Line: xxx

Package Type

20P3

20S

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead / Micro Lead Frame Package (MLF)

20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)

20M1

20M2

12

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

6.2

ATtiny4313

Speed (MHz) ⁽¹⁾

Supply Voltage (V)

Temperature Range

Package ⁽²⁾

Ordering Code ⁽³⁾

ATtiny4313-PU

20P3

ATtiny4313-SU

20S

20M1

ATtiny4313-SUR

ATtiny4313-MU

ATtiny4313-MUR

ATtiny4313-MMH

ATtiny4313-MMHR

Industrial

20

1.8 – 5.5

(-40°C to +85°C) ⁽⁴⁾

20M2 ⁽⁵⁾⁽⁶⁾

Notes: 1. For speed vs. supply voltage, see section 22.3 “Speed” on page 199.

2. All packages are Pb-free, halide-free and fully green, and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. Code indicators:

– H: NiPdAu lead finish

– U or N: matte tin

– R: tape & reel

4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.

5. NiPdAu finish

6. Topside markings:

– 1st Line: T4313

– 2nd Line: Axx

– 3rd Line: xxx

Package Type

20P3

20S

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)

20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)

20M1

20M2

13

8246BS–AVR–09/11

7. Packaging Information

7.1

20P3

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

C

MIN

–

MAX

5.334

–

NOM

NOTE

SYMBOL

eC

A

–

eB

A1

D

0.381

25.493

7.620

6.096

0.356

1.270

2.921

0.203

–

25.984 Note 2

8.255

E

E1

B

7.112 Note 2

0.559

B1

L

1.551

3.810

C

0.356

Notes:

eB

eC

e

10.922

1. This package conforms to JEDEC reference MS-001, Variation AD.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

0.000

1.524

2.540 TYP

2010-10-19

DRAWING NO. REV.

20P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

D

R

14

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

7.2

20S

15

8246BS–AVR–09/11

7.3

20M1

D

1

2

Pin 1 ID

SIDE VIEW

E

3

TOP VIEW

A2

A1

D2

A

0.08

C

1

2

3

Pin #1

Notch

(0.20 R)

COMMON DIMENSIONS

(Unit of Measure = mm)

E2

MIN

0.70

–

MAX

0.80

0.05

b

NOM

0.75

NOTE

SYMBOL

A

A1

A2

b

0.01

L

0.20 REF

0.23

0.18

2.45

0.35

0.30

2.75

0.55

e

D

4.00 BSC

2.60

D2

E

BOTTOM VIEW

4.00 BSC

2.60

E2

e

0.50 BSC

0.40

Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.

Note:

L

10/27/04

DRAWING NO. REV.

20M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,

2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)

A

R

16

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

7.4

20M2

D

C

y

Pin 1 ID

E

SIDE VIEW

TOP VIEW

A1

A

D2

16

17

18

19

20

COMMON DIMENSIONS

(Unit of Measure = mm)

C0.18 (8X)

MIN

0.75

0.00

0.17

MAX

0.85

0.05

0.27

NOM

0.80

0.02

0.22

0.152

3.00

1.55

3.00

1.55

0.45

0.40

–

NOTE

SYMBOL

15

14

13

12

11

1

2

3

4

5

A

Pin #1 Chamfer

(C 0.3)

A1

b

e

E2

C

D

D2

E

2.90

1.40

2.90

1.40

–

3.10

1.70

3.10

1.70

–

E2

e

b

10

9

8

7

6

L

0.35

0.20

0.00

0.45

–

0.3 Ref (4x)

K

L

K

BOTTOM VIEW

y

–

0.08

10/24/08

GPC

DRAWING NO.

TITLE

REV.

20M2, 20-pad,3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm,

1.55 x 1.55 mm Exposed Pad, Thermally Enhanced

Plastic Very Thin Quad Flat No Lead Package (VQFN)

Package Drawing Contact:

packagedrawings@atmel.com

ZFC

20M2

B

17

8246BS–AVR–09/11

8. Errata

The revision letters in this section refer to the revision of the corresponding ATtiny2313A/4313

device.

8.1

ATtiny2313A

8.1.1

Rev. D

No known errata.

8.1.2

Rev. A – C

These device revisions were referred to as ATtiny2313/ATtiny2313V.

8.2

ATtiny4313

8.2.1

Rev. A

No known errata.

18

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

9. Datasheet Revision History

9.1

Rev. 8246B – 10/11

1. Updated device status from Preliminary to Final.

2. Updated document template.

3. Added order codes for tape&reel devices, on page 259 and page 260

4. Updated figures:

– Figure 23-33 on page 223

– Figure 23-44 on page 228

– Figure 23-81 on page 247

– Figure 23-92 on page 252

5. Updated sections:

– Section 5. “Memories” on page 15

– Section 19. “Self-Programming” on page 172

– Section 20. “Lock Bits, Fuse Bits and Device Signature” on page 177

– Section 21. “External Programming” on page 183

– Section 26. “Ordering Information” on page 259

9.2

Rev. 8246A – 11/09

1. Initial revision. Created from document 2543_t2313.

2. Updated datasheet template.

3. Added VQFN in the Pinout Figure 1-1 on page 2.

4. Added Section 7.2 “Software BOD Disable” on page 34.

5. Added Section 7.3 “Power Reduction Register” on page 34.

6. Updated Table 7-2, “Sleep Mode Select,” on page 36.

7. Added Section 7.5.3 “BODCR – Brown-Out Detector Control Register” on page 37.

8. Added reset disable function in Figure 8-1 on page 38.

9. Added pin change interrupts PCINT1 and PCINT2 in Table 9-1 on page 47.

10. Added PCINT17..8 and PCMSK2..1 in Section 9.2 “External Interrupts” on page 48.

11. Added Section 9.3.4 “PCMSK2 – Pin Change Mask Register 2” on page 52.

12. Added Section 9.3.5 “PCMSK1 – Pin Change Mask Register 1” on page 52.

13. Updated Section 10.2.1 “Alternate Functions of Port A” on page 61.

14. Updated Section 10.2.2 “Alternate Functions of Port B” on page 62.

15. Updated Section 10.2.3 “Alternate Functions of Port D” on page 66.

16. Added UMSEL1 and UMSEL0 in Section 14.10.4 “UCSRC – USART Control and Sta-

tus Register C” on page 139.

17. Added Section 15. “USART in SPI Mode” on page 145.

18. Added USI Buffer Register (USIBR) in Section 16.2 “Overview” on page 155 and in Fig-

ure 16-1 on page 155.

19. Added Section 16.5.4 “USIBR – USI Buffer Register” on page 166.

20. Updated Section 19.6.3 “Reading Device Signature Imprint Table from Firmware” on

page 175.

19

8246BS–AVR–09/11

21. Updated Section 19.7.1 “SPMCSR – Store Program Memory Control and Status Regis-

ter” on page 175.

22. Added Section 20.3 “Device Signature Imprint Table” on page 179.

23. Updated Section 20.3.1 “Calibration Byte” on page 180.

24. Changed BS to BS1 in Section 20.6.13 “Reading the Signature Bytes” on page 189.

25. Updated Section 22.2 “DC Characteristics” on page 198.

26. Added Section 23.1 “Effect of Power Reduction” on page 206.

27. Updated characteristic plots in Section 23. “Typical Characteristics” for ATtiny2313A

(pages 207 - 230), and added plots for ATtiny4313 (pages 231 - 254).

28. Updated Section 24. “Register Summary” on page 255 .

29. Updated Section 26. “Ordering Information” on page 259, added the package type

20M2 and the ordering code -MMH (VQFN), and added the topside marking note.

20

ATtiny2313A/4313

8246BS–AVR–09/11

ATtiny2313A/4313

21

8246BS–AVR–09/11

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia Limited

Unit 01-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

HONG KONG

Atmel Munich GmbH

Business Campus

Parkring 4

D-85748 Garching b. Munich

GERMANY

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1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

JAPAN

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Tel: (+49) 89-31970-0

Fax: (+49) 89-3194621

Tel: (852) 2245-6100

Fax: (852) 2722-1369

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

avr@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

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8246BS–AVR–09/11