ASM0912C--Datasheet/数据表在线中文翻译

ASM0912C

ASM0912C –VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

1.0 General Description

The ASM0912C is very low cost voice synthesizer with 4-bit microprocessor. It has various

features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog

timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS

technology and halt function can minimize power dissipation. Its architecture is similar to RISC,

with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,

except for program branches and data table read instructions (which need two instruction

cycles).

1.1 Feature

^ꢀSingle power supply can operate from 2.4V through 5.5V

^ꢀInternal Program ROM: 4K x 10-bit

^ꢀ1 sets of 16-bit DPR can access up to 32K x 10 bits data memory space

^ꢀData Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh

^ꢀI/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)

^ꢀOn-chip clock generator:

^ꢀTimer: 1

Resistive Clock Drive(RM)

• Timer0: a 9-bit auto-reload timer/counter

^ꢀStack: 2-level subroutine nesting

^ꢀHALT and Release from HALT function to reduce power consumption

^ꢀWatch Dog Timer (WDT)

^ꢀInstruction: 1-cycle instruction except for table read and program branches which are 2-cycles

^ꢀNumber of instruction: 22

^ꢀThe Voice function can be implemented by microprocessor instruction

• One 8-bit COUT output for ASMxxxxx

1

Rev 1.0

ASM0912C

FIGURE 1.1 : Block Diagram of ASM0912C

Data Bus[3:0]

ROM Latch

PCLATCH(8)

PCH(8)

PCL(4)

Stack(12)

(2-Level)

PC[11:0]

Instruction

Latch

(ADDR[14:12])

=0000b

ROM_ADDR[14:0]

ADDR[14:0]

0

1

Instruction Bus [9:0]

DPR3,2,1

Program

(Data)

ROM

Instruction

Decoder

DPR[14:0]

Control Signal

DLATCH(10)

ROM_Data[9:0]

Data Bus[3:0]

Instruction Bus [9:0]

Timer0(9)

Accumlator(4)

PRA(4)

SRAM

PRB(4)

PRC(4)

(96 x 4)

Immediate(4)

ALU(4)

00h-1Fh

40h-7Fh

Register(4)

weak or strong

pull-low for PRA,

PRB, PRC

P1,P2,P3,P4

Clock Generator

OSC

PRASL(4)

enter test mode

Reset Chip

Test select

One-Channel

Power on Reset

VDD/GND

( Voice synthesizer )

Reset Chip

RESET pin

COUT

2

Rev 1.0

ASM0912C

FIGURE 1.2 : External ROM Map of ASM0912C

PC[11:0]

12bit x 2 STACK

15-bit Data Pointer

Reset Vector

00000h

00080h

00080h-003FFh

Reserved for Testing

00400h

00000h-00FFFh

00FFFh(4K)

00000h-07FFFh

07FFFh(32Kx10-bits)

3

Rev 1.0

ASM0912C

1.2 Pin-Out

ASM0912C Pin-Out

PRC1

I

STI

Input port with programmable strong pull-low or weak pull-low or

Std./O.D. fix-input-floating capability

PRC0/RESET

I

STI

Input port with programmable strong pull-low or weak pull-low or

Std./O.D. fix-input-floating capability

Mask option selected as an external RESET pin with weak pull-low

capability

I/O port with programmable strong pull-low or weak pull-low or

Std./O.D. fix-input-floating capability

Output type with standard or Open-Drain output

I/O port with programmable strong pull-low or weak pull-low or

Std./O.D. fix-input-floating capability

PRA3-1

I/O

STI

PRA0/RESET

STI

Output type with standard or Open-Drain output

Mask option selected as an external RESET pin with weak pull-low

capability

OSC

I

-

RM mode Oscillator input

VDD1

COUT

GND1

GND2

TEST

First Power supply during operation

Current Output of Audio

O

I

First Circuit Ground Potential

I

Second Circuit Ground Potential

Enter Test Mode. ( TEST = High )

Second Power supply during operation

O

I

VDD2

PRB0-3

PRC2-3

O

I

Std./O.D. Output type with standard or Open-Drain output

STI

Input port with programmable strong pull-low or weak pull-low or

Std./O.D. fix-input-floating capability

1.3 Application circuit

4

Rev 1.0

ASM0912C

1.4 Bonding Diagram

19

18

17

16

15

14

13

12

RC3

RC2

RC1

RC0

GND2 VDD2 TEST OSC

( 32K x 10-bit ) Block ROM

ASM0912C

RA3 RA2

RA1 RA0 VDD1 COUT GND1 RB0

RB1

9

RB2

10

RB3

11

1

2

3

4

5

6

7

8

Substrate must be connected to GND.

ASM0912C Pad Location

Chip Size: X= 1540+80

(um), Y=1510+80

X

(um)

PAD # PAD Name

X

Y

PAD # PAD Name

Y

1

2

RA3

-682.16

-559.84

-437.52

-315.2

-191.28

71.12

-638.92

11

12

13

14

15

16

17

18

19

RB3

674.88

633.56

432.48

273.16

134.68

-51.76

-638.92

670.24

RA2

OSC

TEST

VDD2

GND2

RC0

3

RA1

4

RA0

5

VDD1

COUT

GND1

RB0

6

7

189.52

307.92

430.24

552.56

RC1

-248.4

8

RC2

-454.24

-650.88

9

RB1

RC3

10

RB2

5

Rev 1.0

ASM0912C

1.5 DC Characteristics for ASMxxxxx

SYMBOL

PARAMETER

VDD MIN. TYP. MAX. UNIT

CONDITION

depending on Freq.

4MHz, RM

VDD

OPERATING VOLTAGE

2.4

3

5.5

1

V

3

5

3

5

3

5

Isb

STANDBY

uA

in HALT Mode

SUPPLY

1

CURRENT

2

7

3

9

4MHz, RM

IO Floating

Iop

OPERATING

mA

4MHz, RM

INPUT CURRENT

/Internal pull low

in HALT Mode

(IO Ports with weak

pull-high pull-low)

Iih

uA

5

-5.2

3

5

3

5

3

5

-3

-8

7

Ioh

Iol

OUTPUT HIGH CURRENT

OUTPUT LOW CURRENT

mA

4MHz, RM

(IO ports)

20

4

DA CURRENT OUT

(FULL SCALE)

FREQUENCY

STABILITY

Cout

dF/F

5.2

Fosc(3v- 2.4v)

Fosc (3v)

-10

-20

10

20

%

VDD=3V,

Fosc VARIATION

Rosc=200k, 4MHz

FIGURE 1.3 : Frequency Range for Rosc in RM mode

Resistor(k ohm)

3v Freq.(MHz)

300

2.7

200

4.1

130

6.7

100

8.0

Rosc & Freq.

10

8

6.7

6

4.1

4

2.7

2

0

100

200

300

400

Rosc k ohm

6

Rev 1.0