935047940602--Datasheet/数据表在线中文翻译

INTEGRATED CIRCUITS

74ABT648

Octal transceiver/register, inverting

(3-State)

Product data

2002 Dec 13

Supersedes data of 1998 Jun 08

Philips

Semiconductors

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

The 74ABT648 transceiver/register consists of bus transceiver

FEATURES

circuits with inverting 3-State outputs, D-type flip-flops, and control

circuitry arranged for multiplexed transmission of data directly from

the input bus or the internal registers. Data on the A or B bus will be

clocked into the registers as the appropriate clock pin goes HIGH.

Output Enable (OE) and DIR pins are provided to control the

transceiver function. In the transceiver mode, data present at the

high impedance port may be stored in either the A or B register or

both.

• Combines 74ABT245 and 74ABT374 type functions in one device

• Independent registers for A and B buses

• Multiplexed real-time and stored data

• Output capability: +64 mA / –32 mA

• Power-up 3-state

• Power-up reset

The Select (SAB, SBA) pins determine whether data is stored or

transferred through the device in real-time. The DIR determines

which bus will receive data when the OE is active (LOW). In the

isolation mode (OE = HIGH), data from Bus A may be stored in the

B register and/or data from Bus B may be stored in the A register.

Outputs from real-time, or stored registers will be inverted. When an

output function is disabled, the input function is still enabled and

may be used to store and transmit data. Only one of the two buses,

A or B may be driven at a time. The examples on the next page

demonstrate the four fundamental bus management functions that

can be performed with the 74ABT648.

• Live insertion/extraction permitted

• Latch-up protection exceeds 500 mA per Jedec Std 17

• ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

DESCRIPTION

The 74ABT648 high-performance BiCMOS device combines low

static and dynamic power dissipation with high speed and high

output drive.

QUICK REFERENCE DATA

CONDITIONS

= 25 °C; GND = 0 V

SYMBOL

PARAMETER

TYPICAL

UNIT

ns

T

amb

t

Propagation delay

An to Bn or Bn to An

PLH

PHL

C = 50 pF; V = 5 V

5.9

4

L

CC

Input capacitance

CP, S, OE, DIR

C

V = 0 V or V

CC

pF

IN

I

Outputs disabled;

= 0 V or V

C

I/O capacitance

7

pF

I/O

V

O

CC

I

Total supply current

Outputs disabled; V =5.5 V

110

µA

CCZ

CC

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

PART NUMBER

74ABT648D

DWG NUMBER

SOT137-1

24-Pin plastic SO

–40 °C to +85 °C

24-Pin Plastic TSSOP Type I

74ABT648PW

SOT355-1

PIN CONFIGURATION

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

A to B clock input /

CPAB

SAB

DIR

A0

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

V

CC

CPAB /

CPBA

1, 23

B to A clock input

CPBA

SBA

OE

B0

SAB /

SBA

A to B select input /

B to A select input

2, 22

3

DIR

Direction control input

A1

4, 5, 6, 7,

8, 9, 10, 11

A2

B1

A0 – A7

Data inputs/outputs (A side)

A3

B2

20, 19, 18, 17,

16, 15, 14, 13

B0 – B7

Data inputs/outputs (B side)

A4

B3

A5

B4

Output enable input

(active-LOW)

21

OE

A6 10

A7 11

B5

12

24

GND

Ground (0 V)

B6

GND 12

B7

V

CC

Positive supply voltage

SA00082

2

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

LOGIC SYMBOL

LOGIC SYMBOL (IEEE/IEC)

21

G3

4

5

6

7

8

9

10 11

3EN1 [BA]

3

22

2

3EN2 [AB]

G6

G7

C4

C5

A0 A1 A2 A3 A4 A5 A6 A7

23

1

2

CPAB

SAB

3

23

22

21

DIR

≥1

1

6

4D

2

CPBA

SBA

OE

4

20

6 1

5D

1

7

≥1

B0 B1 B2 B3 B4 B5 B6 B7

19

18

5

6

20 19 18 17 16 15 14 13

17

16

7

8

9

SA00083

15

14

10

11

13

SA00156

REAL TIME BUS TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A OR B

BUS B TO BUS A

OE DIR CPAB CPBA SAB SBA

L

X

L

H

X

L

X

L

H

X

↑

X

↑

X

↑

L

X

L

H

H or L

X

H

X

H

H or L

↑

SA00177

3

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

FUNCTION TABLE

INPUTS

CPAB

DATA I/O

OPERATING MODE

OE

DIR

CPBA

SAB

SBA

An

Bn

Unspecified

output*

X

↑

X

Input

Store A, B unspecified

Unspecified

output*

X

↑

X

Input

Store B, A unspecified

H

X

↑

X

Store A and B data

Isolation, hold storage

Input

Output

Input

H or L

L

X

L

H

Real time B data to A bus

Stored B data to A bus

Input

H or L

L

H

X

L

H

X

Real time A data to B bus

Stored A data to B bus

Output

H or L

H

L

X

↑

=

HIGH voltage level

LOW voltage level

Don’t care

LOW-to-HIGH clock transition

*

The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled, i.e.,

data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.

LOGIC DIAGRAM

21

OE

3

DIR

CPBA

SBA

23

22

1

CPAB

SAB

2

1of 8 Channels

1D

C1

Q

4

20

A0

B0

1D

C1

Q

19

18

17

16

15

14

13

5

A1

A2

A3

A4

A5

A6

A7

B1

B2

B3

B4

B5

B6

B7

6

7

8

DETAIL A X 7

9

10

11

SA00081

4

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

1, 2

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

–0.5 to +7.0

–18

UNIT

V

CC

I

IK

DC input diode current

V < 0 V

I

mA

V

3

V

I

DC input voltage

–1.2 to +7.0

–50

I

DC output diode current

V

O

< 0 V

mA

V

OK

3

V

DC output voltage

output in Off or HIGH state

output in LOW state

–0.5 to +5.5

128

OUT

I

DC output current

mA

°C

T

stg

Storage temperature range

–65 to 150

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

UNIT

Min

4.5

0

Max

V

DC supply voltage

5.5

V

CC

V

Input voltage

V

CC

I

V

HIGH-level input voltage

LOW-level Input voltage

HIGH-level output current

LOW-level output current

Input transition rise or fall rate

2.0

V

IH

V

0.8

–32

64

V

IL

I

mA

ns/V

°C

OH

I

OL

∆t/∆v

0

10

T

amb

Operating free-air temperature range

–40

+85

5

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

DC ELECTRICAL CHARACTERISTICS

LIMITS

T

= –40 °C

to +85 °C

amb

SYMBOL

PARAMETER

TEST CONDITIONS

T

amb

= +25 °C

UNIT

Min

Typ

–0.9

3.2

Max

Min

Max

V

Input clamp voltage

V

= 4.5 V; I = –18 mA

–1.2

V

IK

CC

IK

= 4.5 V; I = –3 mA; V = V or V

2.5

3.0

2.0

2.5

3.0

2.0

OH

I

IL

IH

V

OH

HIGH-level output voltage

Power-up output low

= 5.0 V; I = –3 mA; V = V or V

3.7

OH

I

IL

= 4.5 V; I = –32 mA; V = V or V

IH

2.3

OH

I

IL

V

RST

V

CC

= 5.5 V; I = 1 mA; V = GND or V

CC

0.13

0.55

V

O

I

3

voltage

V

LOW-level output voltage

Power-off leakage current

Power-up/down 3-State

V

= 4.5 V; I = 64 mA; V = V or V

IH

0.42

0.55

V

OL

CC

OL

I

IL

I

= 0.0 V; V or V ≤ 4.5 V

±5.0

±100

µA

OFF

CC

I

O

V

CC

V

OE

= 2.1 V; V = 0.5 V; V = GND or V

;

CC

O

I

±5.0

±50

µA

PU/ PD

4

output current

= Don’t care

I

Control pins

V

= 5.5 V; V = GND or 5.5 V

±0.01

±5

±1.0

±100

50

±1.0

±100

50

µA

mA

I

CC

I

Input leakage

current

Data pins

= 5.5 V; V = GND or 5.5 V

I

IH

+ I

3-State output HIGH current

3-State output LOW current

Output HIGH leakage current

= 5.5 V; V = 2.7 V; V = V or V

5.0

OZH

OZL

O

I

IL

IH

I

IL

= 5.5 V; V = 0.5 V; V = V or V

–5.0

5.0

–50

50

–50

50

O

I

IL

I

= 5.5 V; V = 5.5 V; V = GND or V

CC

CEX

O

I

1

I

O

Output current

= 5.5 V; V = 2.5 V

–50

–65

–180

–50

–180

O

= 5.5 V; Outputs HIGH,

I

110

20

250

30

250

30

µA

mA

µA

CCH

V = GND or V

I

CC

V

CC

= 5.5 V; Outputs LOW,

I

Quiescent supply current

CCL

CCZ

V = GND or V

I

CC

V

CC

= 5.5 V; Outputs 3-State;

110

0.3

250

1.5

250

1.5

V = GND or V

I

CC

Additional supply current per

V

CC

= 5.5 V; one input at 3.4 V,

∆I

CC

mA

2

input pin

other inputs at V or GND; V = 5.5 V

CC CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4 V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V between 0 V and 2.1 V, with a transition time of up to 10 msec. From V = 2.1 to V = 5 V ± 10% a

CC

transition time of up to 100 µsec is permitted.

6

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

AC CHARACTERISTICS

GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω

R

F

L

LIMITS

T

V

= +25 °C

= +5.0 V

T

= –40 °C to +85 °C

amb

CC

amb

V

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0 V ±0.5 V

CC

Min

Typ

Max

Min

Max

f

Maximum clock frequency

1

125

200

125

MHz

ns

MAX

t

Propagation delay

CPAB to Bn or CPBA to An

2.2

1.7

5.3

5.9

6.8

7.4

2.2

1.7

7.8

8.4

PLH

PHL

t

Propagation delay

An to Bn or Bn to An

2

3

1.0

1.5

3.6

4.2

5.1

5.6

1.0

1.5

6.1

6.3

PLH

PHL

ns

t

Propagation delay

SAB to Bn or SBA to An

2

3

1.5

4.9

5.4

6.1

6.9

1.5

7.1

7.7

PLH

PHL

t

Output enable time

OE to An or Bn

5

6

1.0

2.1

4.3

5.5

5.3

7.4

1.0

2.1

6.3

8.8

PZH

t

PZL

Output disable time

OE to An or Bn

5

6

1.5

6.2

6.0

7.3

7.0

1.5

8.3

7.5

PHZ

t

PLZ

Output enable time

DIR to An or Bn

5

6

1.2

2.5

4.8

6.0

5.7

9.0

1.2

2.5

6.7

9.5

PZH

t

PZL

Output disable time

DIR to An or Bn

5

6

1.5

5.9

6.3

6.7

7.2

1.5

7.7

8.2

PHZ

t

PLZ

AC SET-UP REQUIREMENTS

GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω

R

F

L

LIMITS

T

V

= +25 °C

= +5.0 V

T

= -40 °C to +85 °C

amb

CC

amb

V

SYMBOL

PARAMETER

WAVEFORM

UNIT

= +5.0 V ±0.5 V

CC

Min

Typ

Min

t (H)

t (L)

s

Set-up time

An to CPAB, Bn to CPBA

3.0

1.5

1.0

3.0

s

4

1

ns

t (H)

Hold time

An to CPAB, Bn to CPBA

0.0

–0.4

–1.0

0.0

h

t (L)

h

t (H)

Pulse width, High or Low

CPAB or CPBA

3.5

4.0

2.6

1.0

3.5

4.0

w

t (L)

w

7

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

AC WAVEFORMS

V

M

= 1.5 V, V = GND to 3.0 V

IN

1/f

MAX

SBA or SAB

An or Bn

CPBA or

CPAB

V

M

t

V

t

M

t

M

t

PLH

PHL

(H)

t (L)

w

t

PHL

PLH

An or Bn

SA00088

V

M

An or Bn

V

M

SA00087

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

Waveform 2. Propagation Delay, SAB to Bn or SBA to An

An or Bn

V

M

An or Bn

SBA or SAB

V

M

t

t (H)

t (L)

s

t

(H)

t (L)

h

s

h

t

W

(L)

PHL

PLH

CPBA or

CPAB

V

Bn or An

SA00178

M

V

M

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

SA00090

Waveform 3. Propagation Delay, An to Bn or Bn to An,

and SBA to An or SAB to Bn

Waveform 4. Data Set-up and Hold Times

OE

V

M

t

V

M

t

DIR

t

PZL

PLZ

t

PZH

PHZ

V

–0.3V

0V

V

M

OH

An or Bn

V

+0.3V

0V

An or Bn

V

OL

M

SA00180

SA00179

Waveform 6. 3-State Output Enable Time to LOW Level and

Output Disable Time from LOW Level

Waveform 5. 3-State Output Enable Time to HIGH Level and

Output Disable Time from HIGH Level

8

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

TEST CIRCUIT AND WAVEFORM

7 V

500 Ω

S1

From Output

Under Test

Open

GND

500 Ω

C

= 50 pF

L

Load Circuit

TEST

S1

t

open

7 V

pd

t

/t

PLZ PZL

t

/t

open

PHZ PZH

DEFINITIONS

C

=

Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

L

SA00012

9

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

10

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

11

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

REVISION HISTORY

Rev

Date

Description

_3

20021213

Product data (9397 750 10848); ECN 853-1613 29294 of 12 December 2002.

Supersedes data of 08 June 1998 (9397 750 04022).

Modifications:

• Ordering information table: remove “North America” column; remove 74ABT648N and 74ABT648DB package

offerings.

_2

19980608

Product specification (9397 750 04022). ECN 853-1613 19516 of 08 June 1998.

Supersedes data of 17 April 1995.

12

2002 Dec 13

Philips Semiconductors

Product data

Octal bus transceiver/register, inverting (3-State)

74ABT648

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 12-02

9397 750 10848

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

13

2002 Dec 13