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INTEGRATED CIRCUITS  
DATA SHEET  
PCF8573  
Clock/calendar with serial I/O  
Product specification  
2003 Jan 27  
Supersedes data of 1997 March 28  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
CONTENTS  
1
2
3
4
5
6
7
FEATURES  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
ORDERING INFORMATION  
BLOCK DIAGRAM  
PINNING  
FUNCTIONAL DESCRIPTION  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
Oscillator  
Prescaler and time counter  
Alarm register  
Comparator  
Power on/power fail detection  
Interface level shifters  
8
CHARACTERISTICS OF THE I2C-BUS  
8.1  
8.2  
8.3  
8.4  
Bit transfer  
Start and stop conditions  
System configuration  
Acknowledge  
9
I2C-BUS PROTOCOL  
9.1  
9.2  
Addressing  
Clock/calendar READ/WRITE cycles  
10  
11  
12  
13  
14  
15  
16  
LIMITING VALUES  
HANDLING  
DC CHARACTERISTICS  
AC CHARACTERISTICS  
APPLICATION INFORMATION  
PACKAGE OUTLINES  
SOLDERING  
16.1  
Introduction  
16.2  
Through-hole mount packages  
Soldering by dipping or by solder wave  
Manual soldering  
Surface mount packages  
Reflow soldering  
Wave soldering  
Manual soldering  
Suitability of IC packages for wave, reflow and  
dipping soldering methods  
16.2.1  
16.2.2  
16.3  
16.3.1  
16.3.2  
16.3.3  
16.4  
17  
18  
19  
20  
DATA SHEET STATUS  
DEFINITIONS  
DISCLAIMERS  
PURCHASE OF PHILIPS I2C COMPONENTS  
2003 Jan 27  
2
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
1
FEATURES  
• Serial input/output I2C-bus interface for minutes, hours,  
days and months  
• Additional pulse outputs for seconds and minutes  
• Alarm register for presetting a time for alarm or remote  
switching functions  
The IC incorporates an addressable time counter and an  
addressable alarm register for minutes, hours, days and  
months. Three special control/status flags, COMP, POWF  
and NODA, are also available. Back-up for the clock during  
supply interruptions is provided by a 1.2 V nickel cadmium  
battery. The time base is generated from a 32.768 kHz  
crystal-controlled oscillator.  
• On-chip power fail detector  
• Separate ground pin for the clock allows easy  
implementation of battery back-up during supply  
interruption  
• Crystal oscillator control (32.768 kHz)  
• Low power consumption.  
2
GENERAL DESCRIPTION  
The PCF8573 is a low threshold, CMOS circuit that  
functions as a real time clock/calendar. Addresses and  
data are transferred serially via the two-line bidirectional  
I2C-bus.  
3
QUICK REFERENCE DATA  
SYMBOL  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
V
DD − VSS1  
supply voltage, clock (pin 16 to pin 15)  
supply voltage, I2C-bus (pin 16 to pin 8)  
crystal oscillator frequency  
1.1  
2.5  
−
−
−
6.0  
6.0  
−
V
V
VDD − VSS2  
fosc  
32.768  
kHz  
4
ORDERING INFORMATION  
PACKAGE  
TYPE NUMBER  
NAME  
DESCRIPTION  
VERSION  
PCF8573P  
PCF8573T  
DIP16  
SO16  
plastic dual in-line package; 16 leads (300 mil)  
plastic small outline package; 16 leads; body width 7.5 mm  
SOT38-4  
SOT162-1  
2003 Jan 27  
3
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
5
BLOCK DIAGRAM  
V
FSET  
SEC MIN  
DD  
16  
11  
LS  
10  
9
1.5 V  
32.768 kHz  
POWER-ON 15  
RESET  
14  
13  
OSCO  
LS  
SECONDS  
COUNTER  
1 : 60  
PRESCALER  
OSCILLATOR  
15  
1 : 2  
OSCI  
8
V
SS2  
CT  
4
5
6
7
SDA  
EXTPF  
PFIN  
TIME COUNTER  
DAYS  
V
N
DD  
MONTHS  
MINUTES  
HOURS  
DATE  
SCL  
LS  
3
LS  
LS  
COMP  
TEST  
COMPARATOR  
2
I C  
INPUT  
FILTER  
12  
BUS  
CONTROL  
ALARM REGISTER  
LS  
LS  
LEVEL SHIFTER  
PCF8573  
1
2
MBL804  
A0  
A1  
Fig.1 Block diagram.  
6
PINNING  
SYMBOL PIN  
DESCRIPTION  
A0  
1
2
3
4
5
6
7
8
9
address input  
A1  
address input  
handbook, halfpage  
A0  
A1  
1
2
3
4
5
6
7
8
16  
15  
V
DD  
COMP  
SDA  
SCL  
comparator output  
serial data line; I2C-bus  
serial clock line; I2C-bus  
enable power fail flag input  
power fail flag input  
V
SS1  
COMP  
SDA  
14 OSCO  
13 OSCI  
12 TEST  
11 FSET  
10 SEC  
EXTPF  
PFIN  
VSS2  
MIN  
PCF8573P  
SCL  
negative supply 2 (I2C interface)  
EXTPF  
PFIN  
one pulse per minute output  
SEC  
FSET  
TEST  
OSCI  
OSCO  
VSS1  
VDD  
10 one pulse per second output  
11 oscillator tuning output  
12 test input; connect to VSS2 if not in use  
13 oscillator input  
V
9
MIN  
SS2  
MBL805  
14 oscillator input/output  
15 negative supply 1 (clock)  
16 common positive supply  
Fig.2 Pinning diagram (DIP16).  
2003 Jan 27  
4
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
advance the seconds counter. The carry of the prescaler  
and the seconds counter are available at the outputs SEC,  
MIN respectively, and are also readable via the I2C-bus.  
The mark-to-space ratio of both signals is 1 : 1. The time  
counter is advanced one count by the falling edge of output  
signal MIN. A transition from HIGH-to-LOW of output  
signal SEC triggers MIN to change state.  
handbook, halfpage  
A0  
A1  
1
2
3
4
5
6
7
8
16  
15  
V
V
DD  
SS1  
COMP  
SDA  
14 OSCO  
13 OSCI  
12 TEST  
11 FSET  
10 SEC  
The time counter counts minutes, hours, days and months,  
and provides a full calendar function which needs to be  
corrected only once every four years - to allow for  
leap-year. Cycle lengths are shown in Table 1.  
PCF8573T  
SCL  
EXTPF  
PFIN  
7.3  
Alarm register  
The alarm register is a 24-bit memory. It stores the  
time-point for the next setting of the status flag COMP.  
Details of writing and reading of the alarm register are  
included in the description of the characteristics of the  
I2C-bus.  
V
9
MIN  
SS2  
MBL806  
Fig.3 Pinning diagram (SO16).  
7.4  
Comparator  
The comparator compares the contents of the alarm  
register and the time counter, each with a length of 24 bits.  
When these contents are equal the flag COMP will be set  
4 ms after the falling edge of MIN. This set condition  
occurs once at the beginning of each minute. This  
information is latched, but can be cleared by an instruction  
via the I2C-bus. A clear instruction may be transmitted  
immediately after the flag is set and will be executed. Flag  
COMP information is also available at the output COMP.  
The comparison may be based upon hours and minutes  
only if the internal flag NODA (no date) is set. Flag NODA  
can be set and cleared by separate instructions via the  
I2C-bus, but it is undefined until the first set or clear  
instruction has been received. Both COMP and NODA  
flags are readable via the I2C-bus.  
7
FUNCTIONAL DESCRIPTION  
Oscillator  
7.1  
The PCF8573 has an integrated crystal-controlled  
oscillator which provides the timebase for the prescaler.  
The frequency is determined by a single 32.768 kHz  
crystal connected between OSCI and OSCO. A trimmer is  
connected between OSCI and VDD  
.
7.2 Prescaler and time counter  
The prescaler provides a 128 Hz signal at the FSET output  
for fine adjustment of the crystal oscillator without loading  
it. The prescaler also generates a pulse once a second to  
2003 Jan 27  
5
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
Table 1 Cycle length of the time counter  
CARRY FOR  
FOLLOWING UNIT  
CONTENT OF MONTH  
COUNTER  
UNIT  
minutes  
NUMBER OF BITS  
COUNTING CYCLE  
7
00 to 59  
00 to 23  
01 to 28  
59 → 00  
23 → 00  
28 → 01  
or 29 → 01  
30 → 01  
31 → 01  
12 → 01  
hours  
days(1)  
6
6
2
2
01 to 30  
01 to 31  
01 to 12  
4, 6, 9, 11  
1, 3, 5, 7, 8, 10, 12  
months  
5
Note  
1. During February of a leap-year the ‘Time Counter Days’ may be set to 29 by directly writing to it using the ‘execute  
address’ function. Leap-years must be tracked by the system software.  
7.5  
Power on/power fail detection  
The external power fail control operates by absence of the  
DD − VSS2 supply. Therefore the input levels applied to  
V
If the voltage VDD − VSS1 falls below a certain value, the  
operation of the clock becomes undefined. Therefore a  
warning signal is required to indicate that faultless  
operation of the clock is not guaranteed. This information  
is latched in a flag called POWF (Power Fail) and remains  
latched after restoration of the correct supply voltage until  
a write sequence with EXECUTE ADDRESS has been  
received. The flag POWF can be set by an internally  
generated power fail level-discriminator signal for  
applications with (VDD − VSS1) greater than VTH1, or by an  
externally generated power fail signal for applications with  
(VDD − VSS1) less than VTH1. The external signal must be  
applied to the input PFIN. The input stage operates with  
signals of slow rise and fall times. Internally or externally  
controlled POWF can be selected by input EXTPF as  
shown in Table 2.  
PFIN and EXTPF must be within the range VDD − VSS1  
.
A LOW level at PFIN indicates a power fail. POWF is  
readable via the I2C-bus. A power-on reset for the I2C-bus  
control is generated on-chip when the supply voltage  
VDD − VSS2 is less than VTH2  
.
7.6 Interface level shifters  
The level shifters adjust the 5 V operating voltage  
(VDD − VSS2) of the microcontroller to the internal supply  
voltage (VDD − VSS1) of the clock/calendar. The oscillator  
and counter are not influenced by the VDD − VSS2 supply  
voltage. If the voltage VDD − VSS2 is absent (VDD = VSS2),  
the output signal of the level shifter is HIGH because VDD  
is the common node of the VDD − VSS2 and VDD − VSS1  
supplies. Because the level shifters invert the input  
signals, the internal circuit behaves as if a LOW signal is  
present on the inputs. FSET, SEC, MIN and COMP are  
CMOS push-pull output stages. The driving capability of  
these outputs is lost when the supply voltage  
Table 2 Power fail selection  
EXTPF(1)  
PFIN(1)  
FUNCTION  
power fail is sensed internally  
test mode  
0
0
1
0
1
VDD − VSS2 = 0.  
0
1
1
power fail is sensed externally  
no power fail sensed  
Note  
1. 0 = VSS1 (LOW); 1 = VDD (HIGH).  
2003 Jan 27  
6
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
8
CHARACTERISTICS OF THE I2C-BUS  
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line  
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when  
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.  
8.1  
Bit transfer  
See Fig.4. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the  
HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.  
SDA  
SCL  
data line  
stable;  
data valid  
change  
of data  
allowed  
MBC621  
Fig.4 Bit transfer.  
8.2  
Start and stop conditions  
Refer to Fig.5. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data  
line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the  
clock is HIGH is defined as the stop condition (P).  
SDA  
SCL  
SDA  
SCL  
S
P
STOP condition  
START condition  
MBC622  
Fig.5 Definition of start and stop conditions.  
2003 Jan 27  
7
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
8.3  
System configuration  
Refer to Fig.6. A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The  
device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.  
SDA  
SCL  
MASTER  
TRANSMITTER /  
RECEIVER  
SLAVE  
TRANSMITTER /  
RECEIVER  
MASTER  
TRANSMITTER /  
RECEIVER  
SLAVE  
RECEIVER  
MASTER  
TRANSMITTER  
MBA605  
Fig.6 System configuration.  
8.4  
Acknowledge  
The device that acknowledges must pull down the SDA  
line during the acknowledge clock pulse, so that the SDA  
line is stable LOW during the HIGH period of the  
acknowledge related clock pulse (set-up and hold times  
must be taken into consideration). A master receiver must  
signal an end of data to the transmitter by not generating  
an acknowledge on the last byte that has been clocked  
out of the slave. In this event the transmitter must leave the  
data line HIGH to enable the master to generate a stop  
condition, see Figs. 10 and 11.  
See Fig.7. The number of data bytes transferred between  
the start and stop conditions from transmitter to receiver is  
unlimited. Each byte of eight bits is followed by an  
acknowledge bit. The acknowledge bit is a HIGH level  
signal put on the bus by the transmitter during which time  
the master generates an extra acknowledge related clock  
pulse. A slave receiver which is addressed must generate  
an acknowledge after the reception of each byte. Also a  
master receiver must generate an acknowledge after the  
reception of each byte that has been clocked out of the  
slave transmitter.  
DATA OUTPUT  
BY TRANSMITTER  
not acknowledge  
acknowledge  
DATA OUTPUT  
BY RECEIVER  
SCL FROM  
1
2
8
9
MASTER  
S
clock pulse for  
acknowledgement  
START  
condition  
MBC602  
Fig.7 Acknowledgment on the I2C-bus.  
2003 Jan 27  
8
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
9
I2C-BUS PROTOCOL  
Addressing  
9.1  
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is  
always done with the first byte transmitted after the start procedure.  
The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal,  
but the data signal SDA is a bidirectional line.  
The clock/calendar slave address is shown in Fig.8. Bits A0 and A1 correspond to the two hardware address pins A0 and  
A1. Connecting these to VDD or VSS allows the device to have 1 of 4 different addresses.  
msb  
handbook, halfpage  
lsb  
A0 R/W  
MBL807  
1
1
0
1
0
A1  
Fig.8 Slave address.  
9.2  
Clock/calendar READ/WRITE cycles  
The I2C-bus configuration for different clock/calendar READ and WRITE cycles is shown in Figs 9, 10 and 11.  
The write cycle is used to set the time counter, the alarm register and the flags. The transmission of the clock/calendar  
address is followed by the MODE-POINTER-word which contains a CONTROL-nibble (Table 3) and an  
ADDRESS-nibble (Table 4). The ADDRESS-nibble is valid only if the preceding CONTROL-nibble is set to EXECUTE  
ADDRESS. The third transmitted word contains the data to be written into the time counter or alarm register.  
acknowledge  
from slave  
acknowledge  
from slave  
acknowledge  
from slave  
msb  
A
lsb  
R/W  
CLOCK/CALENDAR  
ADDRESS  
DATA  
S
A
P
0
A
MODE POINTER  
n bytes  
(n = 0, 1, 2, ...)  
auto increment  
of B1, B0  
0
C2 C1 C0 0 B2 B1 B0  
MBL808  
Fig.9 Master transmitter transmits to clock/calendar slave receiver.  
2003 Jan 27  
9
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
acknowledge  
from slave  
acknowledge  
from slave  
acknowledge  
from slave  
acknowledge  
from master  
R/W  
R/W msb  
lsb msb  
A
CLOCK/CALENDAR  
CLOCK/CALENDAR  
ADDRESS  
S
0
A
MODE POINTER  
A
S
1
A
DATA  
ADDRESS  
(n − 1) bytes  
at this moment master  
transmitter becomes  
master receiver, and  
CLOCK/CALENDAR  
becomes slave  
auto increment  
of B1, B0  
transmitter  
(1)  
no acknowledge  
lsb  
DATA  
1
P
th  
n
byte  
auto increment  
of B1, B0  
MBL809  
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked  
out of the slave.  
Fig.10 Master transmitter reads clock/calendar after setting mode pointer.  
acknowledge  
handbook, halfpage  
acknowledge  
from slave  
(1)  
from master  
R/W MSB  
LSB  
CLOCK/CALENDAR  
ADDRESS  
S
1
A
DATA  
A
P
n bytes  
auto increment  
of B1, B0  
MBL810  
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked  
out of the slave.  
Fig.11 Master reads clock/calendar immediately after first byte.  
2003 Jan 27  
10  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
Table 3 MODE-POINTER-word, CONTROL-nibble (bits 8, 7, 6 and 5)  
BIT 8  
C2  
C1  
C0  
FUNCTION  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
execute address  
read control/status flags  
reset prescaler, including seconds counter; without carry for minute counter  
time adjust, with carry for minute counter (note 1)  
reset NODA flag  
set NODA flag  
reset COMP flag  
Note  
1. If the seconds counter is below 30 there is no carry. This causes a time adjustment of max. −30 s. From the count  
30 there is a carry which adjusts the time by max. +30 s.  
Table 4 MODE-POINTER-word, ADDRESS-nibble (bits 4, 3, 2 and 1)  
BIT 4  
B2  
B1  
B0  
ADDRESSED TO:  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
time counter hours  
time counter minutes  
time counter days  
time counter months  
alarm register hours  
alarm register minutes  
alarm register days  
alarm register months  
At the end of each data word the address bits B1, B0 will be incremented automatically provided the preceding  
CONTROL-nibble is set to EXECUTE ADDRESS. There is no carry to B2.  
Table 5 shows the placement of the BCD upper and lower digits in the DATA byte for writing into the addressed part of  
the time counter and alarm register respectively.  
Table 6 shows the acknowledgement response of the clock calendar as a slave receiver.  
Table 5 Placement of BCD digits in the DATA byte; note 1  
MSB  
DATA  
LSB  
LA  
UPPER DIGIT  
LOWER DIGIT  
ADDRESSED TO:  
UD  
UC  
UB  
UA  
LD  
LC  
LB  
X
X
X
X
X
D
X
X
D
D
D
X
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
hours  
minutes  
days  
months  
Note  
1. ‘X’ is the don’t care bit; ‘D’ is the data bit.  
2003 Jan 27  
11  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
Acknowledgement response of the PCF8573 as slave-receiver is shown in Table 6. Note that data is only associated  
with the ‘execute address’ function where C0, C1, C2 = 0, 0, 0.  
Table 6 Slave receiver acknowledgement; note 1  
MODE POINTER  
ACKNOWLEDGE ON BYTE:  
MODE  
POINTER  
DATA  
BIT 8  
C2  
C1  
C0  
BIT 4  
B2  
B1  
B0  
ADDRESS  
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
X
0
0
0
1
1
0
0
1
1
X
0
0
1
0
1
0
1
0
1
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
no  
yes  
no  
no  
no  
no  
no  
no  
no  
no  
no  
X
X
X
X
X
X
X
X
yes  
yes  
yes  
yes  
yes  
yes  
no  
no  
Note  
1. ‘X’ is ‘don’t care’.  
To read the addressed part of the time counter and alarm register, plus information from specified control/status flags,  
the BCD digits in the DATA byte are organized as shown in Table 7.  
The status of the CONTROL-nibble of the MODE-POINTER-WORD (C2, C1, C0) remains unchanged until re-written.  
Table 7 Organization of the BCD digits in the DATA byte; note 1  
MSB  
DATA  
LSB  
LA  
UPPER DIGIT  
LOWER DIGIT  
ADDRESSED TO:  
UD  
UC  
UB  
UA  
LD  
LC  
LB  
0
0
0
0
0
0
D
0
0
0
D
D
D
0
D
D
D
D
m
D
D
D
D
s
D
D
D
D
D
D
D
D
hours  
minutes  
days  
D
D
D
D
months  
0
NODA  
COMP  
POWF control/status flags  
Note  
1. ‘D’ is the data bit; ‘m’ = minutes; ‘s’ = seconds.  
2003 Jan 27  
12  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
10 LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
DD − VSS1  
DD − VSS2  
PARAMETER  
supply voltage (pin 16 to pin 15)  
supply voltage (pin 16 to pin 8)  
input voltage  
MIN.  
MAX.  
UNIT  
V
V
−0.3  
−0.3  
+8.0  
+8.0  
V
V
Vl  
pins 4 and 5 (with input impedance of minimum 500 Ω) VSS2 − 0.8  
VDD + 0.8  
VDD + 0.6  
VDD + 0.6  
10  
V
V
V
pins 6, 7, 13 and 14  
any other pin  
V
V
−
−
−
−
SS1 − 0.6  
SS2 − 0.6  
Il  
DC input current  
mA  
mA  
mW  
mW  
°C  
IO  
DC output current  
10  
Ptot  
PO  
Tamb  
Tstg  
total power dissipation per package  
power dissipation per output  
operating ambient temperature  
storage temperature  
200  
100  
−40  
−55  
+85  
+125  
°C  
11 HANDLING  
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take  
normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).  
2003 Jan 27  
13  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
12 DC CHARACTERISTICS  
VSS2 = 0 V; Tamb = −40 to + 85 °C unless otherwise specified. Typical values at Tamb = 25 °C.  
SYMBOL  
Supply  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
V
V
DD − VSS2 supply voltage (I2C interface)  
DD − VSS1 supply voltage (clock)  
2.5  
1.1  
5.0  
6.0  
VDD − VSS2  
V
V
tHD;DAT ≥ 300 ns  
1.5  
ISS1  
supply current  
at VSS1 (pin 15)  
see Fig.12  
V
V
DD − VSS1 = 1.5 V  
DD − VSS1 = 5 V  
−
−
−
−3  
−12  
−
−10  
−50  
−50  
µA  
µA  
µA  
ISS2  
supply current  
at VSS2 (pin 8)  
V
DD − VSS2 = 5 V;  
IO = 0 all outputs  
Input SCL, input/output SDA  
VIL  
VIH  
ILI  
LOW level input voltage  
−
−
−
−
−
0.3VDD  
V
HIGH level input voltage  
input leakage current  
input capacitance  
0.7VDD  
−
V
VI = VSS2 or VDD  
−1  
+1  
7
µA  
pF  
Ci  
−
Inputs A0, A1, TEST  
VIL  
VIH  
ILI  
LOW level input voltage  
−
−
−
−
0.2VDD  
−
V
HIGH level input voltage  
input leakage current  
0.7VDD  
−250  
V
VI = VSS2 or VDD  
+250  
nA  
Inputs EXTPF, PFIN  
VIL  
VIH  
ILI  
LOW level input voltage  
0
−
−
−
−
0.2VDD − VSS1  
V
HIGH level input voltage  
input leakage current  
0.7VDD − VSS1  
−1.0  
−
V
VI = VSS1 to VDD  
VI = VSS1 to VDD  
amb = 25 °C  
+1.0  
+0.1  
µA  
µA  
;
−0.1  
T
Output SDA (N-channel open-drain)  
VOL  
LOW level output voltage  
output ON; IO = 3 mA;  
−
−
−
0.4  
V
V
DD − VSS2 = 2.5 to 6 V  
ILI  
input leakage current  
V
DD − VSS2 = 6 V;  
−1.0  
+1.0  
µA  
VO = 6 V  
Output SEC, MIN, COMP, FSET (normal buffer outputs)  
VOL  
LOW level output voltage  
V
DD − VSS2 = 2.5 V;  
IO = 0.3 mA  
DD − VSS2 = 4 to 6 V;  
IO = 1.6 mA  
DD − VSS2 = 2.5 V;  
IO = −0.1 mA  
DD − VSS2 = 4 to 6 V;  
IO = −0.5 mA  
−
−
−
−
−
−
0.4  
0.4  
−
V
V
V
V
V
VOH  
HIGH level output voltage  
V
V
V
DD − 0.4  
DD − 0.4  
V
−
2003 Jan 27  
14  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Internal threshold voltages  
VTH1  
VTH2  
power failure detection  
Power-on reset  
1
1.2  
2.0  
1.4  
2.5  
V
V
1.5  
MGL072  
−12  
handbook, halfpage  
I
SS1  
(µA)  
−8  
−4  
0
0
2
4
6
V
−V (V)  
DD SS1  
Fig.12 Typical supply current (ISS1) as a function of clock supply voltage (VDD − VSS1) at Tamb = −40 to +85 °C.  
2003 Jan 27  
15  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
13 AC CHARACTERISTICS  
VSS2 = 0 V; Tamb = −40 to +85 °C unless otherwise specified. Typical values at Tamb = +25 °C.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Rise and fall times of input signals  
tr  
rise time  
fall time  
input EXTPF  
−
−
−
−
−
−
1
∞
1
µs  
µs  
µs  
input PFIN  
all other inputs (levels  
between VIL and VIH)  
tf  
input EXTPF  
input PFIN  
−
−
−
−
−
−
1
µs  
µs  
µs  
∞
all other inputs (levels  
between VIL and VIH)  
0.3  
Oscillator  
Cosc  
Rf  
integrated oscillator capacitance  
oscillator feedback resistance  
oscillator stability  
−
−
−
40  
−
−
−
pF  
3
MΩ  
∆fosc  
∆(VDD − VSS1) = 100 mV;  
Tamb = 25 °C;  
2 × 10−7  
(VDD − VSS1) = 1.55 V  
Quartz crystal parameters (f = 32.768 kHz)  
Rs  
CL  
CT  
series resistance  
−
−
5
−
40  
−
kΩ  
pF  
pF  
parallel load capacitance  
trimmer capacitance  
10  
−
25  
I2C-bus timing (see Fig.13; notes 1 and 2)  
fSCL  
SCL clock frequency  
tolerable spike width on bus  
bus free time  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100  
100  
−
kHz  
ns  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
ns  
ns  
µs  
µs  
tSP  
tBUF  
4.7  
4.7  
4.0  
4.7  
4.0  
−
tSU;STA  
tHD;STA  
tLOW  
tHIGH  
tr  
START condition set-up time  
START condition hold time  
SCL LOW time  
−
−
−
SCL HIGH time  
−
SCL and SDA rise time  
SCL and SDA fall time  
data set-up time  
1.0  
0.3  
−
tf  
−
tSU;DAT  
tHD;DAT  
tVD;DAT  
tSU;STO  
250  
0
data hold time  
−
SCL LOW to data out valid  
STOP condition set-up time  
−
3.4  
−
4.0  
Notes  
1. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL  
and VIH with an input voltage swing of VSS to VDD  
.
2. A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to  
use it”. This brochure may be ordered using the code 9398 393 40011.  
2003 Jan 27  
16  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
START  
CONDITION  
(S)  
BIT 7  
MSB  
(A7)  
BIT 6  
(A6)  
BIT 0  
LSB  
(R/W)  
ACKNOWLEDGE  
(A)  
STOP  
CONDITION  
(P)  
PROTOCOL  
t
t
t
HIGH  
SU;STA  
LOW  
1 / f  
SCL  
SCL  
SDA  
t
t
t
f
BUF  
r
t
t
t
t
t
HD;STA  
SU;DAT  
VD;DAT  
SU;STO  
HD;DAT  
MBD820  
Fig.13 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.  
2003 Jan 27  
17  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
14 APPLICATION INFORMATION  
+5 V  
R: pull-up  
resistor  
R
R
V
DD  
SDA  
SCL  
PCF8570  
MASTER DEVICE  
MICROCONTROLLER  
128 × 8 BIT STATIC CMOS RAM  
V
SS  
32.768 kHz  
C
T
R1  
R2  
PCF8577  
EXTPF  
PFIN  
A0  
V
OSCO OSCI  
DD  
64 LCD  
SEGMENT DRIVER  
SDA  
SCL  
PCF8573  
R3  
A1  
V
TEST V  
SS2 SS1  
1.2 V  
(NiCa)  
8 DIGIT LCD  
MBL811  
R
: resistor for  
detection circuit  
with very high  
impedance  
ch  
permanent charging  
2
I C bus  
Fig.14 Application example of the PCF8573 clock/calendar with battery backup.  
+5 V  
1.5 V  
C
R
R
SDA  
SCL  
SCL SDA  
V
SCL SDA  
V
C
SCL SDA V  
DD  
DD  
DD  
T
A0  
A1  
OSCI  
MASTER  
MICRO-  
CONTROLLER  
PCF8573  
TEST  
PFIN  
PCF8571  
OSCO  
SS1  
EXTPF  
V
V
V
V
SS  
SS2  
SS  
MBL812  
Fig.15 Application example of the PCF8573 with common VSS1 and VSS2 supply.  
2003 Jan 27  
18  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
15 PACKAGE OUTLINES  
DIP16: plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
D
M
E
A
2
A
A
1
L
c
e
w M  
Z
b
1
(e )  
1
b
b
2
16  
9
M
H
pin 1 index  
E
1
8
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
(1)  
Z
A
A
A
2
(1)  
(1)  
1
w
UNIT  
mm  
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.  
min.  
max.  
max.  
1.73  
1.30  
0.53  
0.38  
1.25  
0.85  
0.36  
0.23  
19.50  
18.55  
6.48  
6.20  
3.60  
3.05  
8.25  
7.80  
10.0  
8.3  
4.2  
0.51  
3.2  
2.54  
0.10  
7.62  
0.30  
0.254  
0.01  
0.76  
0.068 0.021 0.049 0.014  
0.051 0.015 0.033 0.009  
0.77  
0.73  
0.26  
0.24  
0.14  
0.12  
0.32  
0.31  
0.39  
0.33  
inches  
0.17  
0.020  
0.13  
0.030  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
92-11-17  
95-01-14  
SOT38-4  
2003 Jan 27  
19  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
SO16: plastic small outline package; 16 leads; body width 7.5 mm  
SOT162-1  
D
E
A
X
c
H
v
M
A
E
y
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
detail X  
e
w
M
b
p
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
max.  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30  
0.10  
2.45  
2.25  
0.49  
0.36  
0.32  
0.23  
10.5  
10.1  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.1  
1.0  
0.9  
0.4  
mm  
2.65  
1.27  
0.050  
1.4  
0.25  
0.01  
0.25  
0.1  
0.25  
0.01  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.019 0.013 0.41  
0.014 0.009 0.40  
0.30  
0.29  
0.419  
0.394  
0.043 0.043  
0.016 0.039  
0.035  
0.016  
inches 0.10  
0.055  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
97-05-22  
99-12-27  
SOT162-1  
075E03  
MS-013  
2003 Jan 27  
20  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
16 SOLDERING  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 220 °C for  
thick/large packages, and below 235 °C for small/thin  
packages.  
16.1 Introduction  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
16.3.2 WAVE SOLDERING  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mount components are mixed on  
one printed-circuit board. Wave soldering can still be used  
for certain surface mount ICs, but it is not suitable for fine  
pitch SMDs. In these situations reflow soldering is  
recommended.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
If wave soldering is used the following conditions must be  
observed for optimal results:  
16.2 Through-hole mount packages  
• Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
16.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE  
The maximum permissible temperature of the solder is  
260 °C; solder at this temperature must not be in contact  
with the joints for more than 5 seconds. The total contact  
time of successive solder waves must not exceed  
5 seconds.  
• For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
The device may be mounted up to the seating plane, but  
the temperature of the plastic body must not exceed the  
specified maximum storage temperature (Tstg(max)). If the  
printed-circuit board has been pre-heated, forced cooling  
may be necessary immediately after soldering to keep the  
temperature within the permissible limit.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
The footprint must incorporate solder thieves at the  
downstream end.  
• For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
16.2.2 MANUAL SOLDERING  
Apply the soldering iron (24 V or less) to the lead(s) of the  
package, either below the seating plane or not more than  
2 mm above it. If the temperature of the soldering iron bit  
is less than 300 °C it may remain in contact for up to  
10 seconds. If the bit temperature is between  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
300 and 400 °C, contact may be up to 5 seconds.  
16.3 Surface mount packages  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
16.3.1 REFLOW SOLDERING  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
16.3.3 MANUAL SOLDERING  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C. When using a dedicated tool, all other leads can  
be soldered in one operation within 2 to 5 seconds  
between 270 and 320 °C.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
2003 Jan 27  
21  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
16.4 Suitability of IC packages for wave, reflow and dipping soldering methods  
SOLDERING METHOD  
WAVE  
REFLOW(2) DIPPING  
suitable(3)  
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable  
MOUNTING  
PACKAGE(1)  
Through-hole mount DBS, DIP, HDIP, SDIP, SIL  
−
suitable  
Surface mount  
suitable  
suitable  
−
−
HBCC, HBGA, HLQFP, HSQFP, HSOP,  
HTQFP, HTSSOP, HVQFN, HVSON, SMS  
not suitable(4)  
PLCC(5), SO, SOJ  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO  
suitable  
suitable  
−
−
−
not recommended(5)(6) suitable  
not recommended(7)  
suitable  
Notes  
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy  
from your Philips Semiconductors sales office.  
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
3. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.  
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder  
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,  
the solder might be deposited on the heatsink surface.  
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not  
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
7. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2003 Jan 27  
22  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
17 DATA SHEET STATUS  
DATA SHEET  
STATUS(1)  
PRODUCT  
STATUS(2)(3)  
LEVEL  
DEFINITION  
I
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
II  
Preliminary data Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Relevant changes will  
be communicated via a Customer Product/Process Change Notification  
(CPCN).  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
18 DEFINITIONS  
19 DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes in the products -  
including circuits, standard cells, and/or software -  
described or contained herein in order to improve design  
and/or performance. When the product is in full production  
(status ‘Production’), relevant changes will be  
Application information  
Applications that are  
communicated via a Customer Product/Process Change  
Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these  
products, conveys no licence or title under any patent,  
copyright, or mask work right to these products, and  
makes no representations or warranties that these  
products are free from patent, copyright, or mask work  
right infringement, unless otherwise specified.  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2003 Jan 27  
23  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
20 PURCHASE OF PHILIPS I2C COMPONENTS  
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the  
components in the I2C system provided the system conforms to the I2C specification defined by  
Philips. This specification can be ordered using the code 9398 393 40011.  
2003 Jan 27  
24  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
NOTES  
2003 Jan 27  
25  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
NOTES  
2003 Jan 27  
26  
Philips Semiconductors  
Product specification  
Clock/calendar with serial I/O  
PCF8573  
NOTES  
2003 Jan 27  
27  
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.  
© Koninklijke Philips Electronics N.V. 2003  
SCA75  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
403512/04/pp28  
Date of release: 2003 Jan 27  
Document order number: 9397 750 10463