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ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS85314I-01 is a low skew, high performance 1-to-5 • 5 differential 2.5V/3.3V LVPECL outputs  
Differential-to-2.5V/3.3V LVPECL Fanout Buffer.The  
• Selectable differential CLK0, nCLK0 or LVCMOS inputs  
ICS85314I-01 has two selectable clock inputs. The CLK0,  
nCLK0 pair can accept most standarddifferential input  
levels. The single-ended CLK1 can accept LVCMOS or  
LVTTL input levels. The clock enable is internally  
synchronized to eliminate runt clock pulses on the outputs  
during asynchronous assertion/deassertion of the  
clockenable pin.  
• CLK0, nCLK0 pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
• CLK1 can accept the following input levels:  
LVCMOS or LVTTL  
• Maximum output frequency: 700MHz  
• Translates any single-ended input signal to 3.3V  
Guaranteed output and part-to-part skew characteristics  
make the ICS85314I-01 ideal for those applications  
demanding well defined performance and repeatability.  
LVPECL levels with resistor bias on nCLK input  
• Output skew: 30ps (maximum), TSSOP package  
50ps (maximum), SOIC package  
• Part-to-part skew: 350ps (maximum)  
• Propagation delay: 1.8ns (maximum)  
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):  
0.05ps (typical)  
• LVPECL mode operating voltage supply range:  
VCC = 2.375V to 3.8V, VEE = 0V  
• -40°C to 85°C ambient operating temperature  
• Available in both standard and lead-free RoHS-compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
Q1  
nQ1  
Q2  
nQ2  
Q3  
nQ3  
Q4  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
nCLK_EN  
VCC  
D
nCLK_EN  
Q
LE  
CLK0  
nCLK0  
nc  
0
Q0  
nQ0  
CLK1  
CLK0  
nCLK0  
nc  
CLK_SEL  
VEE  
1
CLK1  
Q1  
nQ1  
CLK_SEL  
nQ4  
Q2  
nQ2  
ICS85314I-01  
20-Lead TSSOP  
Q3  
nQ3  
6.5mm x 4.4mm x 0.92mm Package Body  
G Package  
Q4  
nQ4  
Top View  
ICS85314I-01  
20-Lead SOIC  
7.5mm x 12.8mm x 2.3mm Package Body  
M Package  
Top View  
85314BGI-01  
www.idt.com  
REV. F JULY 25, 2010  
1
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
TABLE 1. PIN DESCRIPTIONS  
Number  
1, 2  
Name  
Q0, nQ0  
Q1, nQ1  
Q2, nQ2  
Q3, nQ3  
Q4, nQ4  
VEE  
Type  
Description  
Output  
Output  
Output  
Output  
Output  
Power  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
3, 4  
5, 6  
7, 8  
9, 10  
11  
Negative supply pin.  
Clock select input. When HIGH, selects CLK1 input.  
12  
CLK_SEL  
Input  
Pulldown When LOW, selects CLK0, nCLK0 inputs.  
LVTTL / LVCMOS interface levels.  
13, 17  
14  
nc  
Unused  
Input  
No connect.  
nCLK0  
CLK0  
CLK1  
VCC  
Pullup  
Inverting differential clock input.  
15  
Input  
Pulldown Non-inverting differential clock input.  
Pulldown Clock input. LVTTL / LVCMOS interface levels.  
Positive supply pins.  
16  
Input  
18, 20  
Power  
Synchronizing clock enable. When LOW, clock outputs follow clock  
Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced  
high. LVTTL / LVCMOS interface levels.  
19  
nCLK_EN  
Input  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
Input Pulldown Resistor  
4
RPULLUP  
RPULLDOWN  
51  
51  
kΩ  
kΩ  
85314BGI-01  
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REV. F JULY 25, 2010  
2
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
TABLE 3A. CONTROL INPUT FUNCTION TABLE  
Inputs  
Outputs  
nCLK_EN  
CLK_SEL  
Selected Source  
CLK0, nCLK0  
CLK1  
Q0:Q4  
Enabled  
nQ0:nQ4  
Enabled  
0
0
1
1
0
1
0
1
Enabled  
Enabled  
CLK0, nCLK0  
CLK1  
Disabled; LOW  
Disabled; LOW  
Disabled; HIGH  
Disabled; HIGH  
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge  
as shown in Figure 1.  
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs  
as described in Table 3B.  
Enabled  
Disabled  
nCLK0  
CLK0, CLK1  
nCLK_EN  
nQ0:nQ4  
Q0:Q4  
FIGURE 1. nCLK_EN TIMING DIAGRAM  
TABLE 3B. CLOCK INPUT FUNCTION TABLE  
Inputs  
Outputs  
Input to Output Mode  
Polarity  
CLK0 or CLK1  
nCLK0  
Q0:Q4  
LOW  
nQ0:nQ4  
HIGH  
0
1
1
0
Differential to Differential  
Differential to Differential  
Non Inverting  
Non Inverting  
HIGH  
LOW  
85314BGI-01  
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REV. F JULY 25, 2010  
3
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
CC  
Inputs, V  
-0.5V to VCC + 0.5V  
I
device. These ratings are stress specifications only. Functional  
operation of product at these conditions or any conditions be-  
yond those listed in the DC Characteristics or AC Character-  
istics is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect product reliability.  
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
Package Thermal Impedance, θ  
20 Lead TSSOP  
20 Lead SOIC  
JA  
73.2°C/W (0 lfpm)  
46.2°C/W (0 lfpm)  
Storage Temperature, T  
-65°C to 150°C  
STG  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
V
VCC  
IEE  
Power Supply Voltage  
Power Supply Current  
2.375  
3.3  
3.8  
80  
mA  
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
nCLK_EN, CLK_SEL  
CLK1  
2
V
CC + 0.3  
V
V
V
V
VIH  
VIL  
Input High Voltage  
2
VCC + 0.3  
0.8  
nCLK_EN, CLK_SEL  
CLK1  
-0.3  
-0.3  
Input Low Voltage  
1.3  
CLK1,  
CLK_SEL, nCLK_EN  
CLK1,  
CLK_SEL, nCLK_EN  
IIH  
IIL  
Input High Current  
Input Low Current  
VIN = VCC = 3.8V  
150  
µA  
µA  
VCC = 3.8V, VIN = 0V  
-5  
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C  
Symbol Parameter  
IIH Input High Current  
Test Conditions  
Minimum Typical Maximum Units  
nCLK0  
CLK0  
VCC = VIN = 3.8V  
5
µA  
µA  
µA  
µA  
V
VCC = VIN = 3.8V  
150  
nCLK0  
CLK0  
VCC = 3.8V, VIN = 0V  
VCC = 3.8V, VIN = 0V  
-150  
-5  
IIL  
Input Low Current  
VPP  
Peak-to-Peak Input Voltage  
0.15  
1.3  
Common Mode Input Voltage;  
NOTE 1, 2  
VCMR  
0.5  
VCC - 0.85  
V
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V.  
NOTE 2: Common mode voltage is defined as VIH.  
85314BGI-01  
www.idt.com  
REV. F JULY 25, 2010  
4
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum Typical  
VCC - 1.4  
Maximum Units  
VOH  
Output High Voltage; NOTE 1  
VCC - 0.9  
VCC - 1.7  
1.0  
V
V
V
VOL  
Output Low Voltage; NOTE 1  
VCC - 2.0  
VSWING  
Peak-to-Peak Output Voltage Swing  
0.6  
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.  
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
CLK0, nCLK0  
CLK1  
700  
300  
MHz  
MHz  
fMAX  
Output Frequency  
Integration Range:  
(12kHz - 20MHz)  
tjit (Ø)  
tpLH  
RMS Phase Jitter (Random); NOTE 5  
Propagation Delay, Low to High; NOTE 1  
0.05  
1.4  
ps  
1.0  
1.8  
30  
ns  
ps  
ps  
ps  
ps  
%
TSSOP Package  
SOIC Package  
Output Skew;  
NOTE 3, 6  
tsk(o)  
50  
tsk(pp)  
tR / tF  
Part-to-Part Skew; NOTE 4, 6  
Output Rise/Fall Time  
350  
700  
55  
20% to 80%  
ƒ≤ 700MHz  
ƒ≤ 250MHz  
200  
45  
CLK0, nCLK0  
CLK1  
odc  
Output Duty Cycle  
45  
55  
%
All parameters measured at fMAX unless noted otherwise.  
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point.  
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured  
at the differential cross points.  
NOTE 5: Please refer to the Phase Noise Plot.  
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.  
85314BGI-01  
www.idt.com  
REV. F JULY 25, 2010  
5
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
TYPICAL PHASE NOISE AT 155.52MHZ  
0
-10  
-20  
155.52MHz  
RMS Phase Jitter (Random)  
-30  
12kHz to 20MHz = 0.05ps (typical)  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
Raw Phase Noise Data  
-130  
-140  
-150  
-160  
-170  
-180  
-190  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
85314BGI-01  
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REV. F JULY 25, 2010  
6
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
PARAMETER MEASUREMENT INFORMATION  
2V  
VCC  
SCOPE  
VCC  
Qx  
nCLK0  
CLK0  
LVPECL  
VEE  
VPP  
VCMR  
Cross Points  
nQx  
-1.8V -0.375V  
VEE  
3.3V OUTPUT LOAD AC TEST CIRCUIT  
DIFFERENTIAL INPUT LEVEL  
PART 1  
nQx  
nQx  
Qx  
Qx  
PART 2  
nQy  
nQy  
Qy  
Qy  
tsk(o)  
tsk(o)  
OUTPUT SKEW  
PART-TO-PART SKEW  
Phase Noise Plot  
nQ0:nQ4  
Q0:Q4  
Phase Noise Mask  
tPW  
tPERIOD  
tPW  
tPERIOD  
Offset Frequency  
f1  
f2  
odc =  
x 100%  
RMS Jitter = Area Under the Masked Phase Noise Plot  
RMS PHASE JITTER  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
www.idt.com  
85314BGI-01  
REV. F JULY 25, 2010  
7
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
nCLK0  
CLK0  
CLK1  
nQ0:nQ4  
nQ0:nQ4  
Q0:Q4  
Q0:Q4  
tPD  
tPD  
PROPAGATION DELAY (DIFFERENTIAL INPUT)  
PROPAGATION DELAY (LVCMOS INPUT)  
80%  
tF  
80%  
VSWING  
20%  
Clock  
20%  
Outputs  
tR  
OUTPUT RISE/FALL TIME  
85314BGI-01  
www.idt.com  
REV. F JULY 25, 2010  
8
ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
APPLICATION INFORMATION  
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS  
Figure 2 shows how the differential input can be wired to accept  
single ended levels. The reference voltage V_REF = VCC/2 is  
generated by the bias resistors R1, R2 and C1. This bias circuit  
should be located as close as possible to the input pin. The ratio  
of R1 and R2 might need to be adjusted to position the V_REF in  
the center of the input voltage swing. For example, if the input  
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V  
and R2/R1 = 0.609.  
VCC  
R1  
1K  
Single Ended Clock Input  
V_REF  
CLK  
nCLK  
C1  
0.1u  
R2  
1K  
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT  
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS  
INPUTS:  
OUTPUTS:  
CLK INPUT:  
LVPECL OUTPUT  
For applications not requiring the use of a clock input, it can All unused LVPECL outputs can be left floating. We  
be left floating. Though not required, but for additional recommend that there is no trace attached. Both sides of the  
protection, a 1kΩ resistor can be tied from the CLK input to differential output pair should either be left floating or  
ground.  
terminated.  
CLK/nCLK INPUT:  
For applications not requiring the use of the differential input,  
both CLK and nCLK can be left floating. Though not required,  
but for additional protection, a 1kΩ resistor can be tied from  
CLK to ground.  
LVCMOS CONTROL PINS:  
All control pins have internal pull-ups or pull-downs; additional  
resistance is not required but can be added for additional  
protection. A 1kΩ resistor can be used.  
85314BGI-01  
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REV. F JULY 25, 2010  
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ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
DIFFERENTIAL CLOCK INPUT INTERFACE  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL are examples only. Please consult with the vendor of the driver  
and other differential signals. Both VSWING and VOH must meet the component to confirm the driver termination requirements. For  
VPP and VCMR input requirements. Figures 3A to 3E show example in Figure 3A, the input termination applies for LVHSTL  
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an LVHSTL driver from another  
common driver types. The input interfaces suggested here vendor, use their termination recommendation.  
3.3V  
3.3V  
3.3V  
1.8V  
Zo = 50 Ohm  
CLK  
Zo = 50 Ohm  
CLK  
Zo = 50 Ohm  
nCLK  
Zo = 50 Ohm  
HiPerClockS  
Input  
LVPECL  
nCLK  
HiPerClockS  
Input  
LVHSTL  
R1  
50  
R2  
50  
ICS  
HiPerClockS  
R1  
50  
R2  
50  
LVHSTL Driver  
R3  
50  
FIGURE 3A. CLK/NCLK INPUT DRIVEN BY  
LVHSTL DRIVER  
FIGURE 3B. CLK/NCLK INPUT DRIVEN BY  
3.3V LVPECL DRIVER  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50 Ohm  
3.3V  
R3  
125  
R4  
125  
LVDS_Driver  
Zo = 50 Ohm  
Zo = 50 Ohm  
CLK  
CLK  
R1  
100  
nCLK  
Receiv er  
nCLK  
HiPerClockS  
Input  
Zo = 50 Ohm  
LVPECL  
R1  
84  
R2  
84  
FIGURE 3C. CLK/NCLK INPUT DRIVEN BY  
3.3V LVPECL DRIVER  
FIGURE 3D. CLK/NCLK INPUT DRIVEN BY  
3.3V LVDS DRIVER  
3.3V  
3.3V  
3.3V  
R3  
125  
R4  
125  
C1  
LVPECL  
Zo = 50 Ohm  
Zo = 50 Ohm  
CLK  
C2  
nCLK  
HiPerClockS  
Input  
R5  
100 - 200  
R6  
100 - 200  
R1  
84  
R2  
84  
R5,R6 locate near the driver pin.  
FIGURE 3E. CLK/NCLK INPUT DRIVEN BY  
3.3V LVPECL DRIVER WITH AC COUPLE  
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REV. F JULY 25, 2010  
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ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
TERMINATION FOR 3.3V LVPECL OUTPUTS  
The clock layout topology shown below is a typical termina-  
tion for LVPECL outputs. The two different layouts mentioned  
are recommended only as guidelines.  
50Ω transmission lines. Matched impedance techniques should  
be used to maximize operating frequency and minimize signal  
distortion. Figures 4A and 4B show two different layouts which  
are recommended only as guidelines. Other suitable clock lay-  
outs may exist and it would be recommended that the board  
designers simulate to guarantee compatibility across all printed  
circuit and clock component process variations.  
FOUT and nFOUT are low impedance follower outputs that gen-  
erate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must  
be used for functionality. These outputs are designed to drive  
3.3V  
Zo = 50Ω  
125Ω  
125Ω  
FOUT  
FIN  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
FOUT  
FIN  
50Ω  
50Ω  
VCC - 2V  
1
RTT =  
Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
84Ω  
84Ω  
FIGURE 4A. LVPECL OUTPUT TERMINATION  
FIGURE 4B. LVPECL OUTPUT TERMINATION  
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REV. F JULY 25, 2010  
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ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
TERMINATION FOR 2.5V LVPECL OUTPUT  
Figure 5A and Figure 5B show examples of termination for close to ground level. The R3 in Figure 5B can be eliminated  
2.5V LVPECL driver. These terminations are equivalent to ter- and the termination is shown in Figure 5C.  
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very  
2.5V  
VCC=2.5V  
2.5V  
2.5V  
VCC=2.5V  
Zo = 50 Ohm  
Zo = 50 Ohm  
R1  
250  
R3  
250  
+
-
Zo = 50 Ohm  
Zo = 50 Ohm  
+
-
2,5V LVPECL  
Driv er  
R1  
50  
R2  
50  
2,5V LVPECL  
Driv er  
R2  
62.5  
R4  
62.5  
R3  
18  
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE  
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE  
2.5V  
VCC=2.5V  
Zo = 50 Ohm  
+
Zo = 50 Ohm  
-
2,5V LVPECL  
Driv er  
R1  
50  
R2  
50  
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE  
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REV. F JULY 25, 2010  
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ICS85314I-01  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
POWER CONSIDERATIONS  
This section provides information on power dissipation and junction temperature for the ICS85314I-01.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the ICS85314I-01 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.8V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW  
Power (outputs)MAX = 30.2mW/Loaded Output pair  
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW  
Total Power_MAX (3.465V, with all outputs switching) = 304mW + 151mW = 455mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the  
device. The maximum recommended junction temperature for the devices is 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a  
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.455W * 66.6°C/W = 115°C. This is well below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,  
and the type of board (single layer or multi-layer).  
TABLE 6A. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION  
θJA by Velocity (Linear Feet per Minute)  
0
200  
98.0°C/W  
66.6°C/W  
500  
88.0°C/W  
63.5°C/W  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
114.5°C/W  
73.2°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.  
TABLE 6B. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION  
θJA by Velocity (Linear Feet per Minute)  
0
200  
65.7°C/W  
39.7°C/W  
500  
57.5°C/W  
36.8°C/W  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
83.2°C/W  
46.2°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.  
85314BGI-01  
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DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
3. Calculations and Equations.  
LVPECL output driver circuit and termination are shown in Figure 6.  
VCC  
Q1  
VOUT  
RL  
50  
VCC - 2V  
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION  
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination  
voltage of V - 2V.  
CC  
•
•
For logic high, VOUT = V  
= V  
– 1.0V  
OH_MAX  
CC_MAX  
)
= 1.0V  
OH_MAX  
(V  
- V  
CC_MAX  
For logic low, VOUT = V  
= V  
– 1.7V  
OL_MAX  
CC_MAX  
)
= 1.7V  
OL_MAX  
(V  
- V  
CC_MAX  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
))  
Pd_H = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
- V  
/R ] * (V  
- V  
) =  
OH_MAX  
CC_MAX  
CC_MAX  
OH_MAX  
CC_MAX  
OH_MAX  
CC_MAX  
OH_MAX  
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW  
))  
Pd_L = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
/R ] * (V  
- V  
) =  
OL_MAX  
CC_MAX  
CC_MAX  
OL_MAX  
CC_MAX  
OL_MAX  
CC_MAX  
OL_MAX  
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW  
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RELIABILITY INFORMATION  
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP  
θ by Velocity (Linear Feet per Minute)  
JA  
0
200  
98.0°C/W  
66.6°C/W  
500  
88.0°C/W  
63.5°C/W  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
114.5°C/W  
73.2°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.  
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC  
θ by Velocity (Linear Feet per Minute)  
JA  
0
200  
65.7°C/W  
39.7°C/W  
500  
57.5°C/W  
36.8°C/W  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
83.2°C/W  
46.2°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.  
TRANSISTOR COUNT  
The transistor count for ICS85314I-01 is: 674  
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PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP  
TABLE 8A. PACKAGE DIMENSIONS  
Millimeters  
SYMBOL  
Minimum Maximum  
N
A
20  
--  
1.20  
0.15  
1.05  
0.30  
0.20  
6.60  
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
6.40  
c
D
E
6.40 BASIC  
0.65 BASIC  
E1  
e
4.30  
4.50  
L
0.45  
0°  
0.75  
8°  
α
aaa  
--  
0.10  
Reference Document: JEDEC Publication 95, MO-153  
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LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC  
TABLE 8B. PACKAGE DIMENSIONS  
Millimeters  
Minimum Maximum  
SYMBOL  
N
A
20  
--  
2.65  
--  
A1  
A2  
B
0.10  
2.05  
0.33  
0.18  
12.60  
7.40  
2.55  
0.51  
0.32  
13.00  
7.60  
C
D
E
e
1.27 BASIC  
H
h
10.00  
0.25  
0.40  
0°  
10.65  
0.75  
1.27  
8°  
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119  
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TABLE 9. ORDERING INFORMATION  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
tube  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
85314BGI-01  
85314BGI-01T  
85314BGI-01LF  
85314BGI-01LFT  
85314BMI-01  
ICS85314BI01  
ICS85314BI01  
20 lead TSSOP  
20 lead TSSOP  
2500 tape & reel  
tube  
ICS5314BI01L  
20 lead "Lead-Free" TSSOP  
20 lead "Lead-Free" TSSOP  
20 lead SOIC  
ICS5314BI01L  
2500 tape & reel  
tube  
ICS85314BI-01  
ICS85314BI-01  
ICS85314BMI-01LF  
ICS85314BMI-01LF  
85314BMI-01T  
85314BMI-01LF  
85314BMI-01LFT  
20 lead SOIC  
1000 tape & reel  
tube  
20 lead "Lead-Free" SOIC  
20 lead "Lead-Free" SOIC  
1000 tape & reel  
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement  
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial  
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves  
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
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REV. F JULY 25, 2010  
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LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER  
REVISION HISTORY SHEET  
Rev  
Table  
Page  
Description of Change  
Date  
7
8
9
Updated Figure 2, Single Ended Signal Diagram.  
Added "Termination for 2.5V LVPECL Outputs" section.  
Added "Differential Input Interface" section.  
A
3/31/03  
15  
1
2
Corrected Order Number and Marking from Rev. A to Rev. B.  
Added Phase Noise Bullet to Features section.  
Changed CIN from 4pF max. to 4pF typical.  
T2  
T5  
5
6
AC Characteristics Table - added RMS Phase Jitter.  
Added Phase Jitter Plot.  
B
8/11/04  
8
9
1
Updated Termination for 3.3V LVPECL Output diagrams.  
Updated Termination for 2.5V LVPECL Output section.  
Features section - added SOIC package output skew.  
4
5
7
Absolute Maximum Ratings - added SOIC Package Thermal Impedance.  
AC Characteristics table - added SOIC package for Output Skew.  
C
D
E
3/22/05  
5/24/05  
9/23/05  
T5  
Parameter Measurement Information - added Part-to-Part Skew and RMS  
Phase Jitter Diagrams.  
Features section - changed Part-to-Part Skew from 250ps max. to 350ps max.  
1
5
T5  
AC Characteristics table - changed Part-to-Part Skew from 250ps max. to  
350ps max.  
LVPECL DC Characteristics Table - changed VOH max from VCC - 1.0V to  
VCC - 0.9V.  
T4D  
5
9
Application Information Section - added Recommendations for Unused Input  
and Output Pins.  
T9  
T9  
18  
18  
Added TSSOP Lead-Free part number.  
E
F
Ordering Information Table - Added Lead Free marking  
Updated datasheet's header/footer with IDT from ICS.  
Removed ICS prefix from Part/Order Number column.  
Added Contact Page.  
8/1/07  
T9  
18  
20  
7/25/10  
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We’ve Got Your Timing Solution.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
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Tech Support  
netcom@idt.com  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.  
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of  
their respective owners.  
Printed in USA  
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