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PRELIMINARY  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS  
FANOUT BUFFER  
ICS854S013  
General Description  
Features  
The ICS854S013 is a low skew, high performance  
• Two differential LVDS output banks  
• Two differential clock input pairs  
S
IC  
Dual 1-to-3 Differential-to-LVDS Fanout Buffer and  
a member of the HiPerClockS™ family of High  
Performance Clock Solutions from IDT. The PCLKx,  
nPCLKx pairs can accept most standard differential  
HiPerClockS™  
• PCLKx, nPCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, CML, SSTL  
• Maximum output frequency: >3GHz  
input levels. The ICS854S013 is characterized to operate from a  
3.3V power supply. Guaranteed output and bank skew character-  
istics make the ICS854S013 ideal for those clock distribution  
applications demanding well defined performance and  
repeatability.  
• Translates any single ended input signal to LVDS levels with  
resistor bias on nPCLKx input  
• Output skew: <25ps (typical)  
• Bank skew: <50ps (typical)  
• Propagation delay: TBD  
• Additive phase jitter, RMS: 0.15ps (typical)  
• Full 3.3V power supply  
• 0°C to 70°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Block Diagram  
Pin Assignment  
QA0  
nQA0  
QA0  
1
2
20 QA1  
19  
nQA1  
nQA0  
Pulldown  
PCLKA  
QA1  
VDD  
PCLKA  
3
4
18 QA2  
17 nQA2  
Pullup  
nPCLKA  
nQA1  
QA2  
nPCLKA  
PCLKB  
nPCLKB  
5
6
7
16  
15  
14  
VDD  
QB2  
nQB2  
nQA2  
VDD  
nQB0  
QB0  
8
13 QB1  
QB0  
9
10  
12 nQB1  
nQB0  
11  
GND  
Pulldown  
Pullup  
PCLKB  
QB1  
nPCLKB  
nQB1  
ICS854S013  
20-Lead TSSOP  
QB2  
nQB2  
6.5mm x 4.4mm x 0.925mm package body  
G Package  
Top View  
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.  
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT™ / ICS™ LVDS FANOUT BUFFER  
1
ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Table 1. Pin Descriptions  
Number  
1, 2  
Name  
nQA0, QA0  
VDD  
Type  
Description  
Output  
Power  
Input  
Differential output pair. LVDS interface levels.  
Power supply pins.  
3, 8, 16  
4
PCLKA  
Pulldown  
Non-inverting differential clock input.  
5
nPCLKA  
PCLKB  
Input  
Pullup  
Pulldown  
Pullup  
Inverting differential clock input. VDD/2 default when left floating.  
Non-inverting differential clock input.  
6
Input  
7
nPCLKB  
nQB0, QB0  
GND  
Input  
Inverting differential clock input. VDD/2 default when left floating.  
Differential output pair. LVDS interface levels.  
Power supply ground.  
9, 10  
11  
Output  
Power  
Output  
Output  
Output  
12, 13  
14, 15  
17, 18  
nQB1, QB1  
nQB2, QB2  
nQA2, QA2  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
19, 20  
nQA1, QA1  
Output  
Differential output pair. LVDS interface levels.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
4
RPULLUP  
51  
51  
kΩ  
RPULLDOWN Input Pulldown Resistor  
kΩ  
Table 3. Clock Input Function Table  
Inputs  
Outputs  
PCLKA, PCLKB nPCLKA, nPCLKB QA[0:2], QB[0:2] nQA[0:2], nQB[0:2]  
Input to Output Mode  
Differential to Differential  
Differential to Differential  
Single-ended to Differential  
Single-ended to Differential  
Single-ended to Differential  
Single-ended to Differential  
Polarity  
0
1
LOW  
HIGH  
LOW  
HIGH  
HIGH  
LOW  
HIGH  
LOW  
HIGH  
LOW  
LOW  
HIGH  
Non-Inverting  
Non-Inverting  
Non-Inverting  
Non-Inverting  
Inverting  
1
0
0
Biased; NOTE 1  
1
Biased; NOTE 1  
Biased; NOTE 1  
Biased; NOTE 1  
0
1
Inverting  
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuos Current  
Surge Current  
10mA  
15mA  
Package Thermal Impedance, θJA  
87.2°C/W (0 mps)  
Storage Temperature, TSTG  
-65°C to 150°C  
DC Electrical Characteristics  
Table 4A. LVDS Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C  
Symbol Parameter  
VDD Positive Supply Voltage  
IDD Power Supply Current  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
Units  
V
3.135  
3.465  
135  
mA  
Table 4B. LVPECL Differential DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
µA  
PCLKA, PCLKB  
V
DD = VIN = 3.465V  
DD = VIN = 3.465V  
150  
5
IIH Input High Current  
nPCLKA, nPCLKB  
V
µA  
VDD = 3.465V,  
VIN = 0V  
PCLKA, PCLKB  
-5  
µA  
µA  
IIL  
Input Low Current  
VDD = 3.465V,  
nPCLKA, nPCLKB  
-150  
VIN = 0V  
VPP  
Peak-to-Peak Voltage; NOTE 1  
0.15  
1.3  
V
V
VCMR  
Common Mode Input Voltage; NOTE 1, 2  
GND + 0.5  
VDD – 0.85  
NOTE 1: VIL should not be less than -0.3V.  
NOTE 2: Common mode input voltage is defined as VIH.  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Table 4C. LVDS DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
360  
Maximum  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
∆VOD  
VOS  
50  
1.35  
50  
∆VOS  
VOS Magnitude Change  
mV  
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C  
Parameter Symbol Test Conditions  
fMAX Output Frequency  
tPD  
Minimum  
Typical  
Maximum Units  
>3  
GHz  
ps  
Propagation Delay; NOTE 1  
Output Skew; NOTE 2, 4  
Bank Skew; NOTE 3, 4  
TBD  
<25  
<50  
tsk(o)  
tsk(b)  
ps  
ps  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter Section  
100MHz, Integration Range:  
12kHz – 20MHz  
tjit  
0.15  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
200  
50  
ps  
%
All parameters measured at 500MHz unless noted otherwise.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured from the output differential cross points.  
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the  
to the power in the fundamental. When the required offset is  
specified, the phase noise is called a dBc value, which simply  
means dBm at a specified offset from the fundamental. By  
investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the  
entire time record of the signal. It is mathematically possible to  
calculate an expected bit error rate given a phase noise plot.  
fundamental compared to the power of the fundamental is called  
the dBc Phase Noise. This value is normally expressed using a  
Phase noise plot and is most often the specified plot in many  
applications. Phase noise is defined as the ratio of the noise power  
present in a 1Hz band at a specified offset from the fundamental  
frequency to the power value of the fundamental. This ratio is  
expressed in decibels (dBm) or a ratio of the power in the 1Hz band  
0
Additive Phase Jitter @ 100MHz  
12kHz to 20MHz = 0.15ps (typical)  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
-150  
-160  
-170  
-180  
-190  
1k  
10k  
100k  
1M  
10M  
100M  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements  
has issues relating to the limitations of the equipment. Often the  
noise floor of the equipment is higher than the noise floor of the  
device. This is illustrated above. The device meets the noise floor  
of what is shown, but can actually be lower. The phase noise is  
dependent on the input source and measurement equipment.  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Parameter Measurement Information  
V
DD  
SCOPE  
nPCLKA,  
nPCLKB  
Qx  
V
DD  
3.3V 5%  
POWER SUPPLY  
VPP  
VCMR  
Cross Points  
+
Float GND –  
LVDS  
PCLKA,  
PCLKB  
nQx  
GND  
3.3V LVDS Output Load AC Test Circuit  
Differential Input Level  
nQx  
Qx  
nQXx  
QXx  
nQXx  
nQy  
QXx  
Qy  
tsk(o)  
tsk(b)  
Where X = A or B  
Bank Skew  
Output Skew  
nQAx, nQBx  
QAx, QBx  
nPCLKA,  
nPCLKB  
PCLKA,  
PCLKB  
tPW  
tPERIOD  
nQAx,  
nQBx  
tPW  
tPERIOD  
odc =  
x 100%  
QAx, QBx  
tPD  
Output Duty Cycle/Pulse Width/Period  
Propagation Delay  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Parameter Measurement Information, continued  
VDD  
out  
out  
80%  
tF  
80%  
tR  
VOD  
➤
DC Input  
LVDS  
Clock  
Outputs  
20%  
20%  
VOS/∆ VOS  
➤
Output Rise/Fall Time  
Offset Voltage Setup  
VDD  
➤
out  
out  
LVDS  
DC Input  
100  
V
OD/∆ VOD  
➤
Differential Output Voltage Setup  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Application Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
PCLK/nPCLK Inputs  
LVDS Outputs  
For applications not requiring the use of a differential input, both  
the PCLK and nPCLK pins can be left floating. Though not  
required, but for additional protection, a 1kΩ resistor can be tied  
from PCLK to ground.  
All unused LVDS output pairs can be either left floating or  
terminated with 100Ω across. If they are left floating, there should  
be no trace attached.  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how the differential input can be wired to accept  
single-ended levels. The reference voltage V_REF = VDD/2 is  
generated by the bias resistors R1, R2 and C1. This bias circuit  
should be located as close as possible to the input pin. The ratio of  
R1 and R2 might need to be adjusted to position the V_REF in the  
center of the input voltage swing. For example, if the input clock  
VDD  
R1  
1K  
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and  
R2/R1 = 0.609.  
CLK_IN  
PCLKx  
V_REF  
nPCLKx  
C1  
0.1uF  
R2  
1K  
Figure 1. Single-Ended Signal Driving Differential Input  
IDT™ / ICS™ LVDS FANOUT BUFFER  
8
ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other  
differential signals. Both signals must meet the VPP and VCMR input  
requirements. Figures 2A to 2F show interface examples for the  
HiPerClockS PCLK/nPCLK input driven by the most common  
driver types. The input interfaces suggested here are examples  
only. If the driver is from another vendor, use their termination  
recommendation. Please consult with the vendor of the driver  
component to confirm the driver termination requirements.  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50Ω  
3.3V  
R1  
50  
R2  
50  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
R1  
100  
PCLK  
nPCLK  
Zo = 50Ω  
HiPerClockS  
nPCLK  
CML Built-In Pullup  
PCLK/nPCLK  
HiPerClockS  
PCLK/nPCLK  
CML  
Figure 2A. HiPerClockS PCLK/nPCLK Input  
Figure 2B. HiPerClockS PCLK/nPCLK Input  
Driven by a Built-In Pullup CML Driver  
Driven by an Open Collector CML Driver  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
R3  
125  
R4  
125  
3.3V  
R3  
84  
R4  
84  
Zo = 50Ω  
Zo = 50Ω  
C1  
C2  
Zo = 50Ω  
Zo = 50Ω  
3.3V LVPECL  
PCLK  
PCLK  
nPCLK  
nPCLK  
HiPerClockS  
PCLK/nPCLK  
HiPerClockS  
Input  
LVPECL  
R5  
100 - 200  
R6  
100 - 200  
R1  
125  
R2  
125  
R1  
84  
R2  
84  
Figure 2C. HiPerClockS PCLK/nPCLK Input  
Driven by a 3.3V LVPECL Driver  
Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by  
a 3.3V LVPECL Driver with AC Couple  
2.5V  
3.3V  
3.3V  
3.3V  
2.5V  
3.3V  
R3  
120  
R4  
120  
R3  
1k  
R4  
1k  
Zo = 50Ω  
Zo = 50Ω  
Zo = 60Ω  
Zo = 60Ω  
C1  
C2  
PCLK  
PCLK  
R5  
100  
nPCLK  
nPCLK  
HiPerClockS  
PCLK/nPCLK  
HiPerClockS  
PCLK/nPCLK  
LVDS  
SSTL  
R1  
1k  
R2  
1k  
R1  
120  
R2  
120  
Figure 2E. HiPerClockS PCLK/nPCLK Input  
Driven by an SSTL Driver  
Figure 2F. HiPerClockS PCLK/nPCLK Input  
Driven by a 3.3V LVDS Driver  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
3.3V LVDS Driver Termination  
A general LVDS interface is shown in Figure 3. In a 100Ω  
differential transmission line environment, LVDS drivers require a  
matched load termination of 100Ω across near the receiver input.  
For a multiple LVDS outputs buffer, if only partial outputs are used,  
it is recommended to terminate the unused outputs.  
3.3V  
50Ω  
3.3V  
LVDS Driver  
+
–
R1  
100Ω  
50Ω  
100Ω Differential Transmission Line  
Figure 3. Typical LVDS Driver Termination  
IDT™ / ICS™ LVDS FANOUT BUFFER  
10  
ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Power Considerations  
This section provides information on power dissipation and junction temperature for the ICS854S013.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the ICS854S013 is the sum of the core power plus the power dissipated in the load(s). The following is the  
power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 135mA = 467.77mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.  
The maximum recommended junction temperature for HiPerClockS devices is 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow  
and a multi-layer board, the appropriate value is 87.2°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:  
70°C + 0.468W * 87.2°C/W = 110.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type  
of board (single layer or multi-layer).  
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection  
θJA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
87.2°C/W  
82.9°C/W  
80.7°C/W  
IDT™ / ICS™ LVDS FANOUT BUFFER  
11  
ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Reliability Information  
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP  
θJA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
87.2°C/W  
82.9°C/W  
80.7°C/W  
Transistor Count  
The transistor count for ICS854S013 is: 363  
Package Outline and Package Dimensions  
Package Outline - G Suffix for 20 Lead TSSOP  
Table 8 Package Dimensions  
All Dimensions in Millimeters  
Symbol  
Minimum  
Maximum  
N
A
20  
1.20  
0.15  
1.05  
0.30  
0.20  
6.60  
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
6.40  
c
D
E
6.40 Basic  
E1  
e
4.30  
4.50  
0.65 Basic  
L
0.45  
0°  
0.75  
8°  
α
aaa  
0.10  
Reference Document: JEDEC Publication 95, MO-153  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
ICS854S013BG  
ICS854S013BGT  
ICS854S013BGLF  
ICS854S013BGLFT  
Marking  
Package  
20 Lead TSSOP  
20 Lead TSSOP  
Shipping Packaging  
Tube  
2500 Tape & Reel  
Tube  
Temperature  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
ICS854S013BG  
ICS854S013BG  
ICS54S013BL  
ICS54S013BL  
“Lead-Free” 20 Lead TSSOP  
“Lead-Free” 20 Lead TSSOP  
2500 Tape & Reel  
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for  
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use  
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements  
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any  
IDT product for use in life support devices or critical medical instruments.  
IDT™ / ICS™ LVDS FANOUT BUFFER  
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ICS854S013BG REV. A FEBRUARY 26, 2008  
ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
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San Jose, CA 95138  
United States  
IDT (S) Pte. Ltd.  
Sanbancho Tokyu, Bld. 7F,  
8-1 Sanbancho  
Chiyoda-ku, Tokyo 102-0075 KT22 7TU  
321 Kingston Road  
Leatherhead, Surrey  
1 Kallang Sector, #07-01/06  
Kolam Ayer Industrial Park  
Singapore 349276  
800 345 7015  
+81 3 3221 9822  
England  
+408 284 8200 (outside U.S.)  
+65 67443356  
Fax: +65 67441764  
Fax: +81 3 3221 9824  
+44 (0) 1372 363 339  
Fax: +44 (0) 1372 37885  
idteurope@idt.com  
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