LPC810M021FN8FP--Datasheet/数据表在线中文翻译

LPC81xM

32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and

4 kB SRAM

Rev. 4.3 — 22 April 2014

Product data sheet

1. General description

The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory

and 4 kB of SRAM.

The peripheral complement of the LPC81xM includes a CRC engine, one I²C-bus

interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up

timer, and state-configurable timer, one comparator, function-configurable I/O ports

through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O

pins.

2. Features and benefits

 System:

 ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with

single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 Serial Wire Debug (SWD) and JTAG boundary scan modes supported.

 Micro Trace Buffer (MTB) supported.

 Memory:

 Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.

 Up to 4 kB SRAM.

 ROM API support:

 Boot loader.

 USART drivers.

 I2C drivers.

 Power profiles.

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

 Digital peripherals:

 High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and glitch filter.

 High-current source output driver (20 mA) on four pins.

 High-current sink driver (20 mA) on two true open-drain pins.

 GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.

 Switch matrix for flexible configuration of each I/O pin function.

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

 State Configurable Timer/PWM (SCTimer/PWM) with input and output functions

(including capture and match) assigned to pins through the switch matrix.

 Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

 Self Wake-up Timer (WKT) clocked from either the IRC or a low-power,

low-frequency internal oscillator.

 CRC engine.

 Windowed Watchdog timer (WWDT).

 Analog peripherals:

 Comparator with internal and external voltage references with pin functions

assigned or enabled through the switch matrix.

 Serial interfaces:

 Three USART interfaces with pin functions assigned through the switch matrix.

 Two SPI controllers with pin functions assigned through the switch matrix.

 One I²C-bus interface with pin functions assigned through the switch matrix.

 Clock generation:

 12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be

used as a system clock.

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

 10 kHz low-power oscillator for the WKT.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock

input CLKIN, or the internal RC oscillator.

 Clock output function with divider that can reflect the crystal oscillator, the main

clock, the IRC, or the watchdog oscillator.

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption.

 Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

 Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and

I2C peripherals.

 Timer-controlled self wake-up from Deep power-down mode.

 Power-On Reset (POR).

 Brownout detect.

 Unique device serial number for identification.

 Single power supply.

 Operating temperature range 40 °C to 105 °C except for the DIP8 package, which is

available for a temperature range of 40 °C to 85 °C.

 Available as DIP8, TSSOP16, SO20, TSSOP20, and XSON16 package.

3. Applications

 8/16-bit applications

 Lighting

 Consumer

 Motor control

 Climate control

 Fire and security applications

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

2 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC810M021FN8

DIP8

plastic dual in-line package; 8 leads (300 mil)

SOT097-2

SOT403-1

SOT163-1

SOT360-1

SOT1341-1

LPC811M001JDH16 TSSOP16

LPC812M101JDH16 TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

plastic small outline package; 20 leads; body width 7.5 mm

plastic thin shrink small outline package; 20 leads; body width 4.4 mm

LPC812M101JD20

LPC812M101JDH20 TSSOP20

LPC812M101JTB16 XSON16

SO20

plastic extremely thin small outline package; no leads; 16 terminals;

body 2.5  3.2  0.5 mm

4.1 Ordering options

Table 2.

Ordering options

Type number

Flash/kB SRAM/kB USART

I²C-bus SPI Comparator

GPIO

6

Package

LPC810M021FN8

LPC811M001JDH16

LPC812M101JDH16

LPC812M101JD20

LPC812M101JDH20

LPC812M101JTB16

4

1

2

4

2

3

2

3

1

2

1

2

1

DIP8

8

14

TSSOP16

SO20

16

14

18

TSSOP20

XSON16

14

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

3 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

5. Marking

The LPC81xM devices typically have the following top-side marking:

LPC81x

xxxxx

xxxxxxxx

xxYWWxR[x]

The last two letters in the last line (field ‘xR’) identify the boot code version and device

revision.

Table 3.

Device revision table

Revision identifier (xR)

Revision description

‘1A’

‘2A’

’4C’

Initial device revision with boot code version 13.1

Device revision with boot code version 13.2

Device revision with boot code version 13.4

Field ‘Y’ states the year the device was manufactured. Field ‘WW’ states the week the

device was manufactured during that year.

Remark: On the TSSOP16 package, the last line includes only the date code xxYWW.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

4 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

6. Block diagram

/3&ꢃꢄ[0

6:&/.ꢈꢄ6:'

7(67ꢁ'(%8*

,17(5)$&(

ꢀꢅꢄ[ꢄ

3,2ꢉ

+,*+ꢇ63(('

*3,2

$50

&257(;ꢀ0ꢁꢂ

)/$6+

ꢃꢁꢅꢁꢀꢆꢄN%

65$0

ꢀꢁꢂꢁꢃꢄN%

520

3,1ꢄ,17(558376ꢁ

3$77(51ꢄ0$7&+

VODYH

&7287B>ꢊꢋꢉ@

&7,1B>ꢊꢋꢉ@

6&7,0(5ꢁ

3:0

$+%ꢇ/,7(ꢄꢄ%86

VODYH

&5&

VODYH

$+%ꢄ72ꢄ$3%

%5,'*(ꢄ

7;'ꢈꢄ576

5;'ꢈꢄ&76

6&/.

::'7

,2&21

08/7,ꢇ5$7(ꢄ7,0(5

86$57ꢉ

86$57ꢀ

86$57ꢂ

7;'ꢈꢄ576

5;'ꢈꢄ&76

6&/.

ꢀꢅꢄ[ꢄ

6:,7&+

0$75,;

7;'ꢈꢄ576

5;'ꢈꢄ&76

6&/.

6&.ꢈꢄ66(/

0,62ꢈꢄ026,

308

63,ꢉ

63,ꢀ

6&.ꢈꢄ66(/

0,62ꢈꢄ026,

6(/)

:$.(ꢇ83ꢄ7,0(5

$/:$<6ꢇ21ꢄ32:(5ꢄ'20$,1

6&/

6'$

ꢂ

, &ꢇ%86

;7$/287

;7$/,1

;7$/

,5&

6<6&21

&/2&.

5(6(7ꢈꢄ&/.,1

&/.287

*(1(5$7,21ꢈ

32:(5ꢄ&21752/ꢈ

6<67(0ꢄ

:'2VF

%2'

)81&7,216

325

$&03B,ꢀꢁꢂ

9''&03

$&03B2

&203$5$725

FORFNVꢄDQGꢄ

FRQWUROV

DDDꢀꢁꢁꢂꢃꢄꢅ

Fig 1. LPC81xM block diagram

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

5 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

7. Pinning information

7.1 Pinning

ꢀ

ꢂ

ꢊ

ꢃ

ꢅ

ꢍ

ꢆ

ꢌ

5(6(7ꢁ3,2ꢉBꢌ

3,2ꢉBꢉꢁ$&03B,ꢀꢁ7'2

3,2ꢉBꢃꢁ:$.(83ꢁ7567

6:&/.ꢁ3,2ꢉBꢊꢁ7&.

6:',2ꢁ3,2ꢉBꢂꢁ706

9

66

9

''

',3ꢃ

3,2ꢉBꢀꢁ$&03B,ꢂꢁ&/.,1ꢁ7',

DDDꢀꢁꢁꢂꢃꢄꢃ

Fig 2. Pin configuration DIP8 package (LPC810M021JN8)

ꢀ

ꢂ

ꢊ

ꢃ

ꢌ

ꢆ

ꢍ

ꢅ

ꢀꢆ

ꢀꢌ

ꢀꢃ

ꢀꢊ

ꢀꢂ

ꢀꢀ

ꢀꢉ

ꢎ

3,2ꢉBꢀꢊ

3,2ꢉBꢀꢂ

3,2ꢉBꢉꢁ$&03B,ꢀꢁ7'2

3,2ꢉBꢆꢁ9''&03

3,2ꢉBꢍ

5(6(7ꢁ3,2ꢉBꢌ

3,2ꢉBꢃꢁ:$.(83ꢁ7567

6:&/.ꢁ3,2ꢉBꢊꢁ7&.

6:',2ꢁ3,2ꢉBꢂꢁ706

3,2ꢉBꢀꢀ

9

66

9

''

76623ꢄꢅ

3,2ꢉBꢅꢁ;7$/,1

3,2ꢉBꢎꢁ;7$/287

3,2ꢉBꢀꢉ

3,2ꢉBꢀꢁ$&03B,ꢂꢁ&/.,1ꢁ7',

DDDꢀꢁꢁꢆꢃꢁꢃ

Fig 3. Pin configuration TSSOP16 package (LPC811M001JDH16 and LPC812M101JDH16)

ꢀ

ꢂ

ꢂꢉ

ꢀꢎ

ꢀꢅ

ꢀꢍ

ꢀꢆ

ꢀꢌ

ꢀꢃ

ꢀꢊ

ꢀꢂ

ꢀꢀ

3,2ꢉBꢀꢍ

3,2ꢉBꢀꢊ

3,2ꢉBꢀꢃ

3,2ꢉBꢉꢁ$&03B,ꢀꢁ7'2

3,2ꢉBꢆꢁ9''&03

3,2ꢉBꢍ

ꢊ

3,2ꢉBꢀꢂ

ꢃ

5(6(7ꢁ3,2ꢉBꢌ

3,2ꢉBꢃꢁ:$.(83ꢁ7567

6:&/.ꢁ3,2ꢉBꢊꢁ7&.

6:',2ꢁ3,2ꢉBꢂꢁ706

3,2ꢉBꢀꢀ

ꢌ

9

66

9

''

62ꢆꢁ

ꢆ

ꢍ

3,2ꢉBꢅꢁ;7$/,1

ꢅ

3,2ꢉBꢎꢁ;7$/287

3,2ꢉBꢀꢁ$&03Bꢂꢁ&/.,1ꢁ7',

3,2ꢉBꢀꢌ

ꢎ

3,2ꢉBꢀꢉ

ꢀꢉ

3,2ꢉBꢀꢆ

DDDꢀꢁꢁꢆꢃꢂꢅ

Fig 4. Pin configuration SO20 package (LPC812M101JD20)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

6 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

ꢀ

ꢂ

ꢂꢉ

ꢀꢎ

ꢀꢅ

ꢀꢍ

ꢀꢆ

ꢀꢌ

ꢀꢃ

ꢀꢊ

ꢀꢂ

ꢀꢀ

3,2ꢉBꢀꢍ

3,2ꢉBꢀꢊ

3,2ꢉBꢀꢃ

3,2ꢉBꢉꢁ$&03B,ꢀꢁ7'2

3,2ꢉBꢆꢁ9''&03

3,2ꢉBꢍ

ꢊ

3,2ꢉBꢀꢂ

ꢃ

5(6(7ꢁ3,2ꢉBꢌ

ꢌ

3,2ꢉBꢃꢁ:$.(83ꢁ7567

6:&/.ꢁ3,2ꢉBꢊꢁ7&.

6:',2ꢁ3,2ꢉBꢂꢁ706

3,2ꢉBꢀꢀ

9

66

''

76623ꢆꢁ

ꢆ

ꢍ

3,2ꢉBꢅꢁ;7$/,1

ꢅ

3,2ꢉBꢎꢁ;7$/287

3,2ꢉBꢀꢁ$&03B,ꢂꢁ&/.,1ꢁ7',

3,2ꢉBꢀꢌ

ꢎ

3,2ꢉBꢀꢉ

ꢀꢉ

3,2ꢉBꢀꢆ

DDDꢀꢁꢁꢆꢃꢃꢂ

Fig 5.

Pin configuration TSSOP20 package (LPC812M101JDH20)

terminal 1

XSON16

index area

PIO0_13

PIO0_12

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

PIO0_0/ACMP_I1/TDO

PIO0_6/VDDCMP

PIO0_7

RESET/PIO0_5

PIO0_4/WAKEUP/TRST

SWCLK/PIO0_3/TCK

SWDIO/PIO0_2/TMS

PIO0_11

V

SS

V

DD

PIO0_8/XTALIN

PIO0_9/XTALOUT

PIO0_10

9

PIO0_1/ACMP_I2/CLKIN/TDI

aaa-009570

Transparent top view

Fig 6.

Pin configuration XSON16 package (LPC812M101JTB16)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

7 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

7.2 Pin description

The pin description consists of two parts showing pin functions that are fixed to a certain

package pin (see Table 4) and showing pin functions that can be assigned to any pin on

the package through the switch matrix (see Table 5).

The pin description table in Table 4 shows the pin functions that are fixed to specific pins

on each package. These fixed-pin functions are selectable between GPIO and the

comparator inputs, SWD, RESET, and the XTAL pins. By default, the GPIO function is

selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in

boundary scan mode only.

Table 5 shows the the I2C, USART, SPI, and SCT pin functions, which can be assigned

through the switch matrix to any pin that is not power or ground in place of the pin’s fixed

functions.

The following exceptions apply:

For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and

PIO0_10.

Do not assign more than one output to any pin. However, more than one input can be

assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is

disabled.

Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up

from Deep power-down mode via an external pin, do not assign any movable function to

this pin.

The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to

PIO0_4 by hardware when the part is in boundary scan mode.

Table 4.

Symbol

Pin description table (fixed pins)

Type Reset Description

state

[1]

[5]

PIO0_0/ACMP_I1/

TDO

19

12

16 16

8

5

I/O

I; PU PIO0_0 — General purpose digital input/output port 0 pin 0.

In ISP mode, this is the USART0 receive pin U0_RXD.

In boundary scan mode: TDO (Test Data Out).

AI

-

ACMP_I1 — Analog comparator input 1.

PIO0_1/ACMP_I2/

CLKIN/TDI

9

I/O

I; PU PIO0_1 — General purpose digital input/output pin.

In boundary scan mode: TDI (Test Data In).

ISP entry pin on chip versions 1A and 2A and on the DIP8

package (see Table 6). For these chip versions and

packages, a LOW level on this pin during reset starts the

ISP command handler.

See PIO0_12 for all other packages.

AI

I

-

ACMP_I2 — Analog comparator input 2.

CLKIN — External clock input.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

8 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 4.

Symbol

Pin description table (fixed pins)

Type Reset Description

state

[1]

[2]

[6]

SWDIO/PIO0_2/TMS 7

6

5

4

6

5

4

3

2

I/O

I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by

default on this pin.

In boundary scan mode: TMS (Test Mode Select).

I/O

-

PIO0_2 — General purpose digital input/output pin.

SWCLK/PIO0_3/

TCK

6

5

I; PU SWCLK — Serial Wire Clock. SWCLK is enabled by default

on this pin.

In boundary scan mode: TCK (Test Clock).

I/O

-

PIO0_3 — General purpose digital input/output pin.

PIO0_4/WAKEUP/

TRST

I; PU PIO0_4 — General purpose digital input/output pin.

In ISP mode, this is the USART0 transmit pin U0_TXD.

In boundary scan mode: TRST (Test Reset).

This pin triggers a wake-up from Deep power-down mode. If

you need to wake up from Deep power-down mode via an

external pin, do not assign any movable function to this pin.

This pin should be pulled HIGH externally before entering

Deep power-down mode. A LOW-going pulse as short as 50

ns causes the chip to exit Deep power-down mode and

wakes up the part.

[4]

RESET/PIO0_5

4

3

1

I/O

I; PU RESET — External reset input: A LOW-going pulse as short

as 50 ns on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor

execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH

externally. The RESET pin can be left unconnected or be

used as a GPIO or for any movable function if an external

RESET function is not needed and the Deep power-down

mode is not used.

I

-

PIO0_5 — General purpose digital input/output pin.

[9]

PIO0_6/VDDCMP

18

15 15

-

I/O

AI

I; PU PIO0_6 — General purpose digital input/output pin.

-

VDDCMP — Alternate reference voltage for the analog

comparator.

[2]

[8]

PIO0_7

17

14

14 14

11 11

-

I/O

I

I; PU PIO0_7 — General purpose digital input/output pin.

I; PU PIO0_8 — General purpose digital input/output pin.

PIO0_8/XTALIN

-

XTALIN — Input to the oscillator circuit and internal clock

generator circuits. Input voltage must not exceed 1.95 V.

[8]

[3]

PIO0_9/XTALOUT

PIO0_10

13

9

10 10

-

I/O

O

I

I; PU PIO0_9 — General purpose digital input/output pin.

-

XTALOUT — Output from the oscillator circuit.

8

7

8

7

IA

PIO0_10 — General purpose digital input/output pin. Assign

I2C functions to this pin when true open-drain pins are

needed for a signal compliant with the full I2C specification.

[3]

PIO0_11

8

-

I

IA

PIO0_11 — General purpose digital input/output pin. Assign

I2C functions to this pin when true open-drain pins are

needed for a signal compliant with the full I2C specification.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

9 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 4.

Symbol

Pin description table (fixed pins)

Type Reset Description

state

[1]

[2]

PIO0_12

3

2

-

I/O

I; PU PIO0_12 — General purpose digital input/output pin. ISP

entry pin on the SO20/TSSOP20/TSSOP16/XSON16

packages starting with chip version 4C (see Table 6). A

LOW level on this pin during reset starts the ISP command

handler.

See pin PIO0_1 for the DIP8 package and chip versions 1A

and 2A.

[2]

[7]

PIO0_13

PIO0_14

PIO0_15

PIO0_16

PIO0_17

V_DD

2

1

-

1

-

I/O

-

I; PU PIO0_13 — General purpose digital input/output pin.

I; PU PIO0_14 — General purpose digital input/output pin.

I; PU PIO0_15 — General purpose digital input/output pin.

I; PU PIO0_16 — General purpose digital input/output pin.

I; PU PIO0_17 — General purpose digital input/output pin.

20

11

10

1

-

15

16

12 12

13 13

6

7

-

3.3 V supply voltage.

Ground.

V_SS

-

[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V_DD

level); IA = inactive, no pull-up/down enabled.

[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[3] True open-drain pin. I²C-bus pins compliant with the I²C-bus specification for I²C standard mode, I²C Fast-mode, and I²C Fast-mode

Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output

functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all

functions on this pin.

Remark: If this pin is not available on the package, prevent it from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0

register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally.

[4] See Figure 11 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode.

[5] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep

power-down mode, pulling this pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other

purposes, if the WKT low power oscillator is enabled for waking up the part from Deep power-down mode.

[7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system

oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[9] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with

configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is

disabled.

Table 5.

Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name

U0_TXD

Type

Description

O

I

Transmitter output for USART0.

Receiver input for USART0.

Request To Send output for USART0.

Clear To Send input for USART0.

U0_RXD

U0_RTS

O

I

U0_CTS

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

10 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 5.

Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name

U0_SCLK

U1_TXD

Type

I/O

O

Description

Serial clock input/output for USART0 in synchronous mode.

Transmitter output for USART1.

Receiver input for USART1.

Request To Send output for USART1.

Clear To Send input for USART1.

Serial clock input/output for USART1 in synchronous mode.

Transmitter output for USART2.

Receiver input for USART2.

Request To Send output for USART2.

Clear To Send input for USART2.

Serial clock input/output for USART2 in synchronous mode.

Serial clock for SPI0.

U1_RXD

I

U1_RTS

O

U1_CTS

I

U1_SCLK

U2_TXD

I/O

O

U2_RXD

I

U2_RTS

O

U2_CTS

I

U2_SCLK

SPI0_SCK

SPI0_MOSI

SPI0_MISO

SPI0_SSEL

SPI1_SCK

SPI1_MOSI

SPI1_MISO

SPI1_SSEL

CTIN_0

I/O

I

Master Out Slave In for SPI0.

Master In Slave Out for SPI0.

Slave select for SPI0.

Serial clock for SPI1.

Master Out Slave In for SPI1.

Master In Slave Out for SPI1.

Slave select for SPI1.

SCT input 0.

CTIN_1

I

SCT input 1.

CTIN_2

I

SCT input 2.

CTIN_3

I

SCT input 3.

CTOUT_0

CTOUT_1

CTOUT_2

CTOUT_3

I2C0_SCL

O

SCT output 0.

O

SCT output 1.

O

SCT output 2.

O

SCT output 3.

I/O

I²C-bus clock input/output (open-drain if assigned to pin PIO0_10).

High-current sink only if assigned to PIO0_10 and if I²C Fast-mode

Plus is selected in the I/O configuration register.

I2C0_SDA

I/O

I²C-bus data input/output (open-drain if assigned to pin PIO0_11).

High-current sink only if assigned to pin PIO0_11 and if I²C

Fast-mode Plus is selected in the I/O configuration register.

ACMP_O

CLKOUT

O

Analog comparator digital output.

Clock output.

GPIO_INT_BMAT O

Output of the pattern match engine.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

11 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 6.

Pin location in ISP mode

ISP entry pin USART RXD USART TXD

Marking

Boot loader Package

version

PIO0_1

PIO0_0

PIO0_4

1A

v 13.1

TSSOP20; SO20;

TSSOP16; DIP8;

XSON16

2A

v 13.2

TSSOP20; SO20;

TSSOP16; DIP8;

XSON16

PIO0_1

PIO0_0

PIO0_4

4C and

later

v 13.4 and

later

DIP8

PIO0_12

4C and

later

v 13.4 and

later

TSSOP20; SO20;

TSSOP16;

XSON16

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

12 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8. Functional description

8.1 ARM Cortex-M0+ core

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a

two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four

breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O

enabled port for fast GPIO access.

The core includes a single-cycle multiplier and a system tick timer.

8.2 On-chip flash program memory

The LPC81xM contain up to 16 kB of on-chip flash program memory. The flash memory

supports a 64 Byte page size with page write and erase.

8.3 On-chip SRAM

The LPC81xM contain a total of up to 4 kB on-chip static RAM data memory.

8.4 On-chip ROM

The 8 kB on-chip ROM contains the boot loader and the following Application

Programming Interfaces (API):

• In-System Programming (ISP) and In-Application Programming (IAP) support for flash

programming

• Power profiles for configuring power consumption and PLL settings

• USART driver API routines

• I²C-bus driver API routines

8.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

8.5.1 Features

• Controls system exceptions and peripheral interrupts.

• On the LPC81xM, the NVIC supports 32 vectored interrupts including up to 8 external

interrupt inputs selectable from all GPIO pins.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation using the ARM exceptions SVCall and PendSV.

• Relocatable interrupt vector table using vector table offset register.

8.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

13 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Up to eight pins, regardless of the selected function, can be programmed to generate an

interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be

selected from all digital or mixed digital/analog pins. The pin interrupt/pattern match block

controls the edge or level detection mechanism.

8.6 System tick timer

The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to

generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).

8.7 Memory map

The LPC81xM incorporates several distinct memory regions. Figure 7 shows the overall

map of the entire address space from the user program viewpoint following reset. The

interrupt vector area supports address remapping.

The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,

the system tick timer (SysTick), and the reduced power modes.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

14 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

$3%ꢄSHULSKHUDOV

ꢉ[ꢃꢉꢉꢅꢄꢉꢉꢉꢉ

/3&ꢃꢄ[0

ꢃꢄ*%

ꢊꢀꢄꢇꢄꢂꢅꢄUHVHUYHG

ꢉ[ꢃꢉꢉꢍꢄꢉꢉꢉꢉ

ꢉ[))))ꢄ))))

UHVHUYHG

ꢉ[(ꢉꢀꢉꢄꢉꢉꢉꢉ

ꢉ[(ꢉꢉꢉꢄꢉꢉꢉꢉ

SULYDWHꢄSHULSKHUDOꢄEXV

ꢂꢍ

ꢂꢆ

86$57ꢂ

ꢉ[ꢃꢉꢉꢆꢄ&ꢉꢉꢉ

86$57ꢀ

UHVHUYHG

ꢉ[ꢃꢉꢉꢆꢄꢅꢉꢉꢉ

ꢂꢌ

86$57ꢉ

ꢉ[$ꢉꢉꢉꢄꢅꢉꢉꢉ

ꢉ[$ꢉꢉꢉꢄꢃꢉꢉꢉ

ꢉ[ꢃꢉꢉꢆꢄꢃꢉꢉꢉ

UHVHUYHG

SLQꢄLQWHUUXSWVꢁSDWWHUQꢄPDWFK

*3,2

ꢂꢃ

ꢂꢊ

ꢂꢂ

ꢂꢀ

ꢉ[ꢃꢉꢉꢆꢄꢉꢉꢉꢉ

63,ꢀ

ꢉ[ꢃꢉꢉꢌꢄ&ꢉꢉꢉ

ꢉ[$ꢉꢉꢉꢄꢉꢉꢉꢉ

63,ꢉ

ꢉ[ꢃꢉꢉꢌꢄꢅꢉꢉꢉ

UHVHUYHG

ꢉ[ꢌꢉꢉꢉꢄꢅꢉꢉꢉ

ꢉ[ꢌꢉꢉꢉꢄꢃꢉꢉꢉ

ꢉ[ꢌꢉꢉꢉꢄꢉꢉꢉꢉ

ꢉ[ꢃꢉꢉꢌꢄꢃꢉꢉꢉ

6&7LPHUꢁ3:0

&5&

ꢂꢉ

ꢀꢎ

,ꢂ&

ꢉ[ꢃꢉꢉꢌꢄꢉꢉꢉꢉ

UHVHUYHG

ꢉ[ꢃꢉꢉꢃꢄ&ꢉꢉꢉ

6<6&21

ꢀꢅ

ꢀꢍ

ꢉ[ꢃꢉꢉꢃꢄꢅꢉꢉꢉ

UHVHUYHG

,2&21

ꢉ[ꢃꢉꢉꢃꢄꢃꢉꢉꢉ

ꢉ[ꢃꢉꢉꢅꢄꢉꢉꢉꢉ

ꢉ[ꢃꢉꢉꢉꢄꢉꢉꢉꢉ

IODVKꢄFRQWUROOHU

UHVHUYHG

ꢀꢆ

ꢀꢌ

ꢉ[ꢃꢉꢉꢃꢄꢉꢉꢉꢉ

$3%ꢄSHULSKHUDOV

ꢀꢄ*%

ꢉ[ꢃꢉꢉꢊꢄ&ꢉꢉꢉ

ꢉ[ꢃꢉꢉꢊꢄꢅꢉꢉꢉ

ꢀꢃ

ꢀꢊ

UHVHUYHG

ꢉ[ꢃꢉꢉꢊꢄꢃꢉꢉꢉ

ꢉ[ꢃꢉꢉꢊꢄꢉꢉꢉꢉ

ꢉ[ꢂꢉꢉꢉꢄꢉꢉꢉꢉ

ꢉꢏꢌꢄ*%

ꢀꢂ

ꢀꢀ

ꢀꢉ

UHVHUYHG

ꢉ[ꢀ)))ꢄꢂꢉꢉꢉ

ꢉ[ꢀ)))ꢄꢉꢉꢉꢉ

UHVHUYHG

ꢉ[ꢃꢉꢉꢂꢄ&ꢉꢉꢉ

ꢉ[ꢃꢉꢉꢂꢄꢅꢉꢉꢉ

ꢉ[ꢃꢉꢉꢂꢄꢃꢉꢉꢉ

ꢉ[ꢃꢉꢉꢂꢄꢉꢉꢉꢉ

ꢅꢄN%ꢄERRWꢄ520

UHVHUYHG

DQDORJꢄFRPSDUDWRU

ꢎ

ꢉ[ꢀꢃꢉꢉꢄꢉꢃꢉꢉ

ꢉ[ꢀꢃꢉꢉꢄꢉꢉꢉꢉ

308

ꢅ

ꢍ

ꢆ

ꢌ

ꢃ

ꢊ

ꢂ

ꢀꢄN%ꢄ07%ꢄUHJLVWHUV

UHVHUYHG

ꢉ[ꢃꢉꢉꢀꢄ&ꢉꢉꢉ

ꢉ[ꢃꢉꢉꢀꢄꢅꢉꢉꢉ

ꢉ[ꢀꢉꢉꢉꢄꢀꢉꢉꢉ

ꢉ[ꢀꢉꢉꢉꢄꢉꢅꢉꢉ

ꢉ[ꢀꢉꢉꢉꢄꢉꢃꢉꢉ

ꢉ[ꢀꢉꢉꢉꢄꢉꢉꢉꢉ

UHVHUYHG

ꢉ[ꢃꢉꢉꢀꢄꢃꢉꢉꢉ

ꢉ[ꢃꢉꢉꢀꢄꢉꢉꢉꢉ

ꢉ[ꢃꢉꢉꢉꢄ&ꢉꢉꢉ

ꢉ[ꢃꢉꢉꢉꢄꢅꢉꢉꢉ

ꢃꢄN%ꢄꢄ65$0ꢄꢐ/3&ꢅꢀꢂꢑ

ꢂꢄN%ꢄꢄ65$0ꢄꢐ/3&ꢅꢀꢀꢑ

ꢀꢄN%ꢄꢄ65$0ꢄꢐ/3&ꢅꢀꢉꢑ

VZLWFKꢄPDWUL[

ꢄVHOIꢄZDNHꢇXSꢄWLPHU

057

UHVHUYHG

ꢀ

ꢉ

ꢉ[ꢃꢉꢉꢉꢄꢃꢉꢉꢉ

ꢉ[ꢃꢉꢉꢉꢄꢉꢉꢉꢉ

::'7

ꢉ[ꢉꢉꢉꢉꢄꢃꢉꢉꢉ

ꢉ[ꢉꢉꢉꢉꢄꢂꢉꢉꢉ

ꢉ[ꢉꢉꢉꢉꢄꢀꢉꢉꢉ

ꢉ[ꢉꢉꢉꢉꢄꢉꢉꢉꢉ

ꢀꢆꢄN%ꢄRQꢇFKLSꢄIODVKꢄꢐ/3&ꢅꢀꢂꢑ

ꢅꢄN%ꢄRQꢇFKLSꢄIODVKꢄꢐ/3&ꢅꢀꢀꢑ

ꢃꢄN%ꢄRQꢇFKLSꢄIODVKꢄꢐ/3&ꢅꢀꢉꢑ

ꢉ[ꢉꢉꢉꢉꢄꢉꢉ&ꢉ

ꢉ[ꢉꢉꢉꢉꢄꢉꢉꢉꢉ

DFWLYHꢄLQWHUUXSWꢄYHFWRUV

ꢉꢄ*%

DDDꢀꢁꢁꢂꢃꢄꢇ

Fig 7. LPC81xM Memory map

8.8 I/O configuration

The IOCON block controls the configuration of the I/O pins. Each digital or mixed

digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10

and PIO0_11) in Table 4 can be configured as follows:

• Enable or disable the weak internal pull-up and pull-down resistors.

• Select a pseudo open-drain mode. The input cannot be pulled up above V_DD. This pin

is not 5 V tolerant when V_DD= 0.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

15 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• Program the input glitch filter with different filter constants using one of the IOCON

divided clock signals (IOCONCLKCDIV, see Figure 10 “LPC81xM clock generation”).

You can also bypass the glitch filter.

• Invert the input signal.

• Hysteresis can be enabled or disabled.

• For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard

digital operation, for I2C standard and fast modes, or for I2C Fast mode+.

• On mixed digital/analog pins, enable the analog input mode. Enabling the analog

mode disconnects the digital functionality.

Remark: The functionality of each I/O pin is flexible and is determined entirely through the

switch matrix. See Section 8.9 for details.

8.8.1 Standard I/O pad configuration

Figure 8 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver with configurable open-drain output

• Digital input: Weak pull-up resistor (PMOS device) enabled/disabled

• Digital input: Weak pull-down resistor (NMOS device) enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Digital input: Input glitch filter selectable on all pins

• Analog input

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

16 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

9

''

9

''

RSHQꢇGUDLQꢄHQDEOH

RXWSXWꢄHQDEOH

GDWDꢄRXWSXW

VWURQJ

SXOOꢇXS

(6'

SLQꢄFRQILJXUHG

DVꢄGLJLWDOꢄRXWSXW

GULYHU

3,1

VWURQJ

SXOOꢇGRZQ

(6'

9

66

9

''

ZHDN

SXOOꢇXS

SXOOꢇXSꢄHQDEOH

ZHDN

SXOOꢇGRZQ

UHSHDWHUꢄPRGH

HQDEOH

SLQꢄFRQILJXUHG

DVꢄGLJLWDOꢄLQSXW

SXOOꢇGRZQꢄHQDEOH

GDWDꢄLQSXW

352*5$00$%/(

*/,7&+ꢄ),/7(5

VHOHFWꢄGDWD

LQYHUWHU

VHOHFWꢄJOLWFK

ILOWHU

VHOHFWꢄDQDORJꢄLQSXW

SLQꢄFRQILJXUHG

DVꢄDQDORJꢄLQSXW

DQDORJꢄLQSXW

DDDꢀꢁꢁꢄꢆꢃꢃ

Fig 8. Standard I/O pad configuration

8.9 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a

highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and

I2C functions to any pin that is not power or ground. These functions are called movable

functions and are listed in Table 5.

Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can

be enabled or disabled through the switch matrix. These functions are called fixed-pin

functions and cannot move to other pins. The fixed-pin functions are listed in Table 4. If a

fixed-pin function is disabled, any other movable function can be assigned to this pin.

8.10 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC81xM use accelerated GPIO functions:

• GPIO registers are located on the ARM Cortex M0+ IO bus for fastest possible

single-cycle I/O timing, allowing GPIO toggling with rates of up to 15 MHz.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

17 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• An entire port value can be written in one instruction.

• Mask, set, and clear operations are supported for the entire port.

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be

moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and

RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

8.10.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to inputs with internal pull-up resistors enabled after reset - except for

the I²C-bus true open-drain pins PIO0_2 and PIO0_3.

• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 8).

•

8.11 Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC.

The pattern match engine can be used, in conjunction with software, to create complex

state machines based on pin inputs.

Any digital pin, independently of the function selected through the switch matrix, can be

configured through the SYSCON block as input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the IO+ bus for fast single-cycle access.

8.11.1 Features

• Pin interrupts

– Up to eight pins can be selected from all digital pins as edge- or level-sensitive

interrupt requests. Each request creates a separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH- or LOW-active.

– Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and

power-down mode.

• Pin interrupt pattern match engine

– Up to eight pins can be selected from all digital pins to contribute to a boolean

expression. The boolean expression consists of specified levels and/or transitions

on various combinations of these pins.

– Each minterm (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can be programmed to also generate an RXEV

notification to the ARM CPU. The RXEV signal can be connected to a pin.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

18 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

– The pattern match engine does not facilitate wake-up.

8.12 USART0/1/2

Remark: USART0 and USART1 are available on all LPC800 parts. USART2 is available

on parts LPC812M101JDH16 and LPC812M101JDH20 only.

All USART functions are movable functions and are assigned to pins through the switch

matrix.

8.12.1 Features

• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode for USART functions connected to all digital pins except PIO0_10

and PIO0_11.

• 7, 8, or 9 data bits and 1 or 2 stop bits

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485

possible with software address detection and transceiver direction control.)

• Parity generation and checking: odd, even, or none.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator.

• A fractional rate divider is shared among all UARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Separate data and flow control loopback modes for testing.

• Supported by on-chip ROM API.

8.13 SPI0/1

Remark: SPI0 is available on all LPC800 parts. SPI1 is available on parts

LPC812M101JDH16 and LPC812M101JDH20 only.

All SPI functions are movable functions and are assigned to pins through the switch

matrix.

8.13.1 Features

• Maximum data rates of 30 Mbit/s in master mode and 25 Mbit/s in slave mode for SPI

functions connected to all digital pins except PIO0_10 and PIO0_11.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

19 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• One Slave Select input/output with selectable polarity and flexible usage.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

8.14 I2C-bus interface

The I²C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master connected to it.

The I2C-bus functions are movable functions and can be assigned through the switch

matrix to any pin. However, only the true open-drain PIO0_10 and PIO0_11 provide the

electrical characteristics to support the full I2C-bus specification (see Ref. 1).

8.14.1 Features

• Supports standard and fast mode with data rates of up to 400 kbit/s.

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I²C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I²C bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

• Supported by on-chip ROM API.

• If the I2C functions are connected to the true open-drain pins (PIO0_10 and

PIO0_11), the I2C supports the full I2C-bus specification:

– Fail-safe operation: When the power to an I²C-bus device is switched off, the SDA

and SCL pins connected to the I²C-bus are floating and do not disturb the bus.

– Supports Fast-mode Plus with bit rates up to 1 Mbit/s.

8.15 State-Configurable Timer/PWM (SCTimer/PWM)

The state configurable timer (SCTimer/PWM or SCT) can perform basic 16-bit and 32-bit

timer/counter functions with match outputs and external and internal capture inputs. In

addition, the SCTimer/PWM can employ up to two different programmable states, which

can change under the control of events, to provide complex timing patterns.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

20 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

All inputs and outputs of the SCTimer/PWM are movable functions and are assigned to

pins through the switch matrix.

8.15.1 Features

• Two 16-bit counters or one 32-bit counter.

• Counters clocked by bus clock or selected input.

• Up counters or up-down counters.

• State variable allows sequencing across multiple counter cycles.

• The following conditions define an event: a counter match condition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state, and the count direction.

• Events control outputs, interrupts, and the SCT states.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected events can limit, halt, start, or stop a counter.

• Supports:

– 4 inputs

– 4 outputs

– 5 match/capture registers

– 6 events

– 2 states

8.16 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

8.16.1 Features

• 31-bit interrupt timer

• Four channels independently counting down from individually set values

• Bus stall, repeat and one-shot interrupt modes

8.17 Windowed WatchDog Timer (WWDT)

The watchdog timer resets the controller if software fails to periodically service it within a

programmable time window.

8.17.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

21 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2²⁴ 4) in

multiples of T_cy(WDCLK) 4.

• The Watchdog Clock (WDCLK)is generated by a the dedicated watchdog oscillator

(WDOSC).

8.18 Self Wake-up Timer (WKT)

The self wake-up timer is a 32-bit, loadable down-counter. Writing any non-zero value to

this timer automatically enables the counter and launches a count-down sequence. When

the counter is used as a wake-up timer, this write can occur just prior to entering a

reduced power mode.

8.18.1 Features

• 32-bit loadable down-counter. Counter starts automatically when a count value is

loaded. Time-out generates an interrupt/wake up request.

• The WKT resides in a separate, always-on power domain.

• The WKT supports two clock sources: the low-power oscillator and the IRC. The

low-power oscillator is located in the always-on power domain, so it can be used as

the clock source in Deep power-down mode.

• The WKT can be used for waking up the part from any reduced power mode,

including Deep power-down mode, or for general-purpose timing.

8.19 Analog comparator (ACMP)

The analog comparator with selectable hysteresis can compare voltage levels on external

pins and internal voltages.

After power-up and after switching the input channels of the comparator, the output of the

voltage ladder must be allowed to settle to its stable value before it can be used as a

comparator reference input. Settling times are given in Table 22.

The analog comparator output is a movable function and is assigned to a pin through the

switch matrix. The comparator inputs and the voltage reference are enabled or disabled

on pins PIO0_0 and PIO0_1 through the switch matrix.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

22 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

&203$5$725ꢄ$1$/2*ꢄ%/2&.

&203$5$725ꢄ',*,7$/ꢄ%/2&.

9

''

9''&03

ꢂ

ꢊꢂ

FRPSDUDWRU

OHYHOꢄ$&03B2

V\QF

HGJHꢄGHWHFW

FRPSDUDWRU

HGJHꢄ19,&

LQWHUQDO

YROWDJH

UHIHUHQFH

ꢂ

$&03B,>ꢂꢋꢀ@

DDDꢀꢁꢁꢄꢂꢁꢇ

Fig 9. Comparator block diagram

8.19.1 Features

• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input

hysteresis.

• Two selectable external voltages (V_DDor VDDCMP on pin PIO0_6); fully configurable

on either positive or negative input channel.

• Internal voltage reference from band gap selectable on either positive or negative

input channel.

• 32-stage voltage ladder with the internal reference voltage selectable on either the

positive or the negative input channel.

• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V

supply voltage rail.

• Voltage ladder can be separately powered down for applications only requiring the

comparator function.

• Interrupt output is connected to NVIC.

• Comparator level output is connected to output pin ACMP_O.

• The comparator output can be routed internally to the SCT input through the switch

matrix.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

23 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.20 Clocking and power control

6<6&21

$+%ꢄFORFNꢄꢉ

ꢐFRUHꢈꢄV\VWHPꢒꢄ

PDLQꢄFORFN

V\VWHPꢄFORFN

DOZD\VꢇRQꢑ

&/2&.ꢄ',9,'(5

6<6$+%&/.',9

ꢀꢎ

PHPRULHV

DQGꢄSHULSKHUDOVꢈ

SHULSKHUDOꢄFORFNV

6<6$+%&/.&75/>ꢀꢋꢀꢎ@

ꢐV\VWHPꢄFORFNꢄHQDEOHꢑ

86$57ꢉ

86$57ꢀ

86$57ꢂ

)5$&7,21$/ꢄ5$7(

*(1(5$725

&/2&.ꢄ',9,'(5

8$57&/.',9

,5&ꢄRVFLOODWRU

ꢍ

,2&21ꢄ

JOLWFKꢄILOWHU

&/2&.ꢄ',9,'(5

,2&21&/.',9

ZDWFKGRJꢄRVFLOODWRU

0$,1&/.6(/

ꢐPDLQꢄFORFNꢄVHOHFWꢑ

,5&ꢄRVFLOODWRU

V\VWHPꢄRVFLOODWRU

ZDWFKGRJꢄRVFLOODWRU

&/2&.ꢄ',9,'(5

&/.287',9

&/.287ꢄSLQ

;7$/,1

;7$/287

6<67(0

26&,//$725

6<67(0ꢄꢄ3//

&/.,1

&/.2876(/

ꢐ&/.287ꢄFORFNꢄVHOHFWꢑ

6<63//&/.6(/

V\VWHPꢄ3//ꢄFORFNꢄVHOHFW

::'7

:.7

ZDWFKGRJꢄRVFLOODWRU

,5&ꢄRVFLOODWRU

308

:.7

ORZꢇSRZHUꢄRVFLOODWRU

DDDꢀꢁꢁꢂꢃꢄꢈ

Fig 10. LPC81xM clock generation

8.20.1 Crystal and internal oscillators

The LPC81xM include four independent oscillators:

1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz.

2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1%

accuracy.

3. The internal low-power, low-frequency Oscillator with a nominal frequency of 10 kHz

with 40% accuracy for use with the self wake-up timer.

4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal

frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

24 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Each oscillator, except the low-frequency oscillator, can be used for more than one

purpose as required in a particular application.

Following reset, the LPC81xM will operate from the IRC until switched by software. This

allows systems to operate without any external crystal and the bootloader code to operate

at a known frequency.

See Figure 10 for an overview of the LPC81xM clock generation.

8.20.1.1 Internal RC Oscillator (IRC)

The IRC may be used as the clock source for the WWDT, and/or as the clock that drives

the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1.5 % accuracy over the entire voltage and temperature range.

The IRC can be used as a clock source for the CPU with or without using the PLL. The

IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating

frequency, by the system PLL.

Upon power-up or any chip reset, the LPC81xM use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

8.20.1.2 Crystal Oscillator (SysOsc)

The crystal oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted

to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

8.20.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc)

The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz.

The frequency spread over silicon process variations is  40%.

The WDOsc is a dedicated oscillator for the windowed WWDT.

The internal low-power 10 kHz (  40% accuracy) oscillator serves a the clock input to the

WKT. This oscillator can be configured to run in all low power modes.

8.20.2 Clock input

An external clock source can be supplied on the selected CLKIN pin. When selecting a

clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 9 “Static

characteristics” and Table 15 “Dynamic characteristics: I/O pins^[1]”.

An 1.8 V external clock source can be supplied on the XTALIN pins to the system

oscillator limiting the voltage of this signal ((see Section 14.2).

The maximum frequency for both clock signals is 25 MHz.

8.20.3 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

25 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is nominally 100 s.

8.20.4 Clock output

The LPC81xM features a clock output function that routes the IRC, the SysOsc, the

watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can

be connected to any digital pin through the switch matrix.

8.20.5 Wake-up process

The LPC81xM begin operation at power-up by using the IRC as the clock source. This

allows chip operation to resume quickly. If the SysOsc, the external clock source, or the

PLL is needed by the application, software must enable these features and wait for them

to stabilize before they are used as a clock source.

8.20.6 Power control

The LPC81xM supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also

be controlled as needed by changing clock sources, reconfiguring PLL values, and/or

altering the CPU clock divider value. This allows a trade-off of power versus processing

speed based on application requirements. In addition, a register is provided for shutting

down the clocks to individual on-chip peripherals, allowing to fine-tune power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides even

better power control.

8.20.6.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile API. The API is accessible through the on-chip

ROM.

The power configuration routine configures the LPC81xM for one of the following power

modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

8.20.6.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

26 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

8.20.6.3 Deep-sleep mode

In Deep-sleep mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if

selected. The IRC output is disabled. In addition all analog blocks are shut down and the

flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog

oscillator and the BOD circuit running for self-timed wake-up and BOD protection.

The LPC81xM can wake up from Deep-sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave mode).

Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Deep-sleep mode saves power and allows for short wake-up times.

8.20.6.4 Power-down mode

In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

clock sources are off except for watchdog oscillator or low-power oscillator if selected. In

addition all analog blocks and the flash are shut down. In Power-down mode, the

application can keep the watchdog oscillator and the BOD circuit running for self-timed

wake-up and BOD protection.

The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave mode).

Any interrupt used for waking up from Power-down mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Power-down mode reduces power consumption compared to Deep-sleep mode at the

expense of longer wake-up times.

8.20.6.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

pin and the self wake-up timer if enabled. Four general-purpose registers are available to

store information during Deep power-down mode. The LPC81xM can wake up from Deep

power-down mode via the WAKEUP pin, or without an external signal by using the

time-out of the self wake-up timer (see Section 8.18).

The LPC81xM can be prevented from entering Deep power-down mode by setting a lock

bit in the PMU block. Locking out Deep power-down mode enables the application to keep

the watchdog timer or the BOD running at all times.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

27 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in

Deep power-down mode.

8.21 System control

8.21.1 Reset

Reset has four sources on the LPC81xM: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

In Deep power-down mode, an external pull-up resistor is required on the RESET pin.

9

''

9

''

9

''

5

SX

(6'

ꢂꢉꢄQVꢄ5&

*/,7&+ꢄ),/7(5

UHVHW

3,1

(6'

9

66

DDDꢀꢁꢁꢄꢅꢉꢆ

Fig 11. Reset pad configuration

8.21.2 Brownout detection

The LPC81xM includes up to four levels for monitoring the voltage on the V_DDpin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a

dedicated status register. Four threshold levels can be selected to cause a forced reset of

the chip.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

28 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.21.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For

details, see the LPC800 user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using the

ISP entry pin as well. If necessary, the application must provide a flash update

mechanism using IAP calls or using a call to the reinvoke ISP command to enable

flash update via the USART.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can

be disabled. For details, see the LPC800 user manual.

8.21.4 APB interface

The APB peripherals are located on one APB bus.

8.21.5 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the

main static RAM, the CRC, and the ROM.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

29 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

8.22 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is

configured to support up to four breakpoints and two watch points.

The Micro Trace Buffer is implemented on the LPC81xM.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC81xM

is in reset. The JTAG boundary scan pins are selected by hardware when the part is in

boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 4).

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

9

''

/3&ꢃꢁꢁ

975()

6:',2

6:&/.

Q5(6(7

*1'

6:',2

IURPꢄ6:'

FRQQHFWRU

6:&/.

5(6(7

3,2ꢉBꢀꢂꢄ

ꢄ

,63ꢄHQWU\

DDDꢀꢁꢁꢅꢁꢇꢅ

Fig 12. Connecting the SWD pins to a standard SWD connector

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

30 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

9. Limiting values

Table 7.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol Parameter

Conditions

Min

0.5

Max

+4.6

+5.5

Unit

V

[2]

[3]

[4]

V_DD

V_I

supply voltage (core and external rail)

input voltage

5 V tolerant I/O pins; V_DD 1.8 V

V

5 V tolerant open-drain pins PIO0_10

and PIO0_11

V

[5]

3 V tolerant I/O pin PIO0_6

0.5

+3.6

4.6

V

[6]

[7]

V_IA

analog input voltage

[2]

V_i(xtal)

I_DD

crystal input voltage

supply current

0.5

+2.5

100

V

per supply pin

-

mA

I_SS

ground current

per ground pin

(0.5V_DD) < V_I< (1.5V_DD);

T_j< 125 C

I_latch

I/O latch-up current

[8]

[9]

T_stg

storage temperature

non-operating

65

+150

150

1.5

C

W

T_j(max)

maximum junction temperature

-

P_tot(pack)total power dissipation (per package)

based on package heat transfer, not

device power consumption

V_ESDelectrostatic discharge voltage

human body model; all pins

-

5500

1200

V

charged device model; TSSOP20 and

SOP20 packages

charged device model; TSSOP16

package

-

1000

800

V

charged device model; XSON16

package

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

c) The limiting values are stress ratings only. Operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 9.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 9) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Including voltage on outputs in tri-state mode. Does not apply to pin PIO0_6.

[4] V_DDpresent or not present. Compliant with the I²C-bus standard. 5.5 V can be applied to this pin when V_DDis powered down.

[5] V_DDpresent or not present.

[6] If the comparator is configured with the common mode input V_IC= V_DD, the other comparator input can be up to 0.2 V above or below

V_DDwithout affecting the hysteresis range of the comparator function.

[7] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[8] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[9] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

31 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

10. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T_j= T_amb+ P_D R_{thj – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 8.

Thermal resistance

Symbol Parameter

DIP8

Conditions

Max/Min

Unit

R_th(j-a)

thermal resistance from

JEDEC (4.5 in  4 in); still air

60 ± 15 % C/W

junction to ambient

Single-layer (4.5 in  3 in); still air 81 ± 15 % C/W

38 ± 15 % C/W

R_th(j-c)

thermal resistance from

junction to case

TSSOP16

R_th(j-a)

thermal resistance from

junction to ambient

JEDEC (4.5 in  4 in); still air

133 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 182 ± 15 % C/W

33 ± 15 % C/W

R_th(j-c)

thermal resistance from

junction to case

TSSOP20

R_th(j-a)

thermal resistance from

junction to ambient

JEDEC (4.5 in  4 in); still air

110 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 153 ± 15 % C/W

23 ± 15 % C/W

R_th(j-c)

thermal resistance from

junction to case

SO20

R_th(j-a)

thermal resistance from

junction to ambient

JEDEC (4.5 in  4 in); still air

87 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 112 ± 15 % C/W

50 ± 15 % C/W

R_th(j-c)

thermal resistance from

junction to case

XSON16

R_th(j-a)

thermal resistance from

junction to ambient

JEDEC (4.5 in  4 in); still air

92 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 180 ± 15 % C/W

27 ± 15 % C/W

R_th(j-c)

thermal resistance from

junction to case

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

32 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11. Static characteristics

Table 9.

Static characteristics

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

V_DD

Parameter

Conditions

Min

Typ^[1]

Max

Unit

supply voltage (core

and external rail)

1.8

3.3

3.6

V

I_DD

supply current

Active mode; code

while(1){}

executed from flash;

[2][3][4][5]

system clock = 12 MHz; default

mode; V_DD= 3.3 V

-

1.4

1.0

2.2

3.3

3

-

mA

[2][3][4][5]

[6]

system clock = 12 MHz;

low-current mode; V_DD= 3.3 V

[2][4][5][6]

[7]

system clock = 24 MHz;

low-current mode; V_DD= 3.3 V

[2][4][5][8]

system clock = 30 MHz; default

mode; V_DD= 3.3 V

[2][4][5][6]

[8]

system clock = 30 MHz;

low-current mode; V_DD= 3.3 V

Sleep mode

[2][3][4][5]

system clock = 12 MHz; default

mode; V_DD= 3.3 V

-

0.8

0.7

1.3

1.8

1.7

-

mA

[2][3][4][5]

[6]

system clock = 12 MHz;

low-current mode; V_DD= 3.3 V

[2][4][5][6]

[7]

system clock = 24 MHz;

low-current mode; V_DD= 3.3 V

[2][4][5][8]

system clock = 30 MHz; default

mode; V_DD= 3.3 V

[2][4][5][6]

[8]

system clock = 30 MHz;

low-current mode; V_DD= 3.3 V

Deep-sleep mode

[2][9]

V

_DD= 3.3 V, T_amb= 25 °C

-

150

-

300

400

A

V_DD= 3.3 V, T_amb= 105 °C

Power-down mode

[2][9]

V_DD= 3.3 V, T_amb= 25 °C

V_DD= 3.3 V, T_amb= 105 °C

-

0.9

-

5

A

40

Deep power-down mode;

Low-power oscillator and self

wakeup timer (WKT) disabled

[10]

V_DD= 3.3 V, T_amb= 25 °C

V_DD= 3.3 V, T_amb= 105 °C

-

170

1000

nA

A

-

4

-

Deep power-down mode;

1

Low-power oscillator and self

wakeup timer (WKT) enabled

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

33 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 9.

Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Standard port pins configured as digital pins, RESET; see Figure 13

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

-

0.5

-

10

5.0

3.6

nA

V

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD; on-chip pull-down

resistor disabled

-

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

-

[11]

[12]

input voltage

V_DD 1.8 V; 5 V tolerant pins

0

except PIO0_6

V_DD 1.8 V; on 3 V tolerant pin

-

PIO0_6

V_DD= 0 V

0

-

3.6

V_DD

-

V

V_O

output voltage

output active

0

V_IH

HIGH-level input

voltage

0.7V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

V_OH

0.4

-

V

HIGH-level output

voltage

2.5 V  V_DD 3.6 V; I_OH= 4 mA

1.8 V  V_DD< 2.5 V; I_OH= 3 mA

2.5 V  V_DD 3.6 V; I_OL= 4 mA

1.8 V  V_DD< 2.5 V; I_OL= 3 mA

V_OH= V_DD 0.4 V;

V_DD 0.4 -

-

V

-

V

V_OL

LOW-level output

voltage

-

0.4

-

V

-

V

I_OH

HIGH-level output

current

4

mA

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

4

-

mA

I_OL

LOW-level output

current

V_OL= 0.4 V

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

-

mA

[13]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

45

LOW-level short-circuit V_OL= V_DD

output current

-

50

mA

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

V_I= 0 V;

10

15

50

150

85

A

2.0 V  V_DD 3.6 V

1.8 V  V_DD< 2.0 V

10

0

50

0

85

0

A

V_DD< V_I< 5 V

High-drive output pins configured as digital pins (PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13); see Figure 13

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

-

0.5

10

nA

I_IH

I_OZ

HIGH-level input

current

V_I= V_DD; on-chip pull-down

resistor disabled

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

34 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 9.

Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[11]

[12]

V_I

input voltage

V_DD 1.8 V

0

-

5.0

V

V_DD= 0 V

0

-

3.6

V_DD

-

V

V_O

output voltage

output active

0

V_IH

HIGH-level input

voltage

0.7V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

V_OH

0.4

-

V

HIGH-level output

voltage

2.5 V  V_DD 3.6 V; I_OH= 20 mA

1.8 V  V_DD< 2.5 V; I_OH= 12 mA

2.5 V  V_DD 3.6 V; I_OL= 4 mA

1.8 V  V_DD< 2.5 V; I_OL= 3 mA

V_DD 0.4 -

-

V

-

V

V_OL

LOW-level output

voltage

-

0.4

-

V

-

V

I_OH

HIGH-level output

current

V_OH= V_DD 0.4 V;

2.5 V  V_DD 3.6 V

20

mA

1.8 V  V_DD< 2.5 V

V_OL= 0.4 V

12

4

-

mA

I_OL

LOW-level output

current

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

-

mA

[13]

I_OLS

LOW-level short-circuit V_OL= V_DD

output current

50

[14]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

V_I= 0 V

10

15

50

150

85

A

2.0 V  V_DD 3.6 V

1.8 V  V_DD< 2.0 V

10

0

50

0

85

0

A

V_DD< V_I< 5 V

I²C-bus pins (PIO0_10 and PIO0_11); see Figure 13

V_IH

HIGH-level input

voltage

0.7V_DD

-

V

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3V_DD

V

V_hys

I_OL

-

0.05V_DD

-

V

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as standard mode pins

3.5

mA

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

-

I_OL

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as Fast-mode Plus

pins

20

mA

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

V_I= V_DD

16

-

[15]

I_LI

input leakage current

2

4

A

V_I= 5 V

-

10

22

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

35 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 9.

Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Oscillator input pins (PIO0_8 and PIO0_9)

V_i(xtal)

crystal input voltage

crystal output voltage

0.5

1.8

1.95

V

V_o(xtal)

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] I_DDmeasurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[3] IRC enabled; system oscillator disabled; system PLL disabled.

[4] BOD disabled.

[5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system

configuration block.

[6] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[7] IRC enabled; system oscillator disabled; system PLL enabled.

[8] IRC disabled; system oscillator enabled; system PLL enabled.

[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[10] WAKEUP pin pulled HIGH externally.

[11] Including voltage on outputs in tri-state mode.

[12] 3-state outputs go into tri-state mode in Deep power-down mode.

[13] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[14] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 8.

[15] To V_SS

.

/3&ꢃꢁꢁ

9

''

,

2/

SG

ꢓ

ꢇ

SLQꢄ3,2ꢉBQ

$

,

2+

,SX

ꢇ

ꢓ

SLQꢄ3,2ꢉBQ

$

DDDꢇꢉꢉꢃꢆꢃꢉ

Fig 13. Pin input/output current measurement

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

36 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.1 Power consumption

Power measurements in Active, Sleep, Deep-sleep,and Power-down modes were

performed under the following conditions:

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

• Configure GPIO pins as outputs using the GPIO DIR register.

• Write 1 to the GPIO CLR register to drive the outputs LOW.

DDDꢀꢁꢁꢃꢈꢇꢄ

ꢊ

,

''

ꢐP$ꢑ

ꢂꢏꢃ

ꢀꢏꢅ

ꢀꢏꢂ

ꢉꢏꢆ

ꢉ

ꢊꢉꢄ0+]

ꢂꢃꢄ0+]

ꢀꢂꢄ0+]

ꢆꢄ0+]

ꢃꢄ0+]

ꢊꢄ0+]

ꢂꢄ0+]

ꢀꢄ0+]

ꢀꢏꢅ

ꢂꢏꢀꢆ

ꢂꢏꢌꢂ

ꢂꢏꢅꢅ

ꢊꢏꢂꢃ

ꢊꢏꢆ

9

''

ꢄꢐ9ꢑ

Conditions: T_amb= 25 C; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: IRC disabled; SYSOSC enabled; PLL enabled.

Fig 14. Active mode: Typical supply current I_DDversus supply voltage V_DD

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

37 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

DDDꢀꢁꢁꢃꢈꢇꢆ

ꢊ

,,

''

ꢐP$ꢑ

ꢂꢏꢃ

ꢀꢏꢅ

ꢀꢏꢂ

ꢉꢏꢆ

ꢉ

ꢊꢉꢄ0+]

ꢂꢃꢄ0+]

ꢀꢂꢄ0+]

ꢆꢄ0+]

ꢃꢄ0+]

ꢊꢄ0+]

ꢂꢄ0+]

ꢀꢄ0+]

ꢇꢃꢉ

ꢇꢀꢀ

ꢀꢅ

ꢃꢍ

ꢍꢆ

ꢀꢉꢌ

WHPSHUDWXUHꢄꢐ&ꢑ

Conditions: V_DD= 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: IRC disabled; SYSOSC enabled; PLL enabled.

Fig 15. Active mode: Typical supply current I_DDversus temperature

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

38 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

DDDꢀꢁꢁꢃꢈꢇꢂ

ꢂ

,,

''

ꢐP$ꢑ

ꢀꢏꢆ

ꢀꢏꢂ

ꢉꢏꢅ

ꢉꢏꢃ

ꢉ

ꢊꢉꢄ0+]

ꢂꢃꢄ0+]

ꢀꢂꢄ0+]

ꢆꢄ0+]

ꢃꢄ0+]

ꢊꢄ0+]

ꢂꢄ0+]

ꢀꢄ0+]

ꢇꢃꢉ

ꢇꢀꢀ

ꢀꢅ

ꢃꢍ

ꢍꢆ

ꢀꢉꢌ

WHPSHUDWXUHꢄꢐ&ꢑ

Conditions: V_DD= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: IRC disabled; SYSOSC enabled; PLL enabled.

Fig 16. Sleep mode: Typical supply current I_DDversus temperature for different system

clock frequencies

DDDꢀꢁꢁꢃꢈꢅꢄ

ꢂꢉꢉ

ꢊꢏꢆꢄ9

ꢊꢏꢉꢄ9

ꢀꢏꢅꢄ9

,''

''

ꢐȝ$ꢑ

ꢀꢅꢉ

ꢀꢆꢉ

ꢀꢃꢉ

ꢀꢂꢉ

ꢀꢉꢉ

ꢇꢃꢉ

ꢇꢀꢌ

ꢀꢉ

ꢊꢌ

ꢆꢉ

ꢅꢌ

WHPSHUDWXUHꢄꢐꢄ&ꢑ

ꢀꢀꢉ

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 17. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

39 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

DDDꢀꢁꢁꢃꢈꢅꢆ

ꢊꢌ

ꢂꢅ

ꢂꢀ

ꢀꢃ

ꢍ

,''

''

ꢐȝ$ꢑ

ꢊꢏꢆꢄ9

ꢊꢏꢊꢄ9

ꢀꢏꢅꢄ9

ꢉ

ꢇꢃꢉ

ꢇꢀꢌ

ꢀꢉ

ꢊꢌ

ꢆꢉ

ꢅꢌ

ꢀꢀꢉ

WHPSHUDWXUHꢄꢐꢄ&ꢑ

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 18. Power-down mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

DDDꢀꢁꢁꢃꢈꢅꢊ

ꢊ

,''

''

ꢐȝ$ꢑ

ꢂꢏꢌ

ꢂ

ꢊꢏꢆꢄ9

ꢊꢏꢉꢄ9

ꢀꢏꢅꢄ9

ꢀꢏꢌ

ꢀ

ꢉꢏꢌ

ꢉ

ꢇꢃꢉ

ꢇꢀꢌ

ꢀꢉ

ꢊꢌ

ꢆꢉ

ꢅꢌ

WHPSHUDWXUHꢄꢐꢄ&ꢑ

ꢀꢀꢉ

WKT not running.

Fig 19. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

40 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.2 CoreMark data

DDDꢀꢁꢁꢃꢈꢇꢅ

ꢌ

ꢃ

ꢊ

ꢂ

ꢀ

ꢉ

,''

''

ꢐP$ꢑ

'HIDXOW

&38ꢁHIILFLHQF\

/RZꢇFXUUHQW

ꢉ

ꢃ

ꢅ

ꢀꢂ

ꢀꢆ

ꢂꢉ

ꢂꢃ

V\VWHPꢄFORFNꢄIUHTXHQF\ꢄꢐ0+]ꢑ

Conditions: V_DD= 3.3 V; T_amb= 25 C; active mode; all peripherals except one UART and the SCT

disabled in the SYSAHBCLKCTRL register; system clock derived from the IRC; system oscillator

disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7.

Fig 20. Active mode: CoreMark power consumption I_DD

DDDꢀꢁꢁꢃꢈꢇꢃ

ꢂꢏꢌ

&0

ꢐꢐLWHUDWLRQVꢁVꢑꢁ0+]ꢑꢑ

ꢐP$ꢑ

&&3388ꢁꢁHHIIILFLHQF\

ꢂ

ꢀꢏꢌ

ꢀ

'HIDXOW

/RZꢇFXUUHQW

ꢉꢏꢌ

ꢉ

ꢃ

ꢅ

ꢀꢂ

ꢀꢆ

ꢂꢉ

ꢂꢃ

V\VWHPꢄFORFNꢄIUHTXHQF\ꢄꢐ0+]ꢑ

Conditions: V_DD= 3.3 V; active mode; all peripherals except one UART and the SCT disabled in

the SYSAHBCLKCTRL register; internal pull-up resistors enabled; BOD disabled. Measured with

Keil uVision v.4.7.

Fig 21. CoreMark score

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

41 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.3 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Measured on a typical sample at T_amb= 25 C. Unless

noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz.

Table 10. Power consumption for individual analog and digital blocks

Peripheral

Typical supply current in mA

Notes

n/a

12 MHz

30 MHz

IRC

0.21

-

System oscillator running; PLL off; independent

of main clock frequency.

System oscillator at 12 MHz

0.28

-

IRC running; PLL off; independent of main clock

frequency.

Watchdog oscillator at

500 kHz/2

0.002

System oscillator running; PLL off; independent

of main clock frequency.

BOD

0.05

-

Independent of main clock frequency.

-

Main PLL

CLKOUT

-

0.31

0.06

-

0.09

Main clock divided by 4 in the CLKOUTDIV

register.

ROM

I2C

-

0.08

0.06

0.09

0.19

0.15

0.23

-

GPIO + pin interrupt/pattern

match

GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

register.

SWM

-

0.03

0.17

0.01

0.09

0.05

0.06

0.03

0.04

0.07

0.42

0.03

0.21

0.13

0.14

0.07

0.10

0.11

0.10

-

SCT

WKT

MRT

SPI0

SPI1

CRC

USART0

USART1

USART2

WWDT

Main clock selected as clock source for the

WDT.

IOCON

-

0.03

0.04

0.08

0.09

-

Comparator

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

42 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

11.4 Electrical pin characteristics

DDDꢀꢁꢁꢃꢇꢅꢁ

ꢊꢏꢆ

ꢇꢃꢉꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ9Y

ꢂꢌꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢅꢌꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢀꢉꢌꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

92+

2+

ꢐP$ꢑ

ꢊꢏꢂ

ꢂꢏꢅ

ꢂꢏꢃ

ꢂ

ꢇꢃꢉꢄ¡&&ꢁꢁꢀꢊꢏꢏꢅꢊꢄꢄ9Y

ꢂꢌꢄ¡&&ꢁꢁꢀꢊꢏꢏꢅꢊꢄꢄ99

ꢅꢌꢄ¡&&ꢁꢁꢀꢊꢏꢏꢅꢊꢄꢄ99

ꢀꢉꢌꢄ¡&&ꢁꢁꢀꢊꢏꢏꢅꢊꢄꢄ99

ꢀꢏꢆ

ꢀꢏꢂ

ꢉ

ꢀꢉ

ꢂꢉ

ꢊꢉ

ꢃꢉ

ꢌꢉ

ꢆꢉ

ꢍꢉ

ꢄꢐP$ꢑ

ꢅꢉ

,

2+

Conditions: V_DD= 3.3 V and V_DD= 1.8 V; on pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13.

Fig 22. High-drive output: Typical HIGH-level output voltage V_OHversus HIGH-level

output current I_OH

DDDꢀꢁꢁꢃꢇꢂꢈ

ꢇꢃꢉꢄ"&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢆꢉ

,2/

2/

ꢐP$ꢑ

ꢂꢌꢄ"&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢅꢌꢄ"&&ꢁꢁꢄꢄꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢀꢉꢌꢄ"&&ꢁꢁꢄꢄꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢇꢃꢉꢄ"&&ꢁꢁꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢂꢌꢄ"&&ꢁꢁꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢅꢌꢄ"&&ꢁꢁꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢀꢉꢌꢄ"&&ꢁꢁꢄꢄꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢃꢌ

ꢊꢉ

ꢀꢌ

ꢉ

ꢉꢏꢀ

ꢉꢏꢂ

ꢉꢏꢊ

ꢉꢏꢃ

ꢉꢏꢌ

ꢉꢏꢆ

9

ꢄꢐ9ꢑ

2/

Conditions: V_DD= 3.3 V and V_DD= 1.8 V; on pins PIO0_10 and PIO0_11.

Fig 23. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus

LOW-level output voltage V_OL

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

43 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

DDDꢀꢁꢁꢃꢇꢂꢇ

ꢀꢌ

ꢀꢂ

ꢎ

ꢇꢃꢉꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢂꢌꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢅꢌꢄ¡&&ꢁꢁꢄꢄꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢀꢉꢌꢄ¡&&ꢁꢁꢄꢄꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢇꢃꢉꢄ¡&&ꢁꢁꢀꢊꢏꢏꢅꢊꢄꢄ99

ꢂꢌꢄ¡&&ꢁꢁꢀꢊꢏꢏꢅꢊꢄꢄ99

ꢅꢌꢄ¡&&ꢁꢁꢄꢄꢀꢊꢏꢏꢅꢊꢄꢄ99

ꢀꢉꢌꢄ¡&&ꢁꢁꢄꢄꢀꢊꢏꢏꢅꢊꢄꢄ99

,2/

2/

ꢐP$ꢑ

ꢆ

ꢊ

ꢉ

ꢉꢏꢀ

ꢉꢏꢂ

ꢉꢏꢊ

ꢉꢏꢃ

ꢉꢏꢌ

ꢉꢏꢆ

9

ꢄꢐ9ꢑ

2/

Conditions: V_DD= 3.3 V and V_DD= 1.8 V; standard port pins and high-drive pins PIO0_2, PIO0_3,

PIO0_7, PIO0_12, PIO0_13.

Fig 24. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

DDDꢀꢁꢁꢃꢃꢈꢆ

ꢊꢏꢆ

92+

2+

ꢐ9ꢑ

ꢊꢏꢂ

9

ꢄ ꢄꢊꢏꢊꢄ9ꢒ

''

7ꢄ ꢄꢄꢇꢃꢉꢄ&

7ꢄ ꢄꢂꢌꢄ&

7ꢄ ꢄꢅꢌꢄ&

7ꢄ ꢄꢀꢉꢌꢄ&

ꢂꢏꢅ

ꢂꢏꢃ

ꢂ

9

ꢄ ꢄꢀꢏꢅꢄ9ꢒ

''

7ꢄ ꢄꢄꢇꢃꢉꢄ&

7ꢄ ꢄꢂꢌꢄ&

7ꢄ ꢄꢅꢌꢄ&

7ꢄ ꢄꢀꢉꢌꢄ&

ꢀꢏꢆ

ꢀꢏꢂ

ꢉ

ꢊ

ꢆ

ꢎ

ꢀꢂ

ꢀꢌ

ꢀꢅ

ꢂꢀ

,

ꢄꢐP$ꢑ

2+

Conditions: V_DD= 3.3 V and V_DD= 1.8 V; standard port pins.

Fig 25. Typical HIGH-level output voltage V_OHversus HIGH-level output source current

I_OH

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

44 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

DDDꢀꢁꢁꢃꢇꢇꢅ

ꢉꢏꢉꢀ

,SX

SX

9

ꢄ ꢄꢀꢏꢅꢄ9

''

ꢐP$ꢑ

ꢉ

ꢀꢉꢌꢄꢄ¡&&

ꢎꢉꢄꢄ¡&&

ꢅꢌꢄꢄ¡&&

ꢂꢌꢄꢄ¡&&

ꢇꢃꢉꢄꢄ¡&&

ꢀꢉꢌꢄ¡&&

ꢎꢉꢄꢄ¡&&

ꢅꢌꢄꢄ¡&&

ꢂꢌꢄꢄ¡&&

ꢇꢃꢉꢄ¡&&

ꢇꢉꢏꢉꢂ

ꢇꢉꢏꢉꢊ

ꢇꢉꢏꢉꢃ

ꢇꢉꢏꢉꢆ

ꢇꢉꢏꢉꢍ

9

ꢄ ꢄꢊꢏꢊꢄ9

''

ꢉ

ꢀ

ꢂ

ꢊ

ꢃ

ꢌ

9 ꢄꢐ9ꢑ

,

Conditions: V_DD= 3.3 V and V_DD= 1.8 V; standard port pins.

Fig 26. Typical pull-up current I_puversus input voltage V_I

DDDꢀꢁꢁꢃꢇꢅꢉ

ꢉꢏꢉꢅ

ꢇꢃꢉꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢂꢌꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢅꢌꢄꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

ꢀꢉꢌꢄꢄ¡&&ꢁꢁꢊꢊꢏꢏꢊꢊꢄꢄ99

,3'

3'

ꢐP$ꢑ

ꢉꢏꢉꢆ

ꢉꢏꢉꢃ

ꢉꢏꢉꢂ

ꢉ

ꢇꢃꢉꢄꢄ¡&&ꢁꢁꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢂꢌꢄꢄꢄ¡&&ꢁꢁꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢅꢌꢄꢄꢄ¡&&ꢁꢁꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢀꢉꢌꢄꢄꢄ¡&&ꢁꢁꢀꢀꢏꢏꢅꢅꢄꢄ99

ꢉ

ꢀ

ꢂ

ꢊ

ꢃ

ꢌ

9 ꢄꢐ9ꢑ

,

Conditions: V_DD= 3.3 V and V_DD= 1.8 V; standard port pins.

Fig 27. Typical pull-down current I_pdversus input voltage V_I

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

45 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12. Dynamic characteristics

12.1 Flash memory

Table 11. Flash characteristics

_amb= 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

T

Symbol

N_endu

t_ret

Parameter

Conditions

Min

10000

10

Typ

100000

20

Max

Unit

[1]

endurance

-

cycles

years

ms

retention time

powered

-

unpowered

20

40

-

t_er

erase time

page or multiple

consecutivepages,

sector or multiple

consecutive

95

100

105

sectors

[2]

t_prog

programming

time

0.95

1

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 64 bytes to the flash. T_amb +85 C. Flash programming with IAP

calls (see LPC800 user manual).

12.2 External clock for the oscillator in slave mode

Remark: The input voltage on the XTAL1/2 pins must be  1.95 V (see Table 9). For

connecting the oscillator to the XTAL pins, also see Section 14.2.

Table 12. Dynamic characteristic: external clock (XTALIN inputs)

T_amb= 40 C to +105 C; V_DDover specified ranges.^[1]

Symbol

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk) 0.4

-

ns

T_cy(clk) 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

W

&+&;

W

&/&+

&+&/

&/&;

7

F\ꢐFONꢑ

DDDꢀꢁꢁꢄꢅꢄꢇ

Fig 28. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

46 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.3 Internal oscillators

Table 13. Dynamic characteristics: IRC

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V^[1]

.

Symbol

Parameter

Conditions

Min

Typ^[2]Max

12 12.18

Unit

f_osc(RC)

internal RC oscillator

frequency

T_amb= 40 C to

+105 C

11.82

MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

DDDꢀꢁꢁꢃꢈꢃꢂ

ꢀꢂꢏꢀꢂ

I

ꢐ0+]ꢑ

ꢀꢂꢏꢉꢅ

ꢊꢏꢆꢄ9

ꢊꢏꢊꢄ9

ꢊꢏꢉꢄ9

ꢂꢏꢍꢄ9

ꢂꢏꢃꢄ9

ꢂꢏꢀꢄ9

ꢀꢏꢅꢄ9

ꢀꢂꢏꢉꢃ

ꢀꢂ

ꢀꢀꢏꢎꢆ

ꢀꢀꢏꢎꢂ

ꢀꢀꢏꢅꢅ

ꢇꢃꢉ

ꢇꢀꢉ

ꢂꢉ

ꢌꢉ

ꢅꢉ

ꢀꢀꢉ

WHPSHUDWXUHꢄꢐ&ꢑ

Conditions: Frequency values are typical values. 12 MHz  1.5 % accuracy is guaranteed for

2.7 V  V_DD 3.6 V and T_amb= 40 C to +105 C. Variations between parts may cause the IRC to

fall outside the 12 MHz  1.5 % accuracy specification for voltages below 2.7 V.

Fig 29. Typical Internal RC oscillator frequency versus temperature

Table 14. Dynamic characteristics: Watchdog oscillator

Symbol

Parameter

Conditions

Min Typ^[1]Max Unit

[2][3]

f_osc(int)

internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1

-

9.4

-

kHz

frequency

in the WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register

-

2300

-

kHz

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +105 C) is 40 %.

[3] See the LPC81xM user manual.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

47 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.4 I/O pins

Table 15. Dynamic characteristics: I/O pins^[1]

T_amb= 40 C to +105 C; 3.0 V  V_DD 3.6 V.

Symbol Parameter Conditions

Min

3.0

2.5

Typ

Max

5.0

Unit

ns

t_r

t_f

rise time

fall time

pin configured as output

-

5.0

ns

[1] Applies to standard port pins and RESET pin.

12.5 I²C-bus

Table 16. Dynamic characteristic: I²C-bus pins^[1]

T_amb= 40 C to +105 C.^[2]

Symbol

Parameter

Conditions

Standard-mode

Fast-mode

Min

Max

Unit

kHz

MHz

f_SCL

SCL clock

frequency

0

100

400

1

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

[4][5][6][7]

t_f

fall time

of both SDA and

SCL signals

-

300

ns

Standard-mode

Fast-mode

20 + 0.1  C_b300

ns

Fast-mode Plus;

on pins PIO0_10

and PIO0_11

-

120

t_LOW

LOW period of

the SCL clock

Standard-mode

Fast-mode

4.7

1.3

-

s

Fast-mode Plus; on 0.5

pins PIO0_10 and

PIO0_11

t_HIGH

HIGH period of

the SCL clock

Standard-mode

Fast-mode

4.0

0.6

-

s

Fast-mode Plus; on 0.26

pins PIO0_10 and

PIO0_11

[3][4][8]

t_HD;DAT

data hold time

Standard-mode

Fast-mode

0

-

s

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

[9][10]

t_SU;DAT

data set-up

time

Standard-mode

Fast-mode

250

100

-

ns

Fast-mode Plus; on 50

pins PIO0_10 and

PIO0_11

[1] See the I²C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

48 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

[3] t_HD;DATis the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

V_IH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF.

[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage t_fis specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of t_VD;DATor t_VD;ACKby a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (t_LOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9]

t_SU;DATis the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement

_SU;DAT= 250 ns must then be met. This will automatically be the case if the device does not stretch the

t

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

W

I

W

68ꢒ'$7

ꢍꢉꢄꢔ

ꢊꢉꢄꢔ

ꢍꢉꢄꢔ

ꢊꢉꢄꢔ

6'$

6&/

W

+'ꢒ'$7

9'ꢒ'$7

W

I

W

+,*+

ꢍꢉꢄꢔ

ꢊꢉꢄꢔ

ꢍꢉꢄꢔ

ꢊꢉꢄꢔ

ꢍꢉꢄꢔ

ꢊꢉꢄꢔ

ꢍꢉꢄꢔ

ꢊꢉꢄꢔ

W

/2:

ꢀꢄꢁꢄI

6

6&/

DDDꢀꢁꢁꢄꢅꢄꢆ

Fig 30. I²C-bus pins clock timing

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

49 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.6 SPI interfaces

The maximum data bit rate is 30 Mbit/s in master mode and 25 Mbit/s in slave mode.

Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for

all digital pins except the open-drain pins PIO0_10 and PIO0_11.

Table 17. SPI dynamic characteristics

T_amb= 40 C to 105 C; 1.8 V  V_DD 3.6 V. Simulated parameters sampled at the 50 % level of

the rising or falling edge; values guaranteed by design.

Symbol

SPI master^[1]

T_cy(clk)

t_DS

Parameter

Conditions

Min

Max

Unit

[2]

clock cycle time

33

0

-

ns

data set-up time

data hold time

-

t_DH

16

-

t_v(Q)

data output valid time

data output hold time

C_L= 10 pF

0.5

-

t_h(Q)

0.5

SPI slave

T_cy(clk)

t_DS

40

0

ns

data set-up time

-

t_DH

data hold time

16

-

t_v(Q)

data output valid time

data output hold time

C_L= 10 pF

10

-

t_h(Q)

10

[1] Capacitance on pin SPIn_SCK C_SCK< 5 pF.

[2] _cy(clk)= DIVVAL/CCLK with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the

LPC800 User manual UM10601.

T

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

50 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

7

F\ꢐFONꢑ

6&.ꢄꢐ&32/ꢄ ꢄꢉꢑ

6&.ꢄꢐ&32/ꢄ ꢄꢀꢑ

026,

W

Kꢐ4ꢑ

Yꢐ4ꢑ

'$7$ꢄ9$/,'

&3+$ꢄ ꢄꢀ

W

'+

'6

'$7$ꢄ9$/,'

0,62

W

Kꢐ4ꢑ

Yꢐ4ꢑ

'$7$ꢄ9$/,'

W

026,

0,62

W

&3+$ꢄ ꢄꢉ

'6

'+

'$7$ꢄ9$/,'

DDDꢀꢁꢁꢄꢅꢄꢄ

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 31. SPI master timing

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

51 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

7

F\ꢐFONꢑ

6&.ꢄꢐ&32/ꢄ ꢄꢉꢑ

6&.ꢄꢐ&32/ꢄ ꢄꢀꢑ

W

'+

'6

026,

0,62

'$7$ꢄ9$/,'

W

Kꢐ4ꢑ

Yꢐ4ꢑ

&3+$ꢄ ꢄꢀ

'$7$ꢄ9$/,'

W

'+

'6

026,

0,62

'$7$ꢄ9$/,'

W

Kꢐ4ꢑ

&3+$ꢄ ꢄꢉ

Yꢐ4ꢑ

'$7$ꢄ9$/,'

DDDꢀꢁꢁꢄꢅꢄꢂ

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 32. SPI slave timing

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

52 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.7 USART interface

The maximum USART bit rate is 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode slave and master mode.

Remark: USART functions can be assigned to all digital pins. The characteristics are valid

for all digital pins except the open-drain pins PIO0_10 and PIO0_11.

Table 18. USART dynamic characteristics

T_amb= 40 C to 105 C; 1.8 V  V_DD 3.6 V. Simulated parameters sampled at the 50 % level of

the falling or rising edge; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Max

Unit

[2]

T_cy(clk)

clock cycle time

100

-

ns

USART master (in synchronous mode)^[3]

t_su(D)

data input set-up

time

44

-

ns

t_h(D)

t_v(Q)

t_h(Q)

data input hold time

data output valid time

data output hold time

0

-

ns

-8

-

-8

USART slave (in synchronous mode)

t_su(D)

data input set-up

time

5

-

ns

t_h(D)

t_v(Q)

t_h(Q)

data input hold time

0

-

ns

data output valid time C_L= 10 pF

data output hold time C_L= 10 pF

-

40

-

40

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), V_DD= 3.3 V, typical

samples.

[2] T_cy(clk)= U_PCLK/BRGVAL. See the LPC800 User manual UM10601.

[3] Capacitance on pin Un_SCLK C_SCLK< 5 pF.

7

F\ꢐFONꢑ

8QB6&/.ꢄꢐ&/.32/ꢄ ꢄꢉꢑ

8QB6&/.ꢄꢐ&/.32/ꢄ ꢄꢀꢑ

7;'

W

Kꢐ4ꢑ

Yꢐ4ꢑ

67$57

%,7ꢉ

%,7ꢀ

W

VXꢐ'ꢑ Kꢐ'ꢑ

%,7ꢀ

67$57

%,7ꢉ

5;'

DDDꢀꢁꢁꢃꢁꢁꢉ

Fig 33. USART timing

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

53 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

13. Analog characteristics

13.1 BOD

Table 19. BOD static characteristics^[1]

T_amb= 40 C to +105 C.

Symbol

Parameter

Conditions

interrupt level 1

assertion

Typ^[2]

Unit

V_th

threshold voltage

2.3

2.4

V

de-assertion

interrupt level 2

assertion

2.6

2.7

V

de-assertion

interrupt level 3

assertion

2.8

2.9

V

de-assertion

reset level 1

assertion

2.1

2.2

V

de-assertion

reset level 2

assertion

2.4

2.5

V

de-assertion

reset level 3

assertion

2.6

2.8

V

de-assertion

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), V_DD= 3.3 V, typical

samples.

13.2 Internal voltage reference

Table 20. Internal voltage reference static and dynamic characteristics

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V

[1]

[2]

[4]

[2]

[3]

V_O

output voltage T_amb= 40 C to +105 C

T_amb= 70 C to 105 C

T_amb= 50 C

0.855 0.900

0.945

-

0.906

0.905

-

V

-

V

T_amb= 25 C

0.893 0.903

0.913

V

T_amb= 0 C

-

0.902

0.899

0.896

155

-

V

T_amb= 20 C

-

V

T_amb= 40 C

-

V

t_s(pu)

power-up

to 99% of V_O

195

s

settling time

[1] Characterized through simulation.

[2] Characterized on a typical silicon sample.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

54 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

[3] Typical values are derived from nominal simulation (V_DD= 3.3 V; T_amb= 27 C; nominal process models).

Maximum values are derived from worst case simulation (V_DD= 2.6 V; T_amb= 105 C; slow process

models).

[4] Maximum and minimum values are measured on samples from the corners of the process matrix lot.

DDDꢀꢁꢁꢃꢈꢉꢆ

ꢎꢀꢉ

92

2

ꢐP9ꢑ

ꢎꢉꢌ

ꢎꢉꢉ

ꢅꢎꢌ

ꢅꢎꢉ

ꢇꢃꢉ

ꢇꢀꢌ

ꢀꢉ

ꢊꢌ

ꢆꢉ

ꢅꢌ

ꢀꢀꢉ

WHPSHUDWXUHꢄꢐ&ꢑ

V_DD= 3.3 V

Fig 34. Typical internal voltage reference output voltage

13.3 Comparator

Table 21. Comparator characteristics

V_DD= 3.0 V and T_amb= 27 C unless noted otherwise.

Symbol

Parameter

Conditions

Min Typ

Max

Unit

Static characteristics

V_ref(cmp)

comparator reference

voltage

pin PIO0_6/VDDCMP configured for

function VDDCMP

1.5

-

3.6

V

I_DD

V_IC

supply current

-

55

-

A

common-mode input

voltage

0

V_DD

V

DV_O

output voltage variation

offset voltage

0

-

V_DD

V

V_offset

V_IC= 0.1 V

V_IC= 1.5 V

V_IC= 2.8 V

1.9

2.1

2.0

-

mV

-

Dynamic characteristics

t_startup

start-up time

nominal process

-

4

-

s

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

55 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 21. Comparator characteristics …continued

V_DD= 3.0 V and T_amb= 27 C unless noted otherwise.

Symbol

Parameter

Conditions

Min Typ

Max

Unit

t_PD

propagation delay

HIGH to LOW; V_DD= 3.0 V;

-

109

121

[1]

V

_IC= 0.1 V; 50 mV overdrive input

ns

V_IC= 0.1 V; rail-to-rail input

V_IC= 1.5 V; 50 mV overdrive input

V_IC= 1.5 V; rail-to-rail input

-

155

95

164

105

108

129

82

101

122

74

V_IC= 2.9 V; 50 mV overdrive input

V_IC= 2.9 V; rail-to-rail input

t_PD

propagation delay

LOW to HIGH; V_DD= 3.0 V;

246

260

[1]

[2]

V

_IC= 0.1 V; 50 mV overdrive input

_IC= 0.1 V; rail-to-rail input

ns

mV

V

-

57

59

V_IC= 1.5 V; 50 mV overdrive input

V_IC= 1.5 V; rail-to-rail input

218

146

155

206

286

-

V_IC= 2.9 V; 50 mV overdrive input

V_IC= 2.9 V; rail-to-rail input

184

250

V_hys

R_lad

hysteresis voltage

ladder resistance

positive hysteresis; V_DD= 3.0 V;

V_IC= 1.5 V

6, 11, 21

negative hysteresis; V_DD= 3.0 V;

V_IC= 1.5 V

[2]^[2]

-

4, 9, 19

1.034

-

mV

-

M

[1] C_L= 10 pF; results from measurements on silicon samples over process corners and over the full temperature range T_amb= 40 C to

+105 C. Typical data are for T_amb= 27 C.

[2] Input hysteresis is relative to the reference input channel and is software programmable to three levels.

Table 22. Comparator voltage ladder dynamic characteristics

Symbol Parameter

t_s(pu)power-up settling

Conditions

Min Typ

Max

Unit

[1]

to 99% of voltage

ladder output

value

-

30

s

time

[1]

[2]

t_s(sw)

switching settling

time

to 99% of voltage

ladder output

value

-

15

s

[1] Maximum values are derived from worst case simulation (V_DD= 2.6 V; T_amb= 105 C; slow process

models).

[2] Settling time applies to switching between comparator channels.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

56 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 23. Comparator voltage ladder reference static characteristics

V_DD= 3.3 V; T_amb= 40 C to + 105C.

Symbol

Parameter

Conditions

Min

Typ

Max[1] Unit

E_V(O)

output voltage error

Internal V_DDsupply

decimal code = 00

decimal code = 08

decimal code = 16

decimal code = 24

decimal code = 30

decimal code = 31

[2]

-

0

%

0

0.4

0.2

0.1

0.2

0.1

E_V(O)

output voltage error

External VDDCMP

supply

decimal code = 00

decimal code = 08

decimal code = 16

decimal code = 24

decimal code = 30

decimal code = 31

-

0

%

0.1

0.2

0.1

0.5

0.4

0.3

0.2

0.1

[1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V.

[2] All peripherals except comparator and IRC turned off.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

57 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

14. Application information

14.1 Typical wake-up times

Table 24. Typical wake-up times (3.3 V, Temp = 25 °C)

Power modes

V_DDcurrent

0.7 mA

Wake-up time

2.6 s

Sleep mode (12 MHz)^[1][2]

Deep-sleep mode^[1][3]

Power-down mode^[1][3]

Deep Power-down mode^[4]

150 A

4 s

0.9 A

50 s

170 nA

215 s

[1] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler.

[2] IRC enabled, all peripherals off.

[3] Watchdog oscillator disabled, Brown-Out Detect (BOD) disabled.

[4] Self wakeup-timer disabled. Wake-up from deep power-down causes the LPC800 to go through entire reset

process. The wake-up time measured is the time between when a wake-up pin is triggered to wake the

device up from the low power modes and from when a GPIO output pin is set in the reset handler.

14.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave

mode, a minimum of 200 mV(RMS) is needed.

/3&ꢃꢁꢁ

;7$/,1

&

L

&

J

ꢀꢉꢉꢄS)

DDDꢀꢁꢁꢄꢅꢄꢅ

Fig 35. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(Figure 35), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 36 and in

Table 25 and Table 26. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C_X1and C_X2need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, C_Land

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

58 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

R_S). Capacitance C_Pin Figure 36 represents the parallel package capacitance and should

not be larger than 7 pF. Parameters F_OSC, C_L, R_Sand C_Pare supplied by the crystal

manufacturer (see Table 25).

/3&ꢃꢁꢁ

/

;7$/,1

;7$/287

&

3

/

;7$/

5

6

&

;ꢀ

;ꢂ

DDDꢀꢁꢁꢄꢅꢄꢃ

Fig 36. Oscillator modes and models: oscillation mode of operation and external crystal

model used for C_X1/C_X2evaluation

Table 25. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

1 MHz to 5 MHz

10 pF

< 300 

< 200 

< 100 

< 160 

< 60 

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

20 pF

30 pF

5 MHz to 10 MHz

10 pF

20 pF

30 pF

10 MHz to 15 MHz

15 MHz to 20 MHz

10 pF

20 pF

10 pF

< 80 

Table 26. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

15 MHz to 20 MHz

10 pF

< 180 

< 100 

< 160 

< 80 

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

20 pF

20 MHz to 25 MHz

10 pF

20 pF

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

59 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

14.3 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1,C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_x1and C_x2should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

60 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

15. Package outline

DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-2

D

M

E

A

2

A

1

L

e

w

Z

b

1

(e )

1

M

H

b

2

8

5

pin 1 index

E

1

4

0

2.5

5 mm

scale

Dimensions (inch dimensions are derived from the original dimensions)

(1)

Unit

A

2

b

2

c

D

E

e

1

L

M

H

w

Z

1

E

max 4.2

3.43 1.73 0.53 1.07 0.38 9.8 6.48

3.60 7.88 9.40

1.15

mm nom

min

2.54 7.62

0.254

0.51

0.02

1.14 0.38 0.89 0.20 9.2 6.20

3.05 7.62 7.88

0.14 0.31 0.37

max 0.17

inches nom

min

0.14 0.068 0.021 0.042 0.015 0.39 0.26

0.045

0.1

0.01

0.045 0.015 0.035 0.008 0.36 0.24

0.3 0.12 0.30 0.31

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included

sot097-2_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

JEITA

- - -

10-10-15

10-10-18

SOT97-2

MO-001

Fig 37. Package outline SOT097-2 (DIP8)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

61 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 38. Package outline SOT403-1 (TSSOP16)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

62 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 39. Package outline SOT163-1 (SO20)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

63 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 40. Package outline SOT360-1 (TSSOP20)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

64 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

XSON16: plastic extremely thin small outline package; no leads; 16 terminals; body 2.5 x 3.2 x 0.5 mm

SOT1341-1

X

D

B

A

E

A

1

c

detail X

terminal 1

index area

e

1

C

v

C

A

B

terminal 1

index area

y

e

b

C

1

w

1

8

L

1

k

L

16

9

0

1

2

3 mm

scale

Dimensions (mm are the original dimensions)

(1)

Unit

A

b

c

D

E

e

k

L

1

v

w

y

1

max 0.5 0.05 0.25 0.152 3.3 2.6

0.9 1.0

mm nom

min

0.20

3.2 2.5

0.4

2.8

0.8 0.9 0.1 0.05 0.05 0.05

0.7 0.8

0.00 0.15 0.050 3.1 2.4

0.2

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot1341-1_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

JEITA

- - -

12-09-05

13-02-13

SOT1341-1

MO-252

Fig 41. Package outline SOT1341-1 (XSON16)

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

65 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

16. Soldering

Footprint information for reflow soldering of TSSOP16 package

SOT403-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450

sot403-1_fr

Fig 42. Reflow soldering of the TSSOP16 package

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

66 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

13.40

0.60 (20×)

1.50

8.00 11.00 11.40

1.27 (18×)

solder lands

sot163-1_fr

occupied area

placement accuracy 0.25

Dimensions in mm

Fig 43. Reflow soldering of the SO20 package

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

67 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Footprint information for reflow soldering of TSSOP20 package

SOT360-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450

sot360-1_fr

Fig 44. Reflow soldering of the TSSOP20 package

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

68 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

)RRWSULQWꢉLQIRUPDWLRQꢉIRUꢉUHIORZꢉVROGHULQJꢉRIꢉ;621ꢄꢅꢉSDFNDJHꢉ

627ꢄꢇꢈꢄꢀꢄ

ꢊꢏꢌ

ꢊꢏꢀꢂ

ꢊꢏꢉꢂ

ꢉꢏꢃ

ꢉꢏꢂꢂ

ꢉꢏꢀꢅ

ꢀꢏꢀꢍ ꢀꢏꢉꢍ

ꢊꢏꢀꢃ

ꢉꢏꢍ

RFFXSLHGꢄDUHD

VROGHUꢄUHVLVW

VROGHUꢄSDVWH

VROGHUꢄODQGV

'LPHQVLRQVꢄLQꢄPP

ꢀꢃꢇꢉꢂꢇꢂꢅ

,VVXHꢄGDWH

VRWꢉꢆꢄꢉꢀꢉBIU

ꢀꢃꢇꢉꢊꢇꢉꢍ

Fig 45. Reflow soldering of the XSON16 package

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

69 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

17. Abbreviations

Table 27. Abbreviations

Acronym

AHB

Description

Advanced High-performance Bus

Advanced Peripheral Bus

BrownOut Detection

APB

BOD

GPIO

PLL

General-Purpose Input/Output

Phase-Locked Loop

RC

Resistor-Capacitor

SPI

Serial Peripheral Interface

System Management Bus

Transverse ElectroMagnetic

SMBus

TEM

UART

Universal Asynchronous Receiver/Transmitter

18. References

[1] I2C-bus specification UM10204.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

70 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

19. Revision history

Table 28. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC81XM v.4.3

20140422

Product data sheet

-

LPC81XM v.4.2

Modifications:

• Section 8.20.2 “Clock input” updated for clarity.

• CLKIN signal removed from Table 12 “Dynamic characteristic: external clock (XTALIN

inputs)”.

• Name “SCT” changed to “SCTimer/PWM” for clarity.

• Remove slew rate control from GPIO features for clarity.

• MRT bus stall mode added.

• WWDT clock source corrected in Section 8.17.1.

• Pin description table updated for clarification (I2C-bus pins, WAKEUP, RESET).

• Added reflow solder diagram and thermal resistance numbers for XSON16

(SOT1341-1).

• Table 21: Added V_ref(cmp)spec for PIO0_6/VDDCMP.

LPC81XM v.4.2

Modifications:

LPC81XM v.4.1

Modifications:

LPC81XM v.4

Modifications:

20131210

Corrected vertical axis marker in Figure 21 “CoreMark score”.

20131112 Product data sheet LPC81XM v.4

• Corrected XSON16 pin information in Figure 6 and Table 4.

Product data sheet

-

LPC81XM v.4.1

-

20131025

Product data sheet

-

LPC81XM v.3.1

• Added Section 14.1 “Typical wake-up times”.

• Added LPC812M101JTB16 and XSON16 package.

LPC81XM v.3.1

Modifications:

20130916

Product data sheet

-

LPC81XM v.3

• Correct the pin interrupt features: Pin interrupts can wake up the part from Sleep

mode, Deep-sleep mode, and Power-down mode. See Section 8.11.1.

• Table 9 “Static characteristics”: Updated power numbers for Deep-sleep, Power-down,

and Deep power-down.

• Added 30 MHz data to Figure 13 “Active mode: Typical supply current IDD versus

supply voltage VDD”, Figure 14 “Active mode: Typical supply current IDD versus

temperature”, and Figure 15 “Sleep mode: Typical supply current IDD versus

temperature for different system clock frequencies”.

LPC81XM v.3

20130729

Product data sheet

-

LPC81XM v.2.1

• Operating temperature range changed to 40 °C to 105 °C.

• Type numbers updated to reflect the new operating temperature range. See Table 1

“Ordering information” and Table 2 “Ordering options”.

• ISP entry pin moved from PIO0_1 to PIO0_12 for TSSOP, and SSOP packages. See

Table 4 and Table 6.

• Propagation delay values updated in Table 21 “Comparator characteristics”.

• SPI characteristics updated. See Section 12.6.

• IRC characteristics updated. See Section 12.3.

• CoreMark data updated. See Figure 19 and Figure 20.

• IRC frequency changed to 12 MHz +/- 1.5 %. See Table 13.

• Data sheet status updated to Product data sheet.

LPC81XM v.2.1

20130325

Preliminary data sheet -

LPC81XM v.2

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

71 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 28. Revision history …continued

Document ID

Release date

Data sheet status

Change notice Supersedes

• Editorial updates (temperature sensor removed).

• CoreMark data added. See Figure 19 “Active mode: CoreMark power consumption

IDD” and Figure 20 “CoreMark score”.

• I_DDin Deep power-down mode added for condition Low-power oscillator on/WKT

wake-up enabled. See Table 10.

• Table note 3 updated for Table 4 “Pin description table (fixed pins)”.

• Conditions for t_erand t_progupdated in Table 12 “Flash characteristics”.

• Section 13.3 “Internal voltage reference” added.

• Typical timing data added for SPI. See Section 12.6.

• Typical timing data added for USART in synchronous mode. See Section 12.7.

• BOD characterization added. See Section 13.1.

• IRC characterization added. See Section 12.3.

• Internal voltage reference characteristics added. See Section 13.3.

• Data sheet status changed to Preliminary data sheet.

LPC81XM v.2

Modifications:

20130128

Objective data sheet

-

LPC81XM v.1

• MTB memory space changed to 1 kB in Figure 6.

• Electrical pin characteristics added in Table 10.

• Figure 11 “Connecting the SWD pins to a standard SWD connector” added.

• Peripheral power consumption added in Table 11.

• Table 7 updated.

• MRT implementation changed to 31-bit timer.

• Power consumption data in active and sleep mode with IRC added. See Figure 13 to

Figure 15.

• Power consumption (parameter I_DD) in active and sleep mode for low-power mode at

12 MHz corrected in Table 10.

• Power consumption (parameter I_DD) in active and sleep mode at 24 MHz added in

Table 10.

• Maximum USART speed in synchronous mode changed to 10 Mbit/s.

• Section 5 “Marking” added.

LPC81XM v.1

20121112

Objective data sheet

-

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

72 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

20.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

73 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

20.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

74 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

22. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.20.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 25

8.20.1.2 Crystal Oscillator (SysOsc) . . . . . . . . . . . . . . 25

8.20.1.3 Internal Low-power Oscillator and Watchdog

Oscillator (WDOsc) . . . . . . . . . . . . . . . . . . . . 25

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

4

4.1

5

8.20.2

8.20.3

8.20.4

8.20.5

8.20.6

Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 26

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26

Power control. . . . . . . . . . . . . . . . . . . . . . . . . 26

6

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

8.20.6.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 26

8.20.6.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.20.6.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27

8.20.6.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 27

8.20.6.5 Deep power-down mode . . . . . . . . . . . . . . . . 27

8

8.1

8.2

8.3

8.4

8.5

8.5.1

8.5.2

8.6

8.7

8.8

8.8.1

8.9

8.10

8.10.1

8.11

8.11.1

8.12

8.12.1

8.13

8.13.1

8.14

8.14.1

8.15

Functional description . . . . . . . . . . . . . . . . . . 13

ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . 13

On-chip flash program memory . . . . . . . . . . . 13

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 13

On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 13

Nested Vectored Interrupt Controller (NVIC) . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13

System tick timer . . . . . . . . . . . . . . . . . . . . . . 14

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14

I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 15

Standard I/O pad configuration. . . . . . . . . . . . 16

Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 17

Fast General-Purpose parallel I/O (GPIO) . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pin interrupt/pattern match engine . . . . . . . . . 18

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

State-Configurable Timer/PWM

(SCTimer/PWM) . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Windowed WatchDog Timer (WWDT) . . . . . . 21

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Self Wake-up Timer (WKT). . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Analog comparator (ACMP) . . . . . . . . . . . . . . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clocking and power control . . . . . . . . . . . . . . 24

Crystal and internal oscillators . . . . . . . . . . . . 24

8.21

System control . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Brownout detection . . . . . . . . . . . . . . . . . . . . 28

Code security (Code Read Protection - CRP) 29

APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 29

AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Emulation and debugging . . . . . . . . . . . . . . . 30

8.21.1

8.21.2

8.21.3

8.21.4

8.21.5

8.22

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31

Thermal characteristics . . . . . . . . . . . . . . . . . 32

10

11

Static characteristics . . . . . . . . . . . . . . . . . . . 33

Power consumption . . . . . . . . . . . . . . . . . . . . 37

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 41

Peripheral power consumption . . . . . . . . . . . 42

Electrical pin characteristics. . . . . . . . . . . . . . 43

11.1

11.2

11.3

11.4

12

Dynamic characteristics. . . . . . . . . . . . . . . . . 46

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46

External clock for the oscillator in slave mode 46

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

I²C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 50

USART interface . . . . . . . . . . . . . . . . . . . . . . 53

12.1

12.2

12.3

12.4

12.5

12.6

12.7

8.15.1

8.16

8.16.1

8.17

8.17.1

8.18

8.18.1

8.19

13

Analog characteristics . . . . . . . . . . . . . . . . . . 54

BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Internal voltage reference . . . . . . . . . . . . . . . 54

Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 55

13.1

13.2

13.3

14

Application information . . . . . . . . . . . . . . . . . 58

Typical wake-up times . . . . . . . . . . . . . . . . . . 58

XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

XTAL Printed Circuit Board (PCB) layout

14.1

14.2

14.3

8.19.1

8.20

8.20.1

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

15

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 61

continued >>

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.3 — 22 April 2014

75 of 76

LPC81xM

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

16

17

18

19

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 70

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 71

20

Legal information. . . . . . . . . . . . . . . . . . . . . . . 73

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 73

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 74

20.1

20.2

20.3

20.4

21

22

Contact information. . . . . . . . . . . . . . . . . . . . . 74

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 April 2014

Document identifier: LPC81XM