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A6275  
8-Bit Serial Input Constant-Current Latched LED Driver  
Last Time Buy  
This part is in production but has been determined to be  
LAST TIME BUY. This classification indicates that the product is  
obsolete and notice has been given. Sale of this device is currently  
restricted to existing customer applications. The device should not be  
purchased for new design applications because of obsolescence in the  
near future. Samples are no longer available.  
Date of status change: November 1, 2010  
Deadline for receipt of LAST TIME BUY orders: April 30, 2011  
Recommended Substitutions:  
For existing customer transition, and for new customers or new appli-  
cations, refer to the A6279.  
NOTE: For detailed information on purchasing options, contact your  
local Allegro field applications engineer or sales representative.  
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan  
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The  
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-  
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.  
A6275  
8-Bit Serial Input Constant-Current Latched LED Driver  
Features and Benefits  
Description  
▪ Up to 90 mA constant-current outputs  
▪ Undervoltage lockout  
TheA6275isspecificallydesignedforLEDdisplayapplications.  
Each BiCMOS device includes an 8-bit CMOS shift register,  
accompanying data latches, and eight NPN constant-current  
sink drivers.  
▪ Low-power CMOS logic and latches  
▪ High data-input rate  
▪ Pin-compatible with TB62705CP  
The CMOS shift register and latches allow direct interfacing  
with microprocessor-based systems. With a 5 V logic supply,  
typicalserialdata-inputratesareupto20MHz.TheLEDdrive  
current is determined by the user selection of a single resistor.  
A CMOS serial data output permits cascade connections in  
applications requiring additional drive lines. For inter-digit  
blanking, all output drivers can be disabled with an ENABLE  
input high. A similar 150 mA output device is available as the  
A6277; a similar 16-bit device is available as the A6276.  
Packages  
Two package styles are provided: a through-hole DIP (suffix  
A) and a surface-mount SOICW (suffix LW). Under normal  
applications,copperleadframesandlowlogic-powerdissipation  
allow these devices to sink maximum rated current through  
all outputs continuously over the operating temperature range  
16-pin DIP  
(A package)  
(90 mA, 0.9 V drop, 85°C). Both packages are lead (Pb) free,  
with 100% matte tin leadframe plating.  
16-pin SOICW  
(LW package)  
Not to scale  
Functional Block Diagram  
V
DD  
LOGIC  
UVLO  
SUPPLY  
CLOCK  
SERIAL  
DATA IN  
SERIAL  
DATA OUT  
SERIAL-PARALLEL SHIFT REGISTER  
LATCHES  
LATCH  
ENABLE  
OUTPUT ENABLE  
(ACTIVE LOW)  
GROUND  
MOS  
BIPOLAR  
R
I
EXT  
O
REGULATOR  
OUT OUT OUT  
OUT  
N
0
1
2
Dwg. FP-013-3  
26185.200F  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
Selection Guide  
Part Number  
A6275EA-T  
A6275ELWTR-T 16-pin SOICW  
A6275SLWTR-T 16-pin SOICW  
Ambient Temperature  
Package  
Packing  
(°C)  
16-pin DIP  
25 per tube  
–40 to 85  
1000 per reel  
1000 per reel  
–20 to 85  
Absolute Maximum Ratings*  
Characteristic  
Symbol  
VDD  
VI  
Notes  
Rating  
7.0  
Units  
V
Supply Voltage  
Input Voltage Range  
Output Voltage Range  
Output Current  
–0.4 to VDD + 0.4  
–0.5 to VDD + 17  
90  
V
VO  
V
IO  
mA  
mA  
ºC  
ºC  
ºC  
ºC  
Ground Current  
IGND  
750  
Range E  
Range S  
–40 to 85  
–20 to 85  
150  
Operating Ambient Temperature  
TA  
Maximum Junction Temperature  
Storage Temperature  
TJ(max)  
T
stg  
–55 to 150  
*These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static  
electrical charges.  
Thermal Characteristics may require derating at maximum conditions, see application information  
Characteristic  
Symbol  
Test Conditions*  
Value Units  
Package A, 4-layer PCB based on JEDEC standard  
38  
48  
ºC/W  
ºC/W  
Package Thermal Resistance  
RθJA  
Package LW, 4-layer PCB based on JEDEC standard  
*Additional thermal information available on the Allegro website.  
Power Dissipation versus Ambient Temperature  
3500  
3250  
3000  
2750  
2500  
2250  
2000  
1750  
1500  
1250  
1000  
750  
500  
250  
0
25  
50  
75  
100  
125  
150  
Temperature (°C)  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
2
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
V
DD  
V
DD  
IN  
IN  
Dwg. EP-010-12  
Dwg. EP-010-11  
OUTPUT ENABLE (active low)  
LATCH ENABLE  
V
V
DD  
DD  
OUT  
IN  
Dwg. EP-063-6  
Dwg. EP-010-13  
CLOCK and SERIAL DATA IN  
SERIAL DATA OUT  
TRUTH TABLE  
Serial  
Data Clock  
Input Input I  
Shift Register Contents  
Serial Latch  
Data Enable  
Output Input  
Latch Contents  
Output  
Enable  
Input  
Output Contents  
... I  
I
I
...  
I
I
I
I
I
...  
I
I
I
I
I
I
N-1 N  
1
2
3
N-1  
N
1
2
3
N-1  
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...  
...  
...  
...  
...  
R
R
R
X
R
R
R
R
X
1
1
2
2
2
3
N-2 N-1  
N-1  
N-1  
N
R
N-2 N-1  
X
R
X
R
X
1
N-1  
N-1  
N
N
L
R
R
R
...  
...  
...  
R
R
1
2
3
N-1  
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
P
P
... P  
... H  
P
H
1
2
3
N
1
2
3
N-1  
N
1
2
3
N-1  
N
X
H
H H H  
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
3
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).  
Limits  
Characteristic  
Symbol  
Test Conditions  
Min.  
Typ. Max.  
Unit  
Supply Voltage Range  
Undervoltage Lockout  
VDD  
VDD(UV)  
IO  
Operating  
4.5  
3.4  
5.0  
–
5.5  
4.0  
V
VDD = 0 → 5 V  
V
Output Current  
VCE = 0.7 V, REXT = 250 Ω  
64.2  
34.1  
75.5  
40.0  
86.8  
45.9  
mA  
mA  
(any single output)  
VCE = 0.7 V, REXT = 470 Ω  
Output Current Matching  
(difference between any  
∆IO  
0.4 V ≤ VCE(A) = VCE(B) ≤ 0.7 V:  
REXT = 250 Ω  
–
–
±1.5  
±1.5  
±6.0  
±6.0  
%
%
two outputs at same VCE  
)
REXT = 470 Ω  
Output Leakage Current  
Logic Input Voltage  
ICEX  
VIH  
VIL  
VOH = 15 V  
–
0.7VDD  
GND  
–
1.0  
–
5.0  
VDD  
0.3VDD  
0.4  
μA  
V
–
V
SERIAL DATA OUT  
Voltage  
VOL  
VOH  
RI  
IOL = 500 μA  
–
V
IOH = -500 μA  
4.6  
–
–
V
Input Resistance  
Supply Current  
ENABLE Input, Pull Up  
LATCH Input, Pull Down  
REXT = open, VOE = 5 V  
REXT = 470 Ω, VOE = 5 V  
REXT = 250 Ω, VOE = 5 V  
REXT = 470 Ω, VOE = 0 V  
REXT = 250 Ω, VOE = 0 V  
150  
100  
–
300  
200  
0.8  
6.0  
11  
10  
16  
600  
400  
1.4  
kΩ  
kΩ  
mA  
mA  
mA  
mA  
mA  
IDD(OFF)  
3.5  
8.0  
6.5  
15  
IDD(ON)  
5.0  
14  
8.0  
24  
Typical Data is at VDD = 5 V and is for design information only.  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
4
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,  
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.  
Limits  
Characteristic  
Symbol  
Test Conditions  
Min.  
Typ. Max.  
Unit  
Propagation Delay Time  
tpHL  
CLOCK-OUTn  
–
–
350  
350  
350  
40  
1000  
1000  
1000  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LATCH-OUTn  
ENABLE-OUTn  
–
CLOCK-SERIAL DATA OUT  
CLOCK-OUTn  
–
Propagation Delay Time  
tpLH  
–
300  
300  
300  
40  
1000  
1000  
1000  
–
LATCH-OUTn  
–
ENABLE-OUTn  
–
CLOCK-SERIAL DATA OUT  
90% to 10% voltage  
10% to 90% voltage  
–
Output Fall Time  
Output Rise Time  
tf  
tr  
150  
150  
350  
300  
1000  
600  
RECOMMENDED OPERATING CONDITIONS  
Characteristic  
Symbol  
Conditions  
Min.  
Typ. Max.  
Unit  
Supply Voltage  
Output Voltage  
Output Current  
VDD  
VO  
IO  
4.5  
5.0  
1.0  
–
5.5  
4.0  
V
V
–
Continuous, any one output  
SERIAL DATA OUT  
–
90  
mA  
mA  
mA  
V
IOH  
IOL  
VIH  
VIL  
fCK  
–
–
–
-1.0  
SERIAL DATA OUT  
–
1.0  
Logic Input Voltage  
Clock Frequency  
0.7VDD  
-0.3  
–
–
VDD + 0.3  
0.3VDD  
10  
–
V
Cascade operation  
–
MHz  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
5
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
TIMING REQUIREMENTS and SPECIFICATIONS  
(Logic Levels are VDD and Ground)  
C
50%  
B
CLOCK  
A
SERIAL  
DATA IN  
DATA  
50%  
t
p
SERIAL  
DATA OUT  
50%  
DATA  
D
E
LATCH  
ENABLE  
50%  
OUTPUT  
ENABLE  
LOW = ALL OUTPUTS ENABLED  
t
p
HIGH = OUTPUT OFF  
50%  
DATA  
LOW = OUTPUT ON  
Dwg. WP-029-1  
OUT  
N
A. Data Active Time Before Clock Pulse  
(Data Set-Up Time), tsu(D) ............................. 50 ns  
B. Data Active Time After Clock Pulse  
(Data Hold Time), th(D) ................................. 20 ns  
C. Clock Pulse Width, tw(CK) .................................. 50 ns  
D. Time Between Clock Activation  
and Latch Enable, tsu(L) ............................... 100 ns  
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns  
F. Output Enable Pulse Width, tw(OE) ................... 4.5 s  
HIGH = ALL OUTPUTS DISABLED (BLANKED)  
50%  
OUTPUT  
ENABLE  
t
F
pLH  
t
t
r
f
90%  
50%  
10%  
OUT  
N
DATA  
t
pHL  
NOTE: Timing is representative of a 10 MHz clock. Sig-  
nificantly higher speeds are attainable.  
Dwg. WP-030-1A  
Max. Clock Transition Time, tr or tf ....................... 10 s  
Serial data present at the input is transferred to the shift  
register on the logic 0-to-logic 1 transition of the CLOCK input  
pulse. On succeeding CLOCK pulses, the registers shift data in-  
formation towards the SERIAL DATA OUTPUT. The serial data  
must appear at the input prior to the rising edge of the CLOCK  
input waveform.  
Information present at any register is transferred to the  
respective latch when the LATCH ENABLE is high (serial-to-  
parallel conversion). The latches continue to accept new data as  
long as the LATCH ENABLE is held high. Applications where  
the latches are bypassed (LATCH ENABLE tied high) will  
require that the OUTPUT ENABLE input be high during serial  
data entry.  
When the OUTPUT ENABLE input is high, the output sink  
drivers are disabled (OFF). The information stored in the latches  
is not affected by the OUTPUT ENABLE input. With the OUT-  
PUT ENABLE input low, the outputs are controlled by the state  
of their respective latches.  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
6
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE  
A Package  
LW Package  
100  
80  
60  
40  
20  
100  
80  
V
CE = 2 V  
VCE = 1 V  
VCE = 2 V  
V
CE = 3 V  
VCE = 3 V  
V
CE = 4 V  
60  
VCE = 4 V  
40  
T
V
A
= +25°C  
DD = 5 V  
TA = +25°C  
VDD = 5 V  
R θJA = 94°C/W  
20  
0
R θJA = 60°C/W  
0
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
DUTY CYCLE IN PER CENT  
DUTY CYCLE IN PER CENT  
Dwg. GP-062-5  
Dwg. GP-062-4A  
100  
80  
100  
80  
V CE = 1 V  
VCE = 2 V  
V
CE = 2 V  
V
CE = 3 V  
VCE = 3 V  
V
CE = 4 V  
60  
60  
VCE = 4 V  
40  
40  
TA = +50°C  
T
V
A
= +50°C  
DD = 5 V  
VDD = 5 V  
JA = 94°C/W  
20  
20  
0
R
θ
R θJA = 60°C/W  
0
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
DUTY CYCLE IN PER CENT  
DUTY CYCLE IN PER CENT  
Dwg. GP-062-3  
Dwg. GP-062-2A  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
7
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)  
A Package  
LW Package  
100  
80  
100  
80  
V
CE = 0.7 V  
V
V
CE = 1 V  
CE = 2 V  
V
CE = 1 V  
V
CE = 2 V  
V
CE = 3 V  
60  
60  
V
CE = 3 V  
V
CE = 4 V  
V
CE = 4 V  
40  
40  
T
V
A
= +85°C  
DD = 5 V  
T
V
A
= +85°C  
DD = 5 V  
20  
20  
0
R θJA = 60°C/W  
R θJA = 94°C/W  
0
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
DUTY CYCLE IN PER CENT  
DUTY CYCLE IN PER CENT  
Dwg. GP-062-1  
Dwg. GP-062A  
TYPICAL CHARACTERISTICS  
60  
40  
20  
T A = +25°C  
R EXT = 500 Ω  
0
0
2.0  
0.5  
1.0  
1.5  
V CE IN VOLTS  
Dwg. GP-063  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
8
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
Pin-out Diagrams  
Package A  
Package LW  
LOGIC  
SUPPLY  
LOGIC  
SUPPLY  
V
V
GROUND  
1
2
3
4
16  
15  
14  
13  
12  
GROUND  
1
2
3
4
16  
15  
14  
13  
12  
DD  
DD  
SERIAL  
DATA IN  
I
SERIAL  
DATA IN  
I
O
O
R
R
EXT  
EXT  
REGULATOR  
REGULATOR  
SERIAL  
DATA OUT  
SERIAL  
DATA OUT  
CLOCK  
CK  
L
CLOCK  
CK  
L
LATCH  
ENABLE  
OUTPUT  
ENABLE  
LATCH  
ENABLE  
OUTPUT  
ENABLE  
OE  
OE  
REGISTER  
LATCHES  
REGISTER  
LATCHES  
OUT  
OUT  
OUT  
OUT  
OUT  
7
OUT  
OUT  
OUT  
OUT  
OUT  
7
5
6
5
6
0
1
2
3
0
1
2
3
11 OUT  
11 OUT  
6
6
10  
9
10  
9
OUT  
OUT  
OUT  
OUT  
7
8
7
8
5
4
5
4
TERMINAL DESCRIPTION  
Terminal No.  
Terminal Name  
Function  
GND  
Reference terminal for control logic.  
1
2
SERIAL DATA IN  
CLOCK  
Serial-data input to the shift-register.  
3
4
Clock input terminal for data shift on rising edge.  
LATCH ENABLE  
OUT0-7  
Data strobe input terminal; serial data is latched with high-level input.  
The eight current-sinking output terminals.  
5-12  
13  
OUTPUT ENABLE  
When (active) low, the output drivers are enabled; when high, all output driv-  
ers are turned OFF (blanked).  
14  
15  
SERIAL DATA OUT  
REXT  
CMOS serial-data output to the following shift-register.  
An external resistor at this terminal establishes the output current for all sink  
drivers.  
16  
SUPPLY  
(VDD) The logic supply voltage (typically 5 V).  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
9
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
Applications Information  
The load current per bit (IO) is set by the external resistor  
(REXT) as shown in the figure below.  
0.7 V per diode) for a group of drivers. If the available  
voltage source will cause unacceptable dissipation and  
series resistors or diode(s) are undesirable, a regulator  
such as the Sanken Series SAI or Series SI can be used to  
provide supply voltages as low as 3.3 V.  
100  
V
CE = 0.7 V  
80  
For reference, typical LED forward voltages are:  
White  
Blue  
Green  
Yellow  
Amber  
Red  
3.5 – 4.0 V  
3.0 – 4.0 V  
1.8 – 2.2 V  
2.0 – 2.1 V  
1.9 – 2.65 V  
1.6 – 2.25 V  
1.2 – 1.5 V  
60  
40  
Infrared  
20  
Pattern Layout. This device has a common logic-ground  
and power-ground terminal. If ground pattern layout  
contains large common-mode resistance, and the voltage  
between the system ground and the LATCH ENABLE or  
CLOCK terminals exceeds 2.5 V (because of switching  
noise), these devices may not operate correctly.  
0
5 k  
2 k  
EXT IN OHMS  
3 k  
100  
200  
300  
500  
700  
1 k  
CURRENT-CONTROL RESISTANCE, R  
Dwg. GP-061  
Package Power Dissipation (PD). The maximum al-  
lowable package power dissipation is determined as  
PD(max) = (150 - TA)/RθJA  
.
The actual package power dissipation is  
PD(act) = dc(VCE × IO × 8) + (VDD × IDD).  
V
LED  
When the load supply voltage is greater than 3 V to 5 V,  
considering the package power dissipating limits of these  
devices, or if PD(act) > PD(max), an external voltage re-  
ducer (VDROP) should be used.  
V
DROP  
Load Supply Voltage (VLED). These devices are de-  
signed to operate with driver voltage drops (VCE) of  
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to  
4.0 V. If higher voltages are dropped across the driver,  
package power dissipation will be increased significantly.  
To minimize package power dissipation, it is recom-  
mended to use the lowest possible load supply voltage or  
to set any series dropping voltage (VDROP) as  
V
F
V
CE  
Dwg. EP-064  
VDROP = VLED - VF - VCE  
with VDROP = Io × RDROP for a single driver, or a Zener  
diode (VZ), or a series string of diodes (approximately  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
10  
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
Serial-Input Constant-Current Latched LED Driver  
with Open LED Detection and Dot Correction  
A6275  
Package A 16-Pin DIP  
19.05±0.25  
16  
+0.10  
0.38  
–0.05  
+0.76  
–0.25  
+0.38  
10.92  
–0.25  
6.35  
7.62  
A
1
2
For Reference Only  
(reference JEDEC MS-001 BB)  
Dimensions in inches, metric dimensions (mm) in brackets, for reference only  
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions  
Exact case and lead configuration at supplier discretion within limits shown  
5.33 MAX  
+0.51  
3.30  
–0.38  
1.27 MIN  
2.54  
A
Terminal #1 mark area  
+0.25  
1.52  
–0.38  
0.46 ±0.12  
Package LW 16-Pin SOICW  
10.30±0.20  
1.27  
0.65  
4° ±4  
16  
16  
+0.07  
0.27  
–0.06  
10.30±0.33  
7.50±0.10  
9.50  
A
+0.44  
–0.43  
0.84  
0.25  
2.25  
1
2
1
2
PCB Layout Reference View  
B
16X  
C
SEATING PLANE  
GAUGE PLANE  
SEATING  
PLANE  
0.10  
C
1.27  
0.41 ±0.10  
2.65 MAX  
0.20 ±0.10  
For Reference Only  
Dimensions in millimeters  
(reference JEDEC MS-013 AA)  
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions  
Exact case and lead configuration at supplier discretion within limits shown  
Terminal #1 mark area  
A
B
Reference pad layout (reference IPC SOIC127P1030X265-16M)  
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary  
to meet application process requirements and PCB layout tolerances  
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Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-  
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the  
information being relied upon is current.  
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nor for any infringement of patents or other rights of third parties which may result from its use.  
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11  
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