SST31LH021-70-4C-WH--Datasheet/数据表在线中文翻译

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

FEATURES:

•

Organized as 256K x8 flash + 128K x8 SRAM

Single 3.0-3.6V Read and Write Operations

Concurrent Operation

•

Latched Address and Data for Flash

1

Flash Fast Sector-Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Bank-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Bank Rewrite Time: 4 seconds (typical)

– Read from or Write to SRAM while

Erase/Program Flash

2

•

Superior Reliability

•

Flash Automatic Erase and Program Timing

– Internal V_PPGeneration

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

3

Flash End of Write Detection

Low Power Consumption:

– Toggle Bit

– Data# Polling

4

– Active Current: 10 mA (typical) for Flash

and 20 mA (typical) for SRAM Read

– Standby Current: 700 µA (typical)

•

CMOS I/O Compatibility

JEDEC Standard Command Set

Packages Available

•

Sector-Erase Capability

– Uniform 4 KByte sectors

Fast Read Access Times:

5

– 32-Pin TSOP (8mm x 14mm)

– 40-Pin TSOP (10mm x 14mm)

6

– Flash: 70 ns

– SRAM: 25 ns

7

PRODUCT DESCRIPTION

signal, BEF# selects the flash memory bank. The WE#

signal has to be used with Software Data Protection

(SDP) command sequence when controlling the Erase

and Program operations in the flash memory bank. The

SDPcommandsequenceprotectsthedatastoredinthe

flash memory bank from accidental alteration.

The SST31LH021 is a 256K x8 CMOS flash memory

bank combined with a 128K x8 CMOS SRAM memory

bank manufactured with SST’s proprietary, high perfor-

mance SuperFlash technology. The SST31LH021 de-

vice writes (SRAM or flash) with a 3.0-3.6V power

supply.ThemonolithicSST31LH021deviceconformsto

JEDEC standard pinouts and Software Data Protect

(SDP) commands for x8 EEPROMs in TSOP packages.

8

9

The SST31LH021 provides the added functionality of

being able to simultaneously read from or write to the

SRAM bank while erasing or programming in the flash

memory bank. The SRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Byte-Program concurrently. All

flash memory Erase and Program operations will auto-

matically latch the input address and data signals and

complete the operation in background without further

input stimulus requirement. Once the internally con-

trolled Erase or Program cycle in the flash bank has

commenced,theSRAMbankcanbeaccessedforRead

or Write.

10

11

12

13

14

15

16

Featuring high performance Byte-Program, the flash

memory bank provides a maximum Byte-Program time

of 20 µsec. The entire flash memory bank can be erased

and programmed byte-by-byte in typically 4 seconds,

when using interface features such as Toggle Bit or

Data# Polling to indicate the completion of Program

operation. To protect against inadvertent flash write, the

SST31LH021 device has on-chip hardware and soft-

ware data protection schemes. Designed, manufac-

tured,andtestedforawidespectrumofapplications,the

SST31LH021deviceisofferedwithaguaranteedendur-

ance of 10,000 cycles. Data retention is rated at greater

than 100 years.

The SST31LH021 device is suited for applications that

use both nonvolatile flash memory and volatile SRAM

memory to store code or data. For all system applica-

tions, the SST31LH021 device significantly improves

performance and reliability, while lowering power con-

sumption, when compared with multiple chip solutions.

The SST31LH021 inherently uses less energy during

Erase and Program than alternative flash technologies.

When programming a flash device, the total energy

consumed is a function of the applied voltage, current,

and time of application. Since for any given voltage

TheSST31LH021operatesastwoindependentmemory

banks with respective bank enable signals. The SRAM

andFlashmemorybanksaresuperimposedinthesame

memory address space. Both memory banks share

common address lines, data lines, WE# and OE#. The

memory bank selection is done by memory bank enable

signals. The SRAM bank enable signal, BES# selects

the SRAM bank and the flash memory bank enable

353-11 11/99

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2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

range, the SuperFlash technology uses less current to

when OE# is high. Refer to the Read cycle timing

diagram, Figure 2, for further details.

program and has a shorter Erase time, the total energy

consumedduringanyEraseorProgramoperationisless

than alternative flash technologies. The monolithic

ComboMemory eliminates redundant functions when

using two separate memories of similar architecture;

therefore, reducing the total power consumption.

SRAM Write

The SRAM Write operation of the SST31LH021 is con-

trolled by WE# and BES#, both have to be low for the

system to write to the SRAM. BES# is used for SRAM

bank selection. During the Byte Write operation, the

addresses and data are referenced to the rising edge of

either BES# or WE#, whichever occurs first. The Write

time is measured from the last falling edge to the first

rising edge of BES# and WE#. Refer to the Write cycle

timing diagram, Figure 3, for further details.

The SuperFlash technology provides fixed Erase and

Program times, independent of the number of Erase/

Program cycles that have occurred. Therefore the sys-

tem software or hardware does not have to be modified

or de-rated as is necessary with alternative flash tech-

nologies,whoseEraseandProgramtimesincreasewith

accumulated Erase/Program cycles.

Flash Operation

The SST31LH021 device also improves flexibility by

using a single package and a common set of signals to

perform functions previously requiring two separate de-

vices. To meet high density, surface mount require-

ments, the SST31LH021 device is offered in 32-pin and

40-pin TSOP packages. See Figure 1 for the pinouts.

With BEF# active, the SST31LH021 operates as a 256K

x 8 flash memory. The flash memory bank is read using

the common address lines, data lines, WE# and OE#.

Erase and Program operations are initiated with the

JEDEC standard SDP command sequences. Address

and data are latched during the SDP commands and

internally timed Erase and Program operations.

Device Operation

The ComboMemory uses BES# and BEF# to control

operation of either the SRAM or the flash memory bank.

Buscontentioniseliminatedasthemonolithicdevicewill

not recognize both bank enables as being simulta-

neously active. If both bank enables are asserted (i.e.,

BEF# and BES# are both low), the BEF# will dominate

while the BES# is ignored and the appropriate operation

willbeexecutedintheflashmemorybank. SSTdoesnot

recommend that both bank enables be simultaneously

asserted. All other address, data, and control lines are

shared; which minimizes power consumption and area.

The device goes into standby when both bank enables

Flash Read

The Read operation of the SST31LH021 device is con-

trolled by BEF# and OE#, both have to be low, with WE#

high, for the system to obtain data from the outputs.

BEF# is used for flash memory bank selection. When

BEF# and BES# are high, both banks are deselected

and only standby power is consumed. OE# is the output

controlandisusedtogatedatafromtheoutputpins. The

data bus is in high impedance state when OE# is high.

Refer to the Read cycle timing diagram (Figure 4) for

further details.

are raised to V_IHC

.

Flash Erase/Program Operation

SDP commands are used to initiate the flash memory

bank Program and Erase operations of the

SST31LH021. SDP commands are loaded to the flash

memory bank using standard microprocessor write se-

quences. A command is loaded by asserting WE# low

while keeping BEF# low and OE# high. The address is

latched on the falling edge of WE# or BEF#, whichever

occurslast.ThedataislatchedontherisingedgeofWE#

or BEF#, whichever occurs first.

SRAM Operation

With BES# low and BEF# high, the SST31LH021 oper-

ates as a 128K x8 CMOS SRAM, with fully static opera-

tion requiring no external clocks or timing strobes. The

SRAM is mapped into the first 128 KByte address space

of the device. Read and Write cycle times are equal.

SRAM Read

The SRAM Read operation of the SST31LH021 is con-

trolled by OE# and BES#, both have to be low with WE#

high, for the system to obtain data from the outputs.

BES#isusedforSRAMbankselection.WhenBES#and

BEF#arehigh,bothmemorybanksaredeselected.OE#

is the output control and is used to gate data from the

output pins. The data bus is in high impedance state

353-11 11/99

2

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

Flash Byte-Program Operation

Figure 10 for timing diagram, and Figure 19 for the

The flash memory bank of the SST31LH021 device is

programmed on a byte-by-byte basis. The Program

operation consists of three steps. The first step is the

three-byte-load sequence for Software Data Protection.

The second step is to load byte address and byte data.

During the Byte-Program operation, the addresses are

latched on the falling edge of either BEF# or WE#,

whichever occurs last. The data is latched on the rising

edge of either BEF# or WE#, whichever occurs first. The

third step is the internal Program operation which is

initiated after the rising edge of the fourth WE# or BEF#,

whichever occurs first. The Program operation, once

initiated, will be completed, within 20 µs. See Figures 5

and 6 for WE# and BEF# controlled Program operation

timingdiagramsandFigure16forflowcharts. Duringthe

Programoperation,theonlyvalidFlashReadoperations

are Data# Polling and Toggle Bit. During the internal

Program operation, the host is free to perform additional

tasks. Any SDP commands loaded during the internal

Program operation will be ignored.

flowchart. Any SDP commands loaded during the Bank-

Erase operation will be ignored.

1

Flash Write Operation Status Detection

The SST31LH021 flash memory bank provides two

software means to detect the completion of a flash

memorybankWrite(ProgramorErase)cycle,inorderto

optimize the system Write cycle time. The software

detection includes two status bits: Data# Polling (DQ7)

and Toggle Bit (DQ6). The end of write detection mode

is enabled after the rising edge of WE#, which initiates

the internal Program or Erase operation. The actual

completion of the nonvolatile write is asynchronous with

thesystem;therefore,eitheraData#PollingorToggleBit

Read may be simultaneous with the completion of the

Write cycle. If this occurs, the system may possibly get

anerroneousresult,i.e.,validdatamayappeartoconflict

with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed

location an additional two (2) times. If both reads are

valid, then the device has completed the Write cycle,

otherwise the rejection is valid.

2

3

4

5

6

7

Flash Sector-Erase Operation

The Sector-Erase operation allows the system to erase

the flash memory bank on a sector by sector basis. The

sector architecture is based on uniform sector size of 4

KBytes. The Sector-Erase operation is initiated by ex-

ecutingasix-byte-commandloadsequenceforsoftware

data protection with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The address

lines A12-A17 will be used to determine the sector

address. The sector address is latched on the falling

edge of the sixth WE# pulse, while the command (30H)

is latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE#

pulse. The end of Erase can be determined using either

Data# Polling or Toggle Bit methods. See Figure 9 for

timing waveforms. Any SDP commands loaded during

the Sector-Erase operation will be ignored.

8

Flash Data# Polling (DQ7)

When the SST31LH021 flash memory bank is in the

internalProgramoperation,anyattempttoreadDQ7will

produce the complement of the true data. Once the

Program operation is completed, DQ7 will produce true

data. The flash memory bank is then ready for the next

operation. During internal Erase operation, any attempt

to read DQ7 will produce a ‘0’. Once the internal Erase

operation is completed, DQ7 will produce a ‘1’. The

Data# Polling is valid after the rising edge of the fourth

WE# (or BEF#) pulse for Program operation. For Sector

or Bank-Erase, the Data# Polling is valid after the rising

edge of the sixth WE# (or BEF#) pulse. See Figure 7 for

Data# Polling timing diagram and Figure 17 for a flow-

chart.

9

10

11

12

13

14

15

16

Flash Bank-Erase Operation

The SST31LH021 flash memory bank provides a Bank-

Eraseoperation,whichallowstheusertoerasetheentire

flash memory bank array to the “1’s” state. This is useful

when the entire bank must be quickly erased. The Bank-

Erase operation is initiated by executing a six-byte soft-

ware data protection command sequence with Bank-

Erase command (10H) with address 5555H in the last

bytesequence.TheinternalEraseoperationbeginswith

the rising edge of the sixth WE# or BEF# pulse, which-

everoccursfirst.DuringtheinternalEraseoperation,the

only valid Flash Read operations are Toggle Bit and

Data# Polling. See Table 4 for the command sequence,

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any

consecutive attempts to read DQ6 will produce alternat-

ing 0’s and 1’s, i.e., toggling between 0 and 1. When the

internal Program or Erase operation is completed, the

toggling will stop. The flash memory bank is then ready

for the next operation. The Toggle Bit is valid after the

risingedgeofthefourthWE#(orBE#)pulseforProgram

operation. For Sector or Bank-Erase, the Toggle Bit is

valid after the rising edge of the sixth WE# (or BEF#)

pulse. See Figure 8 for Toggle Bit timing diagram and

Figure 17 for a flowchart.

353-11 11/99

3

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

Flash Memory Data Protection

Product Identification

The SST31LH021 flash memory bank provides both

hardware and software features to protect nonvolatile

data from inadvertent writes.

The product identification mode identifies the device as

the SST31LH021 and manufacturer as SST. This mode

may be accessed by hardware or software operations.

ThehardwaredeviceIDReadoperationistypicallyused

by a programmer to identify the correct algorithm for the

SST31LH021 flash memory bank. Users may wish to

usethesoftwareproductidentificationoperationtoiden-

tify the part (i.e., using the device code) when using

multiple manufacturers in the same socket. For details,

see Table 3 for hardware operation or Table 4 for

software operation, Figure 11 for the software ID entry

and read timing diagram and Figure 18 for the ID entry

command sequence flowchart.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less

than 5 ns will not initiate a Write cycle.

V_DDPower Up/Down Detection: The Write operation is

inhibited when V_DDis less than 1.5V.

WriteInhibitMode:ForcingOE#low, BEF#high, orWE#

high will inhibit the Flash Write operation. This prevents

inadvertent writes during power-up or power-down.

Flash Software Data Protection (SDP)

T^ABLE1: PRODUCT IDENTIFICATION TABLE

The SST31LH021 provides the JEDEC approved soft-

ware data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three byte-load sequence is

usedtoinitiatetheProgramoperation, providingoptimal

protectionfrominadvertentWriteoperations,e.g.,during

the system power-up or power-down. Any Erase opera-

tionrequirestheinclusionofsix-byteloadsequence.The

SST31LH021 device is shipped with the software data

protection permanently enabled. See Table 4 for the

specific software command codes. During SDP com-

mand sequence, invalid SDP commands will abort the

device to the Read mode, within TRC.

Address

0000H

Data

Manufacturer’s Code

Device Code

BF H

0001H

18 H

353 PGM T1.0

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the

Software Product Identification mode must be exited.

Exiting is accomplished by issuing the Exit ID command

sequence, which returns the device to the Read opera-

tion. Please note that the software-reset command is

ignored during an internal Program or Erase operation.

See Table 4 for software command codes, Figure 12 for

timing waveform and Figure 18 for a flowchart.

Concurrent Read and Write Operations

The SST31LH021 provides the unique benefit of being

abletoreadfromorwritetoSRAM, whilesimultaneously

erasingorprogrammingtheFlash.Thedevicewillignore

allSDPcommandswhenanEraseorProgramoperation

is in progress. This allows data alteration code to be

executed from SRAM, while altering the data in Flash.

The following table lists all valid states. SST does not

recommendthatbothbankenables,BEF#andBES#,be

simultaneously asserted.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic

capacitortobeplacedascloseaspossiblebetweenV_DD

andV_SS,e.g.,lessthan1cmawayfromtheV_DDpinofthe

device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from V_DDto V_SSshould be placed within 5 cm

of the V_DDpin.

CONCURRENT READ/WRITE STATE TABLE

Flash

SRAM

Read

Write

Program/Erase

Note that Product Identification commands use SDP;

therefore, these commands will also be ignored while an

Erase or Program operation is in progress.

353-11 11/99

4

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

FUNCTIONAL BLOCK DIAGRAM OF SST31LH021

1

1,048,576 bit

SRAM

Cell Array

Address Buffers

Control Logic

2

BES#

BEF#

OE#

A

- A

I/O Buffers

16

0

DQ - DQ

7

0

3

WE#

4

2,097,152 bit

EEPROM

Cell Array

Address Buffers

& Latches

A

17

353 ILL B1.3

5

6

A16

A15

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A17

2

V

SS

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE#

A14

A13

A12

A11

A9

3

NC

2

A10

4

NC

A8

3

BEF#

DQ7

DQ6

DQ5

DQ4

DQ3

5

A10

DQ7

DQ6

DQ5

DQ4

A13

A14

A17

WE#

4

7

6

5

7

Standard Pinout

6

A8

8

7

Standard Pinout

Top View

WE#

NC

BES#

NC

A7

9

Top View

Die Up

V

8

10

11

12

13

14

15

16

17

18

19

20

V

DD

BES#

A16

A15

A12

A7

9

V

8

V

SS

DD

10

11

12

13

14

15

16

DQ2

DQ1

DQ0

A0

NC

Die Up

DQ3

DQ2

DQ1

DQ0

OE#

A6

A1

9

A5

A2

A4

A3

V

SS

A2

BEF#

A0

353 ILL F01A.2

A1

10

11

12

13

14

15

16

353 ILL F01.1

32-PIN TSOP PACKAGE (8mm x 14mm)

40-PIN TSOP PACKAGE (10mm x 14mm)

FIGURE 1: PIN ASSIGNMENTS

TABLE 2: PIN DESCRIPTION

Symbol

Pin Name

Functions

A₁₇-A₀

Address Inputs

To provide memory addresses. During Flash Sector-Erase A₁₇-A₁₂

address lines will select the sector. A₁₇-A₀to provide flash address,

A₁₆-A₀to provide SRAM addresses.

DQ₇-DQ₀Data Input/output

To output data during read cycles and receive input data during write

cycles. Data is internally latched during a Flash Erase/Program cycle.

The outputs are in tri-state when OE# or BES# and BEF# are high.

BES#

BEF#

SRAM Memory Bank

Enable

To activate the SRAM memory bank when BES# is low.

Flash Memory Bank

Enable

To activate the Flash memory bank when BEF# is low.

OE#

WE#

V_DD

Vss

Output Enable

Write Enable

Power Supply

Ground

To gate the data output buffers.

To control the Write operations.

To provide 3.0-3.6V supply

353 PGM T2.5

353-11 11/99

5

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

TABLE 3: OPERATION MODES SELECTION

Mode

BES# BEF# OE# WE#

A9

A_IN

X

DQ

D_OUT

D_IN

X

Address

A_IN

Flash Read

Flash Program

Flash Erase

X

V_IL

V_IH

V_IL

A_IN

Sector address, XXh for

Bank-Erase

SRAM Read

SRAM Write

Standby

V_IL

V_IH

V_IL

X

V_IH

V_IL

X

A_IN

X

D_OUT

D_IN

A_IN

X

V_IHCV_IHC

X

High Z

Flash Write Inhibit

X

V_IH

V_IL

X

V_IH

X

High Z/D_OUT

X

Product Identification

Hardware Mode

X

V_IL

V_IH

V_H

Manufacturer

Code (BF)

A₁₇- A₁= V_IL, A₀= V_IL

Device Code (18) A₁₇- A₁= V_IL, A₀= V_IH

Software Mode

A_IN

ID Code

See Table 4

353 PGM T3.5

TABLE 4: SOFTWARE COMMAND SEQUENCE FOR FLASH MEMORY BANK

Command

Sequence

1st Bus

Write Cycle

Addr⁽¹⁾Data Addr⁽¹⁾Data

2nd Bus

Write Cycle

3rd Bus

Write Cycle

Addr⁽¹⁾Data Addr⁽¹⁾Data

4th Bus

Write Cycle

5th Bus

Write Cycle

Addr⁽¹⁾Data Addr⁽¹⁾Data

6th Bus

Write Cycle

Byte-Program

Sector-Erase

Bank-Erase

5555H AAH

2AAAH 55H

5555H A0H

5555H 80H

5555H 90H

5555H F0H

BA⁽³⁾

Data

5555H AAH

2AAAH 55H SA_x⁽²⁾30H

2AAAH 55H 5555H 10H

Software ID Entry 5555H AAH

Software ID Exit

5555H AAH

353 PGM T4.1

Notes:

(1)

Address format A₁₄-A₀(Hex), Addresses A_15,A₁₆and A₁₇are a “Don’t Care” for the

Command sequence.

SA_xfor Sector-Erase; uses A₁₇-A₁₂address lines

BA = Program Byte address

(2)

(3)

Notes for Software ID Entry Command Sequence

1. With A₁₇-A₁=0; SST Manufacturer Code = BFH, is read with A₀= 0,

31LH021 Device Code = 18H, is read with A₀= 1.

2. The device does not remain in Software Product ID Mode if powered down.

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress

Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice

at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.

Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias ................................................................................................................. -55°C to +125°C

Storage Temperature ...................................................................................................................... -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to V_DD+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential......................................................... -1.0V to V_DD+ 1.0V

Voltage on A₉Pin to Ground Potential ................................................................................................ -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C

Output Short Circuit Current⁽¹⁾................................................................................................................................................................. 50 mA

Note: ⁽¹⁾Outputs shorted for no more than one second. No more than one output shorted at a time.

353-11 11/99

6

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

OPERATING RANGE

Range

AC CONDITIONS OF TEST

Ambient Temp

0 °C to +70 °C

-40 °C to +85 °C

V_DD

Input Rise/Fall Time......... 5 ns

Output Load..................... C_L= 30 pF

See Figures 14 and 15

1

Commercial

Industrial

3.0-3.6V

2

TABLE 5: DC OPERATING CHARACTERISTICS V_DD= 3.0-3.6V

3

Limits

Symbol Parameter

Min

Max

Units Test Conditions

4

I_DD

Power Supply Current

V_DD= V_DDMax, all DQs open, Address

input = V_IL/V_IH, at f=1/T_RCMin.

OE# = V_IL, WE# = V_IH

BEF# = V_IL, BES# = V_IH

BEF# = V_IH, BES# = V_IL

Read

Flash

12

40

mA

5

SRAM

Concurrent Operation

55

mA

BEF# = V_IH, BES# = V_IL

Write

OE# = V_IH, WE# = V_IL

BEF# = V_IL, BES# = V_IH

BEF# = V_IH, BES# = V_IL

6

Flash (Program)

SRAM

15

40

mA

I_SB

I_LI

Standby V_DDCurrent

Input Leakage Current

Output Leakage Current

Input Low Voltage

1

mA

µA

V

V_DD= V_DDMax. BEF# = BES# = V_IHC

V_IN=GND to V_DD, V_DD= V_DDMax.

V_OUT=GND to V_DD, V_DD= V_DDMax.

V_DD= V_DDMin.

7

I_LO

V_IL

V_IH

V_IHC

V_OL

V_OH

V_H

1

8

0.4

Input High Voltage

0.7V_DD

V

V_DD= V_DDMax.

Input High Voltage (CMOS) V_DD-0.3

Output Low Voltage

V

V_DD= V_DDMax.

9

0.2

V

I_OL= 100 µA, V_DD= V_DDMin.

I_OH= -100µA, V_DD= V_DDMin.

BEF# = OE# =V_IL, WE# = V_IH

BEF# = OE# = V_IL, WE# = V_IH, A₉= V_HMax.

Output High Voltage

V_DD-0.2

11.4

V

10

11

12

13

14

15

16

Supervoltage for A₉pin

12.6

200

V

I_H

Supervoltage Current

for A₉pin

µA

353 PGM T5.9

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol

Parameter

Minimum

Units

(1)

T_PU-READ

Power-up to Read Operation

Power-up to Write Operation

100

µs

(1)

T_PU-WRITE

353 PGM T6.0

TABLE 7: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

(1)

C_I/O

I/O Pin Capacitance

Input Capacitance

V_I/O= 0V

V_IN= 0V

12 pF

6 pF

(1)

C_IN

353 PGM T7.0

Note: ⁽¹⁾This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

353-11 11/99

7

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

Test Method

(1)

N_END

Endurance

10,000

100

Cycles

Years

Volts

JEDEC Standard A117

JEDEC Standard A103

JEDEC Standard A114

(1)

T_DR

Data Retention

(1)

V_{ZAP_HBM}

ESD Susceptibility

Human Body Model

1000

(1)

V_{ZAP_MM}

ESD Susceptibility

Machine Model

200

Volts

mA

JEDEC Standard A115

JEDEC Standard 78

(1)

I_LTH

Latch Up

100 + I_DD

353 PGM T8.2

Note: ⁽¹⁾This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 9: SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS V_DD= 3.0-3.6V

Symbol

T_RCS

Parameter

Min

Max

Unit

ns

Read Cycle Time

25

T_AAS

Address Access Time

25

17

ns

T_BES

Bank Enable Access Time

Output Enable Access Time

BES# to Active Output

ns

T_OES

ns

(1)

T_BLZS

0

ns

(1)

T_OLZS

Output Enable to Active Output

BES# to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

ns

(1)

T_BHZS

10

ns

(1)

T_OHZS

ns

T_OHS

0

ns

353 PGM T9.3

Note: (1) This parameter is measured only for initial qualification and after the design or process change

that could affect this parameter.

TABLE 10: SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS V_DD= 3.0-3.6V

Symbol

T_WCS

T_BWS

T_AWS

T_ASTS

T_WPS

T_WRS

T_DSS

Parameter

Min

25

12

0

Max

Unit

ns

Write Cycle Time

Bank Enable to End of Write

Address Valid to End of Write

Address Set-up Time

Write Pulse Width

12

0

Write recovery Time

Data Set-up Time

12

0

T_DHS

Data Hold from Write Time

353 PGM T10.3

353-11 11/99

8

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

AC CHARACTERISTICS

TABLE 11: FLASH READ CYCLE TIMING PARAMETERS V_DD= 3.0-3.6V

1

Symbol

T_RC

Parameter

Min

Max

Units

Read Cycle Time

70

ns

2

T_BE

Bank Enable Access Time

Address Access Time

70

40

ns

T_AA

ns

T_OE

Output Enable Access Time

BEF# Low to Active Output

OE# Low to Active Output

BEF# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

ns

3

(1)

T_BLZ

0

ns

(1)

T_OLZ

ns

(1)

T_BHZ

15

4

(1)

T_OHZ

ns

(1)

T_OH

0

ns

5

353 PGM T11.3

Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect

this parameter.

6

7

TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS V_DD= 3.0-3.6V

Symbol

T_BP

Parameter

Min

Max

Units

µs

8

Byte-Program Time

Address Setup Time

Address Hold Time

WE# and BEF# Setup Time

WE# and BEF# Hold Time

OE# High Setup Time

OE# High Hold Time

BEF# Pulse Width

WE# Pulse Width

20

T_AS

0

30

0

ns

T_AH

ns

9

T_BS

ns

T_BH

0

ns

T_OES

T_OEH

T_BP

0

ns

10

11

12

13

14

15

16

10

40

30

40

0

ns

T_WP

T_WPH

T_BPH

T_DS

ns

WE# Pulse Width High

BEF# Pulse Width High

Data Setup Time

ns

T_DH

Data Hold Time

ns

T_IDA

T_SE

Software ID Access and Exit Time

Sector-Erase

150

25

ns

ms

ns

T_SBE

T_BS

Bank-Erase

100

Bank Enable Setup Time

for Concurrent Operation

0

353 PGM T12.1

353-11 11/99

9

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

T

RCS

AAS

ADDRESS A

16-0

BEF#

BES#

OE#

T

BES

T

OES

T

OHZS

OLZS

V

IH

WE#

T

BHZS

T

OHS

BLZS

HIGH-Z

DQ

7-0

DATA VALID

353 ILL F02.3

FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM

T

WCS

ADDRESS A

ADDRESS

16-0

OE#

T

AWS

BEF#

BES#

WE#

T

BWS

T

WRS

T

WPS

T

ASTS

T

DSS

DATA VALID

T

DHS

DQ

7-0

353 ILL F03.5

FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM

353-11 11/99

10

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

T

AA

RC

1

ADDRESS A

17-0

2

BES#

BEF#

OE#

3

T

BE

4

T

OE

5

T

OHZ

V

OLZ

IH

WE#

T

BHZ

6

T

OH

T

HIGH-Z

BLZ

HIGH-Z

DQ

7-0

DATA VALID

7

353 ILL F18.1

FIGURE 4: FLASH READ CYCLE TIMING DIAGRAM

8

9

INTERNAL PROGRAM OPERATION STARTS

T

BP

10

11

12

13

14

15

16

5555

2AAA

5555

ADDR

ADDRESS A

17-0

T

AH

T

DH

T

WP

WE#

OE#

T

AS

DS

T

WPH

T

CH

BEF#

T

CS

BES#

DQ

7-0

AA

SW0

55

A0

DATA

BYTE

SW1

SW2

(ADDR/DATA)

353 ILL F04.1

FIGURE 5: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

353-11 11/99

11

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

17-0

BES#

BEF#

OE#

T

AH

T

DH

T

CP

T

AS

DS

T

CPH

T

CH

WE#

T

CS

DQ

7-0

AA

SW0

55

A0

DATA

SW1

SW2

BYTE

(ADDR/DATA)

353 ILL F05.1

FIGURE 6: FLASH BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

17-0

BES#

T

CE

BEF#

OE#

T

OES

T

OEH

T

OE

WE#

DQ

7

D

D#

D

353 ILL F06.1

FIGURE 7: FLASH DATA# POLLING TIMING DIAGRAM

353-11 11/99

12

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

1

ADDRESS A

17-0

2

BES#

T

BE

3

BEF#

OE#

T

OES

T

OE

OEH

4

5

WE#

6

DQ

6

TWO READ CYCLES

WITH SAME OUTPUTS

7

353 ILL F07.1

FIGURE 8: FLASH TOGGLE BIT TIMING DIAGRAM

8

9

T

SE

SIX-BYTE CODE FOR SECTOR-ERASE

5555 5555 2AAA

5555

2AAA

SA

X

ADDRESS A

17-0

10

11

12

13

14

15

16

BES#

BEF#

OE#

T

WP

WE#

DQ

7-0

AA

55

SW1

80

SW2

AA

SW3

55

SW4

30

SW0

SW5

353 ILL F08.2

Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See table 10)

SA = Sector Address

X

FIGURE 9: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

353-11 11/99

13

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

T

SBE

SIX-BYTE CODE FOR BANK-ERASE

5555 5555 2AAA

5555

2AAA

5555

ADDRESS A

17-0

BES#

BEF#

OE#

T

WP

WE#

DQ

7-0

AA

55

SW1

80

SW2

AA

SW3

55

SW4

10

SW0

SW5

353 ILL F17.3

Note: The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See table 10)

FIGURE 10: FLASH WE# CONTROLLED BANK-ERASE TIMING DIAGRAM

Three-byte sequence for

Software ID Entry

ADDRESS A

5555

2AAA

5555

0000

0001

14-0

BES#

BEF#

OE#

T

IDA

T

WP

AA

WE#

T

WPH

55

SW1

T

AA

DQ

7-0

90

BF

18

SW0

SW2

MFG ID DEVICE ID

353 ILL F09.3

FIGURE 11: FLASH SOFTWARE ID ENTRY AND READ

353-11 11/99

14

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

1

5555

2AAA

5555

ADDRESS A

14-0

2

BES#

T

IDA

3

BEF#

OE#

4

T

WP

5

WE#

T

WHP

SW0

AA

SW1

SW2

F0

6

DQ

55

7-0

7

353 ILL F10.2

FIGURE 12: FLASH SOFTWARE ID EXIT AND RESET

8

9

ADDRESS A

17-0

10

11

12

13

14

15

16

BEj#

T

BS

BEj1#

WE#

OE#

DQ

7-0

353 ILL F20.0

Note:

j

= F or S

j1 = S or F

FIGURE 13: TIMING DIAGRAM FOR ALTERNATING BETWEEN FLASH/SRAM TO SRAM/FLASH

353-11 11/99

15

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

V

IHT

V

HT

INPUT

REFERENCE POINTS

OUTPUT

V

LT

V

ILT

353 ILL F11.0

AC test inputs are driven at V_IHT(0.9 V_DD) for a logic “1” and V_ILT(0.1 V_DD) for a logic “0”.

Measurement reference points for inputs and outputs are at V_HT(1.6 V)⁽¹⁾and V_LT(1.4 V)⁽¹⁾

Input rise and fall times (10%

90%) are <5 ns.

Note: V_HT–V_HIGHTest

V_LT–V_LOWTest

(1) Output test level per common SRAM test standards

V_IHT–V_INPUTHIGH Test

V_ILT–V_INPUTLOW Test

FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TEST LOAD EXAMPLE

V

DD

TO TESTER

R

L HIGH

TO DUT

C

L

R

L LOW

353 ILL F12.0

FIGURE 15: A TEST LOAD EXAMPLE

353-11 11/99

16

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

1

Start

2

Load data: AA

Address: 5555

3

4

Load data: 55

Address: 2AAA

5

Load data: A0

Address: 5555

6

7

Load Byte

Address/Byte

Data

8

Wait for end of

9

Program (T

,

BP

Data# Polling

bit, or Toggle bit

operation)

10

11

12

13

14

15

16

Program

Completed

353 ILL F13.1

FIGURE 16: BYTE-PROGRAM ALGORITHM

353-11 11/99

17

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

Toggle Bit

Data# Polling

Internal Timer

Byte

Program/Erase

Initiated

Byte

Program/Erase

Initiated

Byte

Program/Erase

Initiated

Read DQ

7

Read byte

Wait T

,

T

BP

T

SBE, or SE

Read same

byte

Is DQ =

7

No

true data?

Program/Erase

Completed

Yes

No

Does DQ

match?

6

Program/Erase

Completed

Yes

Program/Erase

Completed

353 ILL F14.0

FIGURE 17: WAIT OPTIONS

353-11 11/99

18

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

1

Software Product ID Entry

Command Sequence

Software Product ID Exit &

Reset Command Sequence

2

Load data: AA

Address: 5555

Load data: AA

Address: 5555

Load data: F0

Address: XX

3

4

Load data: 55

Address: 2AAA

Load data: 55

Address: 2AAA

Wait T

IDA

5

Load data: 90

Address: 5555

Load data: F0

Address: 5555

Return to normal

operation

6

7

Wait T

IDA

8

9

Return to normal

operation

Read Software ID

353 ILL F15.1

10

11

12

13

14

15

16

FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS

353-11 11/99

19

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

Chip-Erase

Sector-Erase

Command Sequence

Load data: AA

Address: 5555

Load data: AA

Address: 5555

Load data: 55

Address: 2AAA

Load data: 80

Address: 5555

Load data: 80

Address: 5555

Load data: AA

Address: 5555

Load data: AA

Address: 5555

Load data: 55

Address: 2AAA

Load data: 10

Address: 5555

Load data: 30

Address: SA

X

Wait T

SE

SBE

Chip erased

to FFH

Sector erased

to FFH

353 ILL F16.1

FIGURE 19: ERASE COMMAND SEQUENCE

353-11 11/99

20

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

Device

Speed Suffix1

- XXX XX

Suffix2

SST31LH021

-

XX

1

Package Modifier

H = 32 leads

2

I = 40 leads

Numeric = Die modifier

3

Package Type

W = TSOP (die up) 8mm x 14mm, or

10mm x 14mm

4

Temperature Range

C = Commercial = 0° to 70°C

I = Industrial = -40° to 85°C

5

Minimum Endurance

4 = 10,000 cycles

6

Read Access Speed

70 = 70 ns

Version

7

8

SST31LH021 Valid combinations

SST31LH021-70-4C-WI

SST31LH021-70-4C-WH

9

SST31LH021-70-4I-WI

SST31LH021-70-4I-WH

10

11

12

13

14

15

16

Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

353-11 11/99

21

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

PACKAGING DIAGRAMS

1.05

0.95

PIN # 1 IDENTIFIER

.50

BSC

.270

.170

8.10

7.90

0.15

0.05

12.50

12.30

0.70

0.50

14.20

13.80

Note:

1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

32.TSOP-WH-ILL.3

3. Coplanarity: 0.1 (±.05) mm.

32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

353-11 11/99

22

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

1.05

0.95

PIN # 1 IDENTIFIER

1

.50

BSC

2

.270

.170

10.10

9.90

3

4

5

0.15

0.05

12.50

12.30

6

0.60

0.40

14.20

7

13.80

Note:

1. Complies with JEDEC publication 95 MO-142 CA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

8

40.TSOP-WI-ILL.2

40-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 14MM

SST PACKAGE CODE: WI

9

10

11

12

13

14

15

16

353-11 11/99

23

2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

SALES OFFICES

SST Area Offices

Advance Information

International Sales Representatives & Distributors

Customer Service

Northwest USA, Rocky Mtns. & West Canada

Southwest USA

East USA & East Canada

Corporate CEM Accounts

North America - Distribution

Asia Pacific

East Asia

Europe

Northern Europe

(408) 523-7665

(408) 523-7661

(949) 495-6437

(978) 356-3845

(727) 771-8819

(941) 505-8893

(408) 523-7762

(81)45-471-1851

(44)1932-230555

(45) 3833-5000

Australia ACD

(61) 3-762 7644

Austria/Eastern Europe

Endrich Bauelemente Vertriebs GMBH

(43)2-236236-21

(32) 1540-0080

Belgium Memec Benelux

China/Hong Kong

Actron Technology Co., Ltd. (HQ) Hong Kong

Actron Technology Co., Ltd. - Shanghai

Actron Technology Co., Ltd. - Shenzhen

Actron Technology Co., Ltd. - Chengdu

Actron Technology Co., Ltd. - Beijing

Actron Technology Co., Ltd. - Wuhan

Actron Technology Co., Ltd. - Xian

(852) 2727-3978

(86)21-6482-8021

(86)755-376-2763

(86)28-553-2896

(86)10-6261-0042

(86)27-8788-7226

(86)29-831-4585

North American Sales Representatives

Alabama M-Squared, Inc. - Huntsville

Arizona Reptronix, Ltd.

(205) 830-0498

MetaTech Limited (HQ) - Hong Kong

MetaTech Limited - Beijing

MetaTech Limited - Shanghai

MetaTech Limited - Chengdu

MetaTech Limited - Fuzhou

MetaTech Limited - Shenzhen

(852) 2421-2379

(86)10-6858-2188

(86)21-6485-7530

(86)28-5577-415

(86)591-378-1033

(86)755-321-9726

(602) 230-2630

California

Costar - Northern

CK Associates - San Diego

Westar Rep Company, Inc. - Calabasas

Westar Rep Company, Inc. - Irvine

(408) 946-9339

(619) 279-0420

(818) 880-0594

(949) 453-7900

Denmark C-88 AS

Finland Memec Finland Oy

France

(45) 7010-4888

(358)9 350 8880

Colorado Lange Sales, Inc.

(303) 795-3600

(203) 634-8558

Connecticut Delta Conn Technical Sales

Florida

M-Squared, Inc. - Clearwater

M-Squared, Inc. - Longwood

A2M - Bron

(33) 4 72 37 0414

(33) 1 46 23 7900

(727) 669-2408

(407) 682-6662

A2M - Sevres

Germany

Endrich Bauelemente

Vertriebs GMBH - Bramstedt

Georgia M-Squared, Inc. - Atlanta

(770) 447-6124

Illinois

(49)4192-8784-0

(49) 7452-60070

Oasis Sales Corporation - Northern

Rush & West Associates - Southern

(847) 640-1850

(314) 965-3322

Endrich Bauelemente

Vertriebs GMBH - Nagold

Indiana Applied Data Management

Iowa Rush & West Associates

(317) 257-8949

(319) 398-9679

(913) 764-2700

(301) 663-4159

(781) 246-9996

(734) 741-9292

(651) 699-0200

(314) 965-3322

India

Team Technology - Bangalore

Team Technology - Hyderabad

Team Technology - New Delhi

(91)80-526-1102

(91) 40-231130

(91)11-220-5624

Kansas Rush & West Associates

Maryland Nexus Technology Sales

Massachusetts Innovative Applied Solutions

Michigan Applied Data Management

Minnesota Cahill, Schmitz & Cahill

Missouri Rush & West Associates

Ireland Curragh Technology

Israel Spectec Electronics

Italy Carlo Gavazzi Cefra SpA

(353) 61 316116

(972) 3-6498404

(39) 2-424-1471

Japan

Asahi Electronics Co., Ltd. - Tokyo

Asahi Electronics Co., Ltd. - Kitakyushu

(81)3-3350-5418

(81)93-511-6471

North Carolina

M-Squared, Inc. - Charlotte

M-Squared, Inc. - Raleigh

(704) 522-1150

(919) 848-4300

Microtek, Inc. - Osaka

Microtek, Inc. - Tokyo

(81)6-6263-5080

(81)3-5300-5515

New Mexico Reptronix, Ltd.

(505) 292-1718

Ryoden Trading Co., Ltd. - Osaka

Ryoden Trading Co., Ltd. - Tokyo

(81)6-6399-3443

(81)3-5396-6218

New York

Nova Technology

Reagan/Compar - Endwell

Reagan/Compar - E. Rochester

(516) 661-1800

(607) 754-2171

(716) 218-4370

Silicon Technology Co., Ltd.

(81)3-3795-6461

(82) 2-832-8881

Korea Bigshine Korea Co., Ltd.

Ohio

Malaysia

Applied Data Management - Cincinnati

Applied Data Management - Cleveland

(513) 579-8108

(440) 946-6812

MetaTech (M) SDN BHD

(60)4-658-4276

Serial System SDN BHD

Serial System - Kuala Lumpur

(60) 4-657-0204

(60) 3-737-1243

Oregon Thorson Pacific, Inc.

(503) 293-9001

Texas

Netherlands Memec Benelux

Norway Endrich Elektronikk AS

Philippines MetaTech (S) Pte Ltd.

(31)40-265-9399

(47) 22 52 13 20

(65) 748-4844

Technical Marketing, Inc. - Carrollton

Technical Marketing, Inc. - Houston

Technical Marketing, Inc. - Austin

(972) 387-3601

(713) 783-4497

(512) 343-6976

Singapore

MetaTech (S) Pte Ltd.

Utah Lange Sales, Inc.

(801) 487-0843

(425) 603-9393

(414) 782-6660

(65) 748-4844

Washington Thorson Pacific, Inc.

Wisconsin Oasis Sales Corporation

Serial System Ltd. (HQ)

(65) 280-0200

South Africa KH Distributors

Spain Tekelec Espana S.A.

Sweden Memec Scandinavia

Switzerland Leading Technologies

(27) 11 845-5011

(34) 91 371-7768

(46)8-459-7900

(41)27-721-7440/43

Canada

Electronics Sales Professionals - Ottawa

Electronics Sales Professionals - Toronto

Electronics Sales Professionals - Montreal

(613) 828-6881

(905) 856-8448

(514) 344-0420

Taiwan, R.O.C.

GCH-Sun Systems Co., Ltd. (GSS)

PCT Limited

Thorson Pacific, Inc. - B.C.

(604) 294-3999

(886)2-2555-0880

(886)2-2698-0098

(886)2-2651-0011

Tonsam Corporation

United Kingdom Ambar Components, Ltd.

(44)1296-397396

Revised 11-8-99

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873

353-11 11/99

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