CAT5409WI-10-T1--Datasheet/数据表在线中文翻译

CAT5409

Quad Digitally Programmable Potentiometers

(DPP™) with 64 Taps and I²C Interface

FEATURES

DESCRIPTION

Four linear taper digitally programmable

The CAT5409 is four Digitally Programmable

Potentiometers (DPP™) integrated with control logic

and 16 bytes of NVRAM memory.

potentiometers

64 resistor taps per potentiometer

End to end resistance 2.5kΩ, 10kΩ, 50kΩ or

100kΩ

A separate 6-bit control register (WCR) independently

controls the wiper tap position for each DPP.

Associated with each wiper control register are four

6-bit non-volatile memory data registers (DR) used for

storing up to four wiper settings. Writing to the wiper

control register or any of the non-volatile data

registers is via a I²C serial bus. On power-up, the

contents of the first data register (DR0) for each of the

four potentiometers is automatically loaded into its

respective wiper control register (WCR).

I²C interface

Low wiper resistance, typically 80Ω

Four non-volatile wiper settings for each

potentiometer

Recall of saved wiper settings at power-up

2.5 to 6.0 volt operation

Standby current less than 1µA

1,000,000 nonvolatile WRITE cycles

100 year nonvolatile memory data retention

24-lead SOIC and 24-lead TSSOP

Write protection for data register

¯¯¯

The Write Protection (WP) pin protects against

inadvertent programming of the data register.

The CAT5409 can be used as a potentiometer or as a

two terminal, variable resistor. It is intended for circuit

level or system level adjustments in a wide variety of

applications.

For Ordering Information details, see page 15.

FUNCTIONAL DIAGRAM

PIN CONFIGURATION

R

H2

R

H3

H0

H1

SOIC (W)

TSSOP (Y)

V

1

2

24

23

22

21

20

1

2

24 NC

SCL

SDA

WP

CC

I²C BUS

INTERFACE

WIPER CONTROL

REGISTERS

R

W0

W1

W2

W3

A

2

R

A

23

A

L0

L3

1

WP

R

3

22

21

20

19

18

R

W0

H0

H3

W3

L1

R

V

4

W0

A

0

H0

L0

H1

NONVOLATILE

DATA

REGISTERS

A

1

2

3

CONTROL LOGIC

A

2

5

R

0

W1

6

19

18

17

16

15

14

13

6

NC

GND

NC

WP

CC

NC

SDA

A

3

7

R

L2

R

L3

L0

L1

A

1

17 SCL

8

R

W2

L3

R

9

R

9

16

15

14

13

R

H2

H3

W3

L1

L2

R

10

11

12

10

11

12

H1

H2

W2

L2

R

SCL

A

W1

0

A

3

NC

GND

NC

Characteristics subject to change without notice

1

Doc. No. MD-2010 Rev. K

CAT5409

PIN DESCRIPTIONS

Pin#

SCL: Serial Clock

The CAT5409 serial clock input pin is used to clock all

data transfers into or out of the device.

(SOIC) (TSSOP) Name Function

Supply Voltage

19

20

1

2

V_CC

R_L0

Low Reference Terminal

for Potentiometer 0

SDA: Serial Data

The CAT5409 bidirectional serial data pin is used to

transfer data into and out of the device. The SDA pin is

an open drain output and can be wire-Ored with the

other open drain or open collector outputs.

High Reference Terminal

for Potentiometer 0

21

22

3

4

R_H0

Wiper Terminal for

Potentiometer 0

R_W0

A2

Device Address

23

24

1

5

6

7

8

A0, A1, A2, A3: Device Address Inputs

¯¯¯

WP

Write Protection

These inputs set the device address when addressing

multiple devices. A total of sixteen devices can be

addressed on a single bus. A match in the slave

address must be made with the address input in order

to initiate communication with the CAT5409.

Serial Data Input/Output

Device Address

SDA

A1

2

Low Reference Terminal

for Potentiometer 1

3

4

5

9

R_L1

R_H1

R_W1

High Reference Terminal

for Potentiometer 1

R_H, R_L: Resistor End Points

The four sets of R_Hand R_Lpins are equivalent to the

terminal connections on a mechanical potentiometer.

10

11

Wiper Terminal for

Potentiometer 1

R_W: Wiper

Ground

6

7

12

13

GND

NC

The four R_Wpins are equivalent to the wiper terminal of

a mechanical potentiometer.

No Connect

Wiper Terminal for

Potentiometer 2

8

9

14

15

16

R_W2

R_H2

R_L2

¯¯¯

WP: Write Protect Input

High Reference Terminal

for Potentiometer 2

¯¯¯

The WP pin when tied low prevents non-volatile writes

to the data registers (change of wiper control register is

allowed) and when tied high or left floating normal

read/write operations are allowed. See Write Protection

on page 7 for more details.

Low Reference Terminal

for Potentiometer 2

10

Bus Serial Clock

Device Address

No Connect

11

12

13

14

17

18

19

20

SCL

A3

NC

A0

Device Address, LSB

Wiper Terminal for

Potentiometer 3

15

16

21

22

R_W3

R_H3

High Reference Terminal

for Potentiometer 3

Low Reference Terminal

for Potentiometer 3

17

18

23

24

R_L3

NC

No Connect

DEVICE OPERATION

The CAT5409 is four resistor arrays integrated with I²C serial interface logic, four 6-bit wiper control registers and

sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements

connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical

potentiometer (R_Hand R_L). R_Hand R_Lare symmetrical and may be interchanged. The tap positions between and

at the ends of the series resistors are connected to the output wiper terminals (R_W) by a CMOS transistor switch.

Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the

value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile

memory data registers via the I²C bus. Additional instructions allows data to be transferred between the wiper

control registers and each respective potentiometer's non-volatile data registers. Also, the device can be

instructed to operate in an "increment/decrement" mode.

Doc. No. MD-2010 Rev. K

2

Characteristics subject to change without notice

CAT5409

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Parameters

Ratings

-55 to +125

-65 to +150

-2.0 to +V_CC+ 2.0

-2.0 to +7.0

1.0

Units

ºC

Temperature Under Bias

Storage Temperature

°C

V

(1) (2)

Voltage on Any Pin with Respect to V_SS

V_CCwith Respect to Ground

V

Package Power Dissipation Capability (T_A= 25ºC)

Lead Soldering Temperature (10sec)

Wiper Current

W

300

ºC

±12

mA

RECOMMENDED OPERATING CONDITIONS

Parameters

V_CC

Ratings

+2.5 to +6

-40 to +85

Units

V

Industrial Temperature

°C

POTENTIOMETER CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Min

Typ

100

50

Max

Symbol Parameter

Test Conditions

Units

kΩ

R_POT

Potentiometer Resistance (-00)

Potentiometer Resistance (-50)

Potentiometer Resistance (-10)

Potentiometer Resistance (-2.5)

kΩ

10

kΩ

2.5

kΩ

Potentiometer Resistance

Tolerance

±20

%

R_POTMatching

1

%

mW

mA

Ω

Power Rating

25°C, each pot

50

I_W

R_W

Wiper Current

±6

Wiper Resistance

Voltage on any R_Hor R_LPin

Resolution

Absolute Linearity ⁽⁵⁾

Relative Linearity ⁽⁶⁾

I_W= ±3mA @ V_CC= 3V

I_W= ±3mA @ V_CC= 5V

V_SS= 0V

300

150

V_CC

R_W

80

Ω

V_TERM

GND

V

1.6

%

LSB ⁽⁷⁾

(8)

R_W(n)(actual)- R_{(n)(expected)}

±1

(8)

R_W(n+1)- [R_{W(n) + LSB}

]

±0.2 LSB ⁽⁷⁾

ppm/ºC

TC_RPOT

TC_RATIO

Temperature Coefficient of R_POT(4)

Ratiometric Temp. Coefficient (4)

C_H/C_L/C_WPotentiometer Capacitances

fc Frequency Response

±300

20

ppm/ºC

pF

MHz

(4)

10/10/25

0.4

R_POT= 50kΩ ⁽⁴⁾

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC

voltage on output pins is V_CC+0.5V, which may overshoot to V_CC+2.0V for periods of less than 20ns.

(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V_CC+1V.

(4) This parameter is tested initially and after a design or process change that affects the parameter.

(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.

(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-

meter. It is a measure of the error in step size.

(7) LSB = R_TOT/ 63 or (R_H- R_L) / 63, single pot.

(8) n = 0, 1, 2, ..., 63

Characteristics subject to change without notice

3

Doc. No. MD-2010 Rev. K

CAT5409

D.C. OPERATING CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

I_CCPower Supply Current

I_SB

Test Conditions

Min

Max

Units

mA

µA

V

f_SCL= 400kHz

1

Standby Current (V_CC= 5.0V)

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN= GND or V_CC, SDA Open

V_IN= GND to V_CC

1

10

I_LI

I_LO

V_OUT= GND to V_CC

10

V_IL

V_IH

V_OL1

-1

V_CCx 0.3

Input High Voltage

V_CCx 0.7 V_CC+ 1.0

0.4

V

Output Low Voltage (V_CC= 3.0V) I_OL= 3 mA

V

CAPACITANCE ⁽¹⁾

T_A= 25ºC, f = 1.0MHz, V_CC= 5V

Symbol Test

Conditions

Max.

Units

pF

C_I/O

C_IN

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, A3, SCL, WP)

V_I/O= 0V

V_IN= 0V

8

6

¯¯¯

pF

A.C. CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

Min

Typ

Max

400

50

Units

kHz

ns

f_SCL

T_I⁽¹⁾

t_AA

Clock Frequency

Noise Suppression Time Constant at SCL, SDA Inputs

SLC Low to SDA Data Out and ACK Out

0.9

µs

Time the bus must be free before a new transmission can

start

(1)

t_BUF

1.2

µs

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

0.6

1.2

0.6

0

µs

ns

µs

ns

µs

ns

t_HIGH

Clock High Period

t_SU:STA

t_HD:DAT

t_SU:DAT

Start Condition SetupTime (for a Repeated Start Condition)

Data in Hold Time

Data in Setup Time

100

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

50

POWER UP TIMING ⁽¹⁾

Symbol Parameter

Max

Units

ms

t_PUR

t_PUW

Power-up to Read Operation

Power-up to Write Operation

1

ms

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. MD-2010 Rev. K

4

Characteristics subject to change without notice

CAT5409

WRITE CYCLE LIMITS

Symbol

Parameter

Max

Units

t_WR

Write Cycle Time

5

ms

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write

cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Reference Test Method

Min

1,000,000

100

Max

Units

Cycles/Byte

Years

V

(1)

N_END

Endurance

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(1)

T_DR

Data Retention

ESD Susceptibility

Latch-Up

(1)

V_ZAP

2000

(1) (2)

I_LTH

100

mA

Figure 1. Bus Timing

t

R

F

HIGH

t

LOW

SCL

t

HD:DAT

SU:STA

t

HD:STA

SU:DAT

SU:STO

SDA IN

t

BUF

t

DH

AA

SDA OUT

Figure 2. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

t

WR

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 3. Start/Stop Timing

SDA

SCL

START CONDITION

STOP CONDITION

Notes:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) _PURand t_PUWare delays required from the time V_CCis stable until the specified operation can be initiated.

t

Characteristics subject to change without notice

5

Doc. No. MD-2010 Rev. K

CAT5409

most significant bits of the 8-bit slave address are

fixed as 0101 for the CAT5409 (see Figure 5). The

next four significant bits (A3, A2, A1, A0) are the

device address bits and define which device the

Master is accessing. Up to sixteen devices may be

individually addressed by the system. Typically, +5V

and ground are hard-wired to these pins to establish

the device's address.

SERIAL BUS PROTOCOL

The following defines the features of the I²C bus

protocol:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high will

be interpreted as a START or STOP condition.

After the Master sends a START condition and the

slave address byte, the CAT5409 monitors the bus

and responds with an acknowledge (on the SDA line)

when its address matches the transmitted slave

address.

The device controlling the transfer is a master,

typically a processor or controller, and the device

being controlled is the slave. The master will always

initiate data transfers and provide the clock for both

transmit and receive operations. Therefore, the

CAT5409 will be considered a slave device in all

applications.

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

Acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8

bits of data.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT5409 monitors the

SDA and SCL lines and will not respond until this

condition is met.

The CAT5409 responds with an acknowledge after

receiving a START condition and its slave address. If

the device has been selected along with a write

operation, it responds with an acknowledge after

receiving each 8-bit byte.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

When the CAT5409 is in a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the

line for an acknowledge. Once it receives this

acknowledge, the CAT5409 will continue to transmit

data. If no acknowledge is sent by the Master, the

device terminates data transmission and waits for a

STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

Figure 4. Acknowledge Timing

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Doc. No. MD-2010 Rev. K

6

Characteristics subject to change without notice

CAT5409

host's write operation, the CAT5409 initiates the

internal write cycle. ACK polling can be initiated

immediately. This involves issuing the start condition

followed by the slave address. If the CAT5409 is still

busy with the write operation, no ACK will be returned.

If the CAT5409 has completed the write operation, an

ACK will be returned and the host can then proceed

with the next instruction operation.

WRITE OPERATIONS

In the Write mode, the Master device sends the

START condition and the slave address information to

the Slave device. After the Slave generates an

acknowledge, the Master sends the instruction byte

that defines the requested operation of CAT5409. The

instruction byte consist of a four-bit opcode followed

by two register selection bits and two pot selection

bits. After receiving another acknowledge from the

Slave, the Master device transmits the data to be

written into the selected register. The CAT5409

acknowledges once more and the Master generates

the STOP condition, at which time if a non-volatile

data register is being selected, the device begins an

internal programming cycle to non-volatile memory.

While this internal cycle is in progress, the device will

not respond to any request from the Master device.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the non-volatile

¯¯¯

data registers. If the WP pin is tied to LOW, the data

registers are protected and become read only.

¯¯¯

Similarly, the WP pin going low after start but after

start will interrupt non-volatile write to data registers,

¯¯¯

while the WP pin going low after internal write cycle

has started, will have no effect on any write operation.

The CAT5409 will accept both slave addresses and

instructions, but the data registers are protected from

programming by the device’s failure to send an

acknowledge after data is received.

Acknowledge Polling

The disabling of the inputs can be used to take

advantage of the typical write cycle time. Once the

stop condition is issued to indicate the end of the

Figure 5. Slave Address Bits

CAT5409

0

1

0

1

A3 A2 A1 A0

*

A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

Figure 6. Write Timing

S

SLAVE/DPP

ADDRESS

INSTRUCTION

BYTE

T

A

R

T

S

T

O

P

BUS ACTIVITY:

MASTER

Register

Address

Pot/WCR

Address

DR1 WCRDATA

Fixed

Variable

op code

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

Characteristics subject to change without notice

7

Doc. No. MD-2010 Rev. K

CAT5409

INSTRUCTION AND REGISTER

DESCRIPTION

INSTRUCTION BYTE

SLAVE ADDRESS BYTE

The next byte sent to the CAT5409 contains the

instruction and register pointer information. The four

most significant bits used provide the instruction

opcode I [3:0]. The R1 and R0 bits point to one of the

four data registers of each associated potentiometer.

The least two significant bits point to one of four Wiper

Control Registers. The format is shown in Table 2.

The first byte sent to the CAT5409 from the master/

processor is called the Slave/DPP Address Byte. The

most significant four bits of the Device Type address

are a device type identifier. These bits for the

CAT5409 are fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave

address and must match the physical device address

which is defined by the state of the A3 - A0 input pins

for the CAT5409 to successfully continue the

command sequence. Only the device which slave

address matches the incoming device address sent by

the master executes the instruction. The A3 - A0

inputs can be actively driven by CMOS input signals

or tied to V_CCor V_SS.

Data Register Selection

Data Register Selected

R1

0

R0

0

DR0

DR1

DR2

DR3

0

1

0

1

Table 1. Identification Byte Format

Device Type

Identifier

Slave Address

ID3

0

ID2

1

ID1

0

ID0

A3

A2

A1

A0

(LSB)

1

(MSB)

Table 2. Instruction Byte Format

Instruction

Opcode

Data Register

Selection

WCR/Pot Selection

I3

I2

I1

I0

R1

R0

P1

P0

(MSB)

(LSB)

Doc. No. MD-2010 Rev. K

8

Characteristics subject to change without notice

CAT5409

Registers is a non-volatile operation and will take a

maximum of 5ms.

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can

be used as standard memory locations for system

parameters or user preference data.

The CAT5409 contains four 6-bit Wiper Control

Registers, one for each potentiometer. The Wiper

Control Register output is decoded to select one of 64

switches along its resistor array. The contents of the

WCR can be altered in four ways: it may be written by

the host via Write Wiper Control Register instruction; it

may be written by transferring the contents of one of

four associated Data Registers via the XFR Data

Register instruction, it can be modified one step at a

time by the Increment/decrement instruction (see

Instruction section for more details). Finally, it is

loaded with the content of its data register zero (DR0)

upon power-up.

INSTRUCTIONS

Four of the nine instructions are three bytes in length.

These instructions are:

— Read Wiper Control Register – read the current

wiper position of the selected potentiometer in the

WCR

— Write Wiper Control Register – change current

wiper position in the WCR of the selected

potentiometer

The Wiper Control Register is a volatile register that

loses its contents when the CAT5409 is powered-

down. Although the register is automatically loaded

with the value in DR0 upon power-up, this may be

different from the value present at power-down.

— Read Data Register – read the contents of the

selected Data Register

— Write Data Register – write a new value to the

selected Data Register

The basic sequence of the three byte instructions is

illustrated in Figure 8. These three-byte instructions

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper.

The response of the wiper to this action will be de-

layed by t_WRL. A transfer from the WCR (current wiper

Data Registers (DR)

Each potentiometer has four 6-bit non-volatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Control

Register. Any data changes in one of the Data

Table 3. Instruction Set

Note: 1/0 = data is one or zero

Instruction Set

Instruction

Operation

I3 I2 I1 I0 R1 R0

WCR1/ P1

WCR0/ P0

1

0

1

0

1/0

Read Wiper Control

Register

Read the contents of the Wiper Control

Register pointed to by P1-P0

1

0

1

0

1/0

Write Wiper Control

Register

Write new value to the Wiper Control

Register pointed to by P1-P0

1

0

1

0

1

0

1/0 1/0

1/0

Read the contents of the Data Register

pointed to by P1-P0 and R1-R0

Write new value to the Data Register

pointed to by P1-P0 and R1-R0

Read Data Register

Write Data Register

Transfer the contents of the Data Register

pointed to by P1-P0 and R1-R0 to its

associated Wiper Control Register

XFR Data Register to

Wiper Control Register

1

0

1

0

1/0 1/0

1/0

XFR Wiper Control

Register to Data

Register

Transfer the contents of the Wiper Control

Register pointed to by P1-P0 to the Data

Register pointed to by R1-R0

Gang XFR Data

Registers to Wiper

Control Registers

Transfer the contents of the Data Registers

pointed to by R1-R0 of all four pots to their

respective Wiper Control Registers

0

1

1/0 1/0

0

Gang XFR Wiper

Control Registers to

Data Register

Transfer the contents of both Wiper Control

Registers to their respective data Registers

pointed to by R1-R0 of all four pots

1

0

1

0

1/0

Increment/Decrement

Wiper Control Register

Enable Increment/decrement of the Control

Latch pointed to by P1-P0

Characteristics subject to change without notice

9

Doc. No. MD-2010 Rev. K

CAT5409

— Global XFR Data Register to Wiper Control

Register

position), to a Data Register is a write to non-volatile

memory and takes a minimum of t_WRto complete. The

transfer can occur between one of the four poten-

tiometers and one of its associated registers; or the

transfer can occur between all potentiometers and

one associated register.

This transfers the contents of all specified Data

Registers to the associated Wiper Control

Registers.

— Global XFR Wiper Counter Register to Data

Register

This transfers the contents of all Wiper Control

Registers to the specified associated Data

Registers.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 7. These instructions

transfer data between the host/processor and the

CAT5409; either between the host and one of the data

registers or directly between the host and the Wiper

Control Register. These instructions are:

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5

and 9). The Increment/Decrement command is

different from the other commands. Once the

command is issued and the CAT5409 has responded

with an acknowledge, the master can clock the

selected wiper up and/or down in one segment steps;

thereby providing a fine tuning capability to the host.

For each SCL clock pulse (t_HIGH) while SDA is HIGH,

the selected wiper will move one resistor segment

towards the R_Hterminal. Similarly, for each SCL clock

pulse while SDA is LOW, the selected wiper will move

one resistor segment towards the R_Lterminal.

— XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

Register to the associated Wiper Control Register.

— XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

Control Register to the specified associated Data

Register.

See Instructions format for more detail.

Figure 7. Two-Byte Instruction Sequence

SDA

0

1

0

1

ID3 ID2 ID1 ID0

S

A2 A1 A0

S

T

A

R

T

A3

A I3 I2 I1

I0

R1 R0 P1 P0

A

C

K

C

K

T

O

P

Internal

Address

Instruction

Opcode

Register

Address

Pot/WCR

Address

Device ID

Figure 8. Three-Byte Instruction Sequence

SDA

0

1

0

1

S

T

A

R

T

I3

ID3 ID2

ID0

A

C

K

I2

I1

P1 P0

I0 R1 R0

A

C

K

D7 D6 D5 D4 D3 D2 D1 D0

A

C

K

S

T

ID1

A3 A2 A1 A0

O

P

Internal

Address

Device ID

WCR[7:0]

or

Data Register D[7:0]

Instruction

Opcode

Data

Pot/WCR

Register Address

Address

Figure 9. Increment/Decrement Instruction Sequence

0

1

0

1

SDA

ID3 ID2 ID1 ID0

Device ID

I1

A3 A2 A1 A0

I3

I2

I0

R1 R0 P1 P0

S

T

A

R

T

A

C

K

A

C

K

I

D

E

C

1

S

I

D

N

C

1

N

C

2

T

O

P

N

C

n

E

C

n

Internal

Address

Instruction

Opcode

Pot/WCR

Address

Data

Register

Address

Doc. No. MD-2010 Rev. K

10

Characteristics subject to change without notice

CAT5409

Figure 10. Increment/Decrement Timing Limits

INC/DEC

Command

Issued

t

WRID

SCL

SDA

Voltage Out

R

W

INSTRUCTION FORMAT

Read Wiper Control Register (WCR)

S

T

A

R

T

A

C

K

A

C

K

A

C

K

S

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

DATA

T

O

P

0

1

0

1

0

1

0

1

0

1

0

P1 P0

7

0

6

0

5

4

3

2

1

0

Write Wiper Control Register (WCR)

S

T

A

R

T

A

C

K

A

C

K

A

C

K

S

T

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

DATA

0

1

0

1

0

P1 P0

7

0

6

0

5

4

3

2

1

0

O

P

Read Data Register (DR)

S

T

A

C

K

A

S

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

R1 R0 P1 P0

DATA

C

K

C

K

T

O

P

0

1

0

1

7

6

5

4

3

2

1

0

A

R

T

0

Write Data Register (DR)

S

T

A

C

K

A

C

K

A

C

K

S

T

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

R1 R0 P1 P0

DATA

0

1

0

1

0

7

0

6

0

5

4

3

2

1

0

A

R

T

O

P

Characteristics subject to change without notice

11

Doc. No. MD-2010 Rev. K

CAT5409

INSTRUCTION FORMAT (continued)

Global Transfer Data Register (DR) to Wiper Control Register (WCR)

S

T

A

C

K

A

C

K

S

T

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

R1 R0

0

1

0

1

0

1

0

A

R

T

O

P

Global Transfer Wiper Control Register (WCR) to Data Register (DR)

S

T

A

C

K

A

C

K

S

T

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

R1 R0

0

1

0

1

0

A

R

T

O

P

Transfer Wiper Control Register (WCR) to Data Register (DR)

S

T

A

C

K

A

C

K

S

T

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

R1 R0 P1 P0

0

1

0

1

0

A

R

T

O

P

Transfer Data Register (DR) to Wiper Control Register (WCR)

S

T

A

C

K

A

C

K

S

T

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

R1 R0 P1 P0

0

1

0

1

0

1

A

R

T

O

P

Increment (I)/Decrement (D) Wiper Control Register (WCR)

S

T

A

C

K

A

S

T

DEVICE ADDRESSES

A3 A2 A1 A0

INSTRUCTION

DATA

. . .

C

K

0

1

0

1

0

1

0

P1 P0

I/D I/D

A

R

T

O

P

Note:

(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.

Doc. No. MD-2010 Rev. K

12

Characteristics subject to change without notice

CAT5409

PACKAGE OUTLINE DRAWINGS

SOIC 24-Lead 300mils (W) ⁽¹⁾⁽²⁾

SYMBOL

MIN

2.35

0.10

2.05

0.31

0.20

15.20

10.11

7.34

NOM

MAX

A

A1

A2

b

2.65

0.30

2.55

0.51

0.33

15.40

10.51

7.60

E1

E

c

D

E

E1

e

1.27 BSC

h

0.25

0.40

0°

0.75

1.27

8°

b

e

L

θ

PIN#1 IDENTIFICATION

θ1

5°

15°

TOP VIEW

h

D

h

θ1

A2

θ

A

θ1

L

c

A1

SIDE VIEW

END VIEW

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

Notes:

(1) All dimensions in millimeters. Angle in degrees.

(2) Compiles with JEDEC standard MS-013.

Characteristics subject to change without notice

13

Doc. No. MD-2010 Rev. K

CAT5409

TSSOP 24-Lead 4.4mm (Y) ⁽¹⁾⁽²⁾

b

SYMBOL

MIN

NOM

MAX

1.20

0.15

1.05

0.30

0.20

7.90

6.55

4.50

A

A1

A2

b

0.05

0.80

0.19

0.09

7.70

6.25

4.30

c

E1

E

D

7.80

6.40

E

E1

e

4.40

0.65 BSC

1.00 REF

0.60

L

L1

θ1

0.50

0°

0.70

8°

e

TOP VIEW

D

c

A2

A1

A

θ1

L1

L

SIDE VIEW

END VIEW

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

Notes:

(1) All dimensions in millimeters. Angle in degrees.

(2) Compiles with JEDEC standard MO-153.

Doc. No. MD-2010 Rev. K

14

Characteristics subject to change without notice

CAT5409

EXAMPLE OF ORDERING INFORMATION⁽¹⁾

Prefix

Device # Suffix

CAT

5409

W

I

-00

- T1

Package

W: SOIC

Y: TSSOP

Temperature Range

I = Industrial (-40ºC to 85ºC)

Resistance

25: 2.5kΩ

10: 10kΩ

Tape & Reel

T: Tape & Reel

1: 1,000/Reel – SOIC

2: 2,000/Reel – TSSOP

Company ID

50: 50kΩ

00: 100kΩ

Product Number

5409

ORDERING PART NUMBER

Part Number

Resistance

Package

CAT5409WI-25

CAT5409WI-10

CAT5409WI-50

CAT5409WI-00

CAT5409YI-25

CAT5409YI-10

CAT5409YI-50

CAT5409YI-00

2.5kΩ

10kΩ

50kΩ

100kΩ

2.5kΩ

10kΩ

50kΩ

100kΩ

SOIC

TSSOP

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-free).

(2) The standard lead finish is Matte-Tin.

(3) The device used in the above example is a CAT5409WI-00-T1 (SOIC, Industrial Temperature, 100kΩ, Tape & Reel, 1,000/Reel).

(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.

Characteristics subject to change without notice

15

Doc. No. MD-2010 Rev. K

REVISION HISTORY

Date

Rev. Reason

10/8/2003

H

Updated Features

Updated Description

Changed Preliminary designation to Final

Eliminated Commercial temp range in all areas

04/29/06

I

¯¯¯

Updated WP Pin Description

Updated notes in Absolute Max Ratings and Potentiometer Characteristics

Deleted BGA package

Updated Potentiometer Characteristics table

Update Package Outline Drawings

Updated Example of Ordering Information

Added MD- to document number

02/05/2008

04/07/2008

J

Change 2-wire with I²C

Update Ordering Part Number table

K

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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where

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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled

"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical

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Corporate Headquarters

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Santa Clara, CA 95054

Phone: 408.542.1000

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www.catsemi.com

Document No: MD-2010

Revision:

K

Issue date:

04/07/08