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January 1993  
Revised March 2005  
74ABT273  
Octal D-Type Flip-Flop  
General Description  
Features  
The ABT273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
■ Eight edge-triggered D-type flip-flops  
■ Buffered common clock  
■ Buffered, asynchronous Master Reset  
■ See ABT377 for clock enable version  
■ See ABT373 for transparent latch version  
■ See ABT374 for 3-STATE version  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
■ Output sink capability of 64 mA, source capability of  
32 mA  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
■ Guaranteed latchup protection  
■ High impedance glitch free bus loading during entire  
power up and power down cycle  
■ Non-destructive hot insertion capability  
■ Disable time less than enable time to avoid bus conten-  
tion  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74ABT273CSC  
74ABT273CSJ  
74ABT273CMSA  
74ABT273CMTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MSA20  
MTC20  
MTC20  
74ABT273CMTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
D0–D7  
MR  
Data Inputs  
Master Reset (Active LOW)  
Clock Pulse Input (Active Rising Edge)  
Data Outputs  
CP  
Q0–Q7  
© 2005 Fairchild Semiconductor Corporation  
DS011549  
www.fairchildsemi.com  
Truth Table  
Operating Mode  
Inputs  
CP  
Output  
Qn  
MR  
Dn  
Reset (Clear)  
Load “1”  
L
H
H
X
X
h
l
L
H
L
Load “0”  
H
h
L
I
HIGH Voltage Level steady state  
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition  
LOW Voltage Level steady state  
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition  
Immaterial  
X
LOW-to-HIGH clock transition  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions  
65 C to 150 C  
Storage Temperature  
Ambient Temperature under Bias  
Junction Temperature under Bias  
VCC Pin Potential to Ground Pin  
Input Voltage (Note 3)  
55 C to 125 C  
55 C to 150 C  
0.5V to 7.0V  
Free Air Ambient Temperature  
Supply Voltage  
40 C to 85 C  
4.5V to 5.5V  
Minimum Input Edge Rate ( V/ t)  
Data Input  
0.5V to 7.0V  
50 mV/ns  
20 mV/ns  
Input Current (Note 3)  
30 mA to 5.0 mA  
Enable Input  
Voltage Applied to Any Output  
in the Disabled or  
Power-Off State  
0.5V to 4.75V  
0.5V to VCC  
in the HIGH State  
Current Applied to Output  
in LOW State (Max)  
twice the rated IOL (mA)  
500 mA  
Note 2: Absolute maximum ratings are values beyond which the device  
may be damaged or have its useful life impaired. Functional operation  
under these conditions is not implied.  
DC Latchup Source Current  
(Across Comm Operating Range)  
Over Voltage Latchup  
Note 3: Either voltage limit or current limit is sufficient to protect inputs.  
VCC 4.5V  
DC Electrical Characteristics  
V
Symbol  
Parameter  
Input HIGH Voltage  
Min  
Typ  
Max  
Units  
Conditions  
Recognized HIGH Signal  
Recognized LOW Signal  
CC  
V
V
V
V
2.0  
V
V
V
IH  
Input LOW Voltage  
0.8  
1.2  
IL  
Input Clamp Diode Voltage  
Output HIGH Voltage  
Min  
Min  
Min  
Max  
Max  
I
I
I
I
18 mA  
3 mA  
CD  
OH  
IN  
2.5  
2.0  
OH  
OH  
OL  
V
V
A
A
32 mA  
V
Output LOW Voltage  
Input HIGH Current  
0.55  
64 mA  
OL  
I
I
I
1
1
7
V
V
V
2.7V (Note 4)  
IH  
IN  
IN  
IN  
V
CC  
Input HIGH Current  
Breakdown Test  
7.0V  
BVI  
IL  
Input LOW Current  
1
1
V
V
0.5V (Note 4)  
0.0V  
IN  
A
V
Max  
0.0  
IN  
V
Input Leakage Test  
4.75  
100  
I
1.9  
A
ID  
ID  
All Other Pins Grounded  
I
I
I
I
I
Output Short-Circuit Current  
Output HIGH Leakage Current  
Power Supply Current  
275  
50  
mA  
A
Max  
Max  
Max  
Max  
Max  
V
V
0.0V  
OS  
OUT  
V
CEX  
CCH  
CCL  
CCT  
OUT  
CC  
50  
A
All Outputs HIGH  
All Outputs LOW  
Power Supply Current  
30  
mA  
mA  
Maximum I /Input  
Outputs Enabled  
No Load  
1.5  
V
V
2.1V  
CC  
I
CC  
Data Input V  
V
2.1V  
I
CC  
All Others at V or GND  
CC  
I
Dynamic I  
0.3  
mA/  
Outputs Open (Note 5)  
CCD  
CC  
Max  
MHz  
One Bit Toggling, 50% Duty Cycle  
Note 4: Guaranteed but not tested.  
Note 5: For 8 bits toggling, I 0.5 mA/MHz.  
CCD  
3
www.fairchildsemi.com  
AC Electrical Characteristics  
(SSOIC package)  
T
25 C  
5.0V  
T
55 C to 125 C  
4.5V to 5.5V  
T
A
40 C to 85 C  
4.5V to 5.5V  
A
A
V
V
V
CC  
CC  
CC  
Symbol  
Parameter  
Units  
C
50 pF  
C
50 pF  
Max  
C
L
50 pF  
Max  
L
L
Min  
150  
2.0  
Typ  
200  
Max  
Min  
150  
1.0  
Min  
150  
2.0  
f
Maximum Clock Frequency  
Propagation Delay  
MHz  
ns  
MAX  
t
6.0  
6.8  
7.0  
7.5  
6.0  
6.8  
PLH  
t
CP to O  
2.8  
1.0  
2.8  
PHL  
n
t
Propagation Delay  
MR to O  
PHL  
2.5  
7.4  
1.0  
8.2  
2.5  
7.4  
ns  
n
AC Operating Requirements  
T
25 C  
5.0V  
T
55 C to 125 C  
4.5V to 5.5V  
T
A
40 C to 85 C  
4.5V to 5.5V  
A
A
V
V
V
CC  
CC  
CC  
Symbol  
Parameter  
Units  
C
50 pF  
C
50 pF  
Max  
C
L
50 pF  
Max  
L
L
Min  
2.0  
2.5  
1.2  
1.2  
3.3  
3.3  
Max  
Min  
2.0  
2.5  
1.4  
1.4  
3.3  
3.3  
Min  
2.0  
2.5  
1.2  
1.2  
3.3  
3.3  
t (H)  
Setup Time, HIGH  
S
ns  
ns  
ns  
ns  
ns  
t (L)  
or LOW D to CP  
n
S
t (H)  
Hold Time, HIGH  
H
t (L)  
or LOW D to CP  
n
H
t
t
t
(H)  
(L)  
(L)  
Pulse Width, CP,  
HIGH or LOW  
Master Reset Pulse  
Width, LOW  
W
W
W
3.3  
2.0  
3.3  
2.0  
3.3  
2.0  
t
Recovery Time  
MR to CP  
REC  
Capacitance  
(SOIC package)  
Conditions  
25 C  
Symbol  
Parameter  
Typ  
Units  
T
A
C
Input Capacitance  
Output Capacitance  
5
9
pF  
pF  
V
V
0V  
5.0V  
IN  
CC  
CC  
C
(Note 6)  
OUT  
Note 6: C  
is measured at frequency f 1 MHz, per MIL-STD-833, Method 3012.  
OUT  
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4
AC Loading  
*Includes jig and probe capacitance  
FIGURE 2. VM 1.5V  
FIGURE 1. Standard AC Test Load  
Input Pulse Requirements  
Amplitude Rep. Rate  
3.0V 1 MHz  
tW  
tr  
tf  
500 ns  
2.5 ns  
2.5 ns  
FIGURE 3. Test Input Signal Requirements  
AC Waveforms  
FIGURE 6. Propagation Delay Waveforms for  
Inverting and Non-Inverting Functions  
FIGURE 4. Propagation Delay,  
Pulse Width Waveforms  
FIGURE 5. 3-STATE Output HIGH  
and LOW Enable and Disable Times  
FIGURE 7. Setup Time, Hold Time  
and Recovery Time Waveforms  
5
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Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
Package Number MSA20  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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9
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