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HS-26CLV32RH  
TM  
Data Sheet  
August 2000  
File Number 4907  
Radiation Hardened 3.3V Quad Differential  
Line Receiver  
Features  
• Electrically Screened to SMD # 5962-95689  
The Intersil HS-26CLV32RH is a radiation hardened 3.3V  
quad differential line receiver designed for digital data  
transmission over balanced lines, in low voltage, RS-422  
protocol applications. Radiation hardened CMOS processing  
assures low power consumption, high speed, and reliable  
operation in the most severe radiation environments.  
• QML Qualified per MIL-PRF-38535 Requirements  
• 1.2 Micron Radiation Hardened CMOS  
- Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si)(Max)  
2
- Single Event Upset LET . . . . . . . . . . .100MeV/mg/cm )  
- Single Event Latch-up Immune  
The HS-26CLV32RH has an input sensitivity of 200mV (Typ)  
over a common mode input voltage range of -4V to +7V. The  
receivers are also equipped with input fail safe circuitry,  
which causes the outputs to go to a logic “1” when the inputs  
are open. The device has unique inputs that remain high  
impedance when the receiver is disabled or powered-down,  
maintaining signal integrity in multi-receiver applications.  
• Low Stand-by Current. . . . . . . . . . . . . . . . . . . 13mA(Max)  
• Operating Supply Range . . . . . . . . . . . . . . . . 3.0V to 3.6V  
• Enable Input Levels . . . . V > (.7)(V ); V < (.3)(V  
)
IH  
DD  
IL  
DD  
• CMOS Output Levels . . . . . . . . V  
> 2.55V; V < 0.4V  
OH  
OL  
• Input Fail Safe Circuitry  
• High Impedance Inputs when Disabled or Powered-down  
Specifications for Rad Hard QML devices are controlled  
by the Defense Supply Center in Columbus (DSCC). The  
SMD numbers listed here must be used when ordering.  
o
o
• Full -55 C to 125 C Military Temperature Range  
Pinouts  
Detailed Electrical Specifications for these devices are  
contained in SMD 5962-95689. A “hot-link” is provided  
on our homepage for downloading.  
HS1-26CLV32RH 16 LEAD CERAMIC SIDEBRAZE DIP  
MIL-STD-1835: CDIP2-T16  
TOP VIEW  
www.intersil.com/spacedefense/space.asp  
AIN  
AIN  
1
2
3
4
5
6
7
8
16 V  
DD  
Ordering Information  
15 BIN  
TEMP.  
RANGE  
AOUT  
ENABLE  
COUT  
CIN  
14 BIN  
13 BOUT  
12 ENABLE  
11 DOUT  
10 DIN  
o
ORDERING NO.  
5962F9568902QEC  
5962F9568902QXC  
5962F9568902V9A  
5962F9568902VEC  
5962F9568902VXC  
INTERNAL MKT. NO.  
HS1-26CLV32RH-8  
HS9-26CLV32RH-8  
HS0-26CLV32RH-Q  
HS1-26CLV32RH-Q  
HS9-26CLV32RH-Q  
( C)  
-55 to 125  
-55 to 125  
25  
CIN  
9
DIN  
GND  
-55 to 125  
-55 to 125  
HS9-26CLV32RH 16 LEAD FLATPACK  
MIL-STD-1835: CDFP4-F16  
TOP VIEW  
HS1-26CLV32RH/PROTO HS1-26CLV32RH/PROTO -55 to 125  
HS9-26CLV32RH/PROTO HS9-26CLV32RH/PROTO -55 to 125  
AIN  
AIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
DD  
Logic Diagram  
BIN  
AOUT  
ENABLE  
COUT  
CIN  
BIN  
ENABLE ENABLE DIN DIN  
CIN CIN  
BIN BIN  
AIN AIN  
BOUT  
ENABLE  
DOUT  
DIN  
+
-
+
-
+
-
+
-
CIN  
GND  
DIN  
DOUT  
COUT  
BOUT  
AOUT  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
1
HS-26CLV32RH  
Die Characteristics  
DIE DIMENSIONS:  
Metallization:  
84 mils x 130 mils x 21 mils  
Bottom: Mo/Tiw  
(2140µm x 3290µm)  
Thickness: 5800Å ±1kÅ  
Top: Al/Si/Cu  
Thickness: 10kÅ ±1kÅ  
INTERFACE MATERIALS:  
Glassivation:  
Worst Case Current Density:  
Type: PSG (Phosphorus Silicon Glass)  
Thickness: 8kÅ ± 1kÅ  
5
2
<2.0 x 10 A/cm  
Bond Pad Size:  
Substrate:  
110µm x 100µm  
AVLSI1RA, Silicon backside, V  
DD  
backside potential  
Metallization Mask Layout  
HS-26CLV32RH  
AIN  
(1)  
V
(16)  
BIN  
(15)  
DD  
(14) B  
IN  
AIN (2)  
(13) B  
OUT  
A
(3)  
OUT  
ENAB (4)  
(12) ENAB  
(11) D  
OUT  
C
(5)  
(6)  
OUT  
(10) D  
IN  
C
IN  
(7)  
(8)  
(9)  
GND  
CIN  
DIN  
2
HS-26CLV32RH  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Intersil Ltd.  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
Mercure Center  
8F-2, 96, Sec. 1, Chien-kuo North,  
Taipei, Taiwan 104  
Republic of China  
TEL: 886-2-2515-8508  
FAX: 886-2-2515-8369  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
3