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A6812  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
Features and Benefits  
▪ Controlled output slew rate  
▪ High-speed data storage  
▪ 60 V minimum output break down  
▪ High data-input rate  
Description  
The A6812 device combines a 20-bit CMOS shift register,  
accompanying data latches and control circuitry with bipolar  
sourcing outputs ,and PNP active pull-downs. Designed  
primarily to drive vacuum-fluorescent displays, the 60 V and  
-40 mA output ratings also allow these devices to be used in  
many other peripheral power driver applications. The A6812  
features an increased data-input rate (compared with the older  
UCN/UCQ5812-F) and a controlled output slew rate.  
▪ PNP active pull-downs  
▪ Low output-saturation voltages  
▪ Low-power CMOS logic and latches  
▪ Improved replacements for TL5812x, UCN5812x, and  
UCQ5812x  
The CMOS shift register and latches allow direct interfacing  
with microprocessor-based systems. With a 3.3 or 5 V logic  
supply, they operate to at least 10 MHz.  
A CMOS serial data output permits cascaded connections in  
applications requiring additional drive lines. Similar devices  
are available as the A6810 (10-bit) and A6818 (32-bit).  
Package:  
The A6812 output source drivers are NPN Darlingtons,  
capable of sourcing up to 40 mA. The controlled output slew  
rate reduces electromagnetic noise, which is an important  
consideration in systems that include telecommunications  
and/or microprocessors and to meet government emissions  
28-pin SOICW  
(Package LW)  
28-pin PLCC  
(EP package)  
Continued on the next page…  
Not to scale  
Functional Block Diagram  
26182.126G  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
Description (continued)  
-EP). Copper lead frames, low logic-power dissipation, and low  
output-saturation voltages allow these drivers to source 25 mA  
from all outputs continuously to more than 43°C (suffix -LW) or  
61°C (suffix -EP).  
regulations. For inter-digit blanking, all output drivers can be  
disabled and all sink drivers turned on with a BLANKING input  
high. The PNP active pull-downs sink at least 2.5 mA.  
Threetemperaturerangesareavailableforoptimumperformancein  
commercial (suffix S-), industrial (suffix E-), or automotive (suffix  
K-) applications. Package styles are provided for surface-mount  
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix  
Each package is available in a lead (Pb) free version, with 100%  
matte tin leadframe plating.  
Selection Guide  
Ambient Temperature, TA  
Part Number  
Pb-free  
Packing  
Package  
(°C)  
A6812EEPTR  
–
800 pieces/13-in. reel  
PLCC  
A6812EEPTR-T  
A6812ELWTR-T  
A6812KLWTR-T  
A6812SEPTR  
Yes  
Yes  
Yes  
–
–40 to 85  
1000 pieces/13-in. reel  
1000 pieces/13-in. reel  
SOIC-W  
SOIC-W  
–40 to 125  
–20 to 85  
800 pieces/13-in. reel  
1000 pieces/13-in. reel  
PLCC  
A6812SEPTR-T  
A6812SLWTR-T  
Yes  
Yes  
SOIC-W  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
2
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
Absolute Maximum Ratings*  
Characteristic  
Symbol  
VDD  
Notes  
Rating  
7
Units  
V
Logic Supply Voltage  
Driver Supply Voltage  
VBB  
60  
V
Input Voltage Range  
VIN  
–0.3 to VDD + 0.3  
–40 to 15  
–40 to 85  
–40 to 125  
–20 to 85  
150  
V
Continuous Output Current Range  
IOUT  
mA  
ºC  
ºC  
ºC  
ºC  
ºC  
Range E  
Range K  
Range S  
Operating Ambient Temperature  
TA  
Maximum Junction Temperature  
Storage Temperature  
TJ(max)  
T
stg  
–65 to 125  
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high  
static electrical charges.  
2.5  
2.0  
SUFFIX 'EP', R  
= 68  
1.5  
1.0  
0.5  
0
Q
JA  
o
C/W  
25  
50  
75  
100  
125  
150  
o
AMBIENT TEMPERATURE IN C  
Dwg. GP-024-2  
Thermal Characteristics  
Characteristic  
Symbol  
Test Conditions*  
Value Units  
Package EP, 1-layer PCB with solder limited to mounting pads  
68  
80  
ºC/W  
ºC/W  
Package Thermal Resistance  
RθJA  
Package LW, 1-layer PCB with solder limited to mounting pads  
*Additional thermal information available on the Allegro website  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
3
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
EP Package  
LW Package  
LOGIC  
SUPPLY  
LOAD  
SUPPLY  
28  
27  
1
2
3
V
V
DD  
BB  
SERIAL  
DATA IN  
SERIAL  
DATA OUT  
26 OUT  
25 OUT  
24 OUT  
23 OUT  
22 OUT  
OUT  
20  
1
2
3
4
5
25  
5
OUT  
2
OUT  
4
OUT  
19  
18  
5
6
OUT  
18  
6
7
8
24  
23  
OUT  
17  
OUT  
16  
7
OUT  
15  
8
21  
20  
19  
18  
OUT  
OUT  
OUT  
22  
21  
20  
19  
6
7
8
OUT  
14  
9
9
10  
11  
12  
13  
14  
OUT  
13  
10  
OUT  
OUT  
OUT  
12  
11  
9
17 OUT  
10  
11  
OUT  
8
OUT  
12  
16  
BLANKING  
GROUND  
BLNK  
STROBE  
ST  
CLK  
2
15 CLOCK  
Dwg. PP-029-7  
Dwg. PP-059-1  
TYPICAL INPUT CIRCUIT  
TYPICAL OUTPUT DRIVER  
V
DD  
V
BB  
IN  
OUT  
N
Dwg. EP-021-19  
Dwg. EP-010-5  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
4
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
TRUTH TABLE  
Serial  
Data Clock  
Input Input I  
Shift Register Contents  
Serial  
Data Strobe  
Output Input  
Latch Contents  
Output Contents  
... I  
I
I
...  
I
I
I
I
I
...  
I
I
Blanklng  
I
I
I
1
2
3
N-1  
N
1
2
3
N-1  
N
1
2 3  
N-1  
I
N
H
L
H
L
R
R
R
X
R
R
R
X
...  
...  
...  
...  
...  
R
R
R
X
R
R
R
X
R
R
R
X
1
1
2
2
2
3
N-2  
N-2  
N-1  
N-1  
N-1  
N
N-1  
N-1  
N
X
R
1
X
L
R
R
R
...  
...  
...  
R
R
1
2
3
N-1  
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
L
P
L
P
L
... P  
... L  
P
L
1
2
3
N-1  
N
N
1
2
3
N-1  
N
1
2
3
N-1  
N
X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
5
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature range (A6812E- or  
A6812K-), VBB = 60 V; unless otherwise noted  
Limits @ V  
= 3.3 V Limits @ V  
= 5 V  
DD  
DD  
Characteristic  
Symbol  
Test Conditions  
= 0 V  
Mln.  
—
Typ.  
Max.  
-15  
—
Min. Typ. Max.  
<-0.1 -15  
Units  
μA  
V
Output Leakage Current  
Output Voltage  
I
V
<-0.1  
58.3  
1.0  
—
CEX  
OUT  
V
V
I
I
= -25 mA  
= 1 mA  
57.5  
—
57.5 58.3  
—
1.5  
—
OUT(1)  
OUT(0)  
OUT(0)  
OUT  
OUT  
1.5  
—
—
2.5  
3.3  
—
1.0  
5.0  
—
V
Output Pull-Down Current  
Input Voltage  
I
V
= 5 V to V  
2.5  
2.2  
—
5.0  
mA  
V
OUT  
BB  
V
V
—
—
—
IN(1)  
IN(0)  
IN(1)  
IN(0)  
—
1.1  
1.0  
—
1.7  
V
Input Current  
I
I
V
V
= V  
—
<0.01  
—
<0.01 1.0  
<-0.01 -1.0  
μA  
μA  
V
IN  
DD  
= 0 V  
—
<-0.01 -1.0  
—
IN  
Input Clamp Voltage  
V
I
I
I
= -200 μA  
—
-0.8  
3.05  
0.15  
—
-1.5  
—
—
-0.8  
4.75  
0.15  
—
-1.5  
—
IK  
IN  
Serial Data Output Voltage  
V
V
= -200 μA  
= 200 μA  
2.8  
—
4.5  
—
V
OUT(1)  
OUT(0)  
OUT  
OUT  
0.3  
—
0.3  
—
V
Maximum Clock Frequency  
Logic Supply Current  
f
10*  
—
10*  
—
MHz  
mA  
mA  
mA  
μA  
μs  
μs  
μs  
μs  
μs  
μs  
c
I
All Outputs High  
All Outputs Low  
0.25  
0.25  
3.0  
0.2  
0.7  
1.8  
0.7  
1.8  
—
0.75  
0.75  
6.0  
20  
0.3  
0.3  
3.0  
0.2  
0.7  
1.8  
0.7  
1.8  
—
1.0  
1.0  
6.0  
20  
DD(1)  
DD(0)  
I
—
—
Load Supply Current  
I
All Outputs High, No Load  
All Outputs Low  
—
—
BB(1)  
BB(0)  
I
—
—
Blanking-to-Output Delay  
Strobe-to-Output Delay  
t
C = 30 pF, 50% to 50%  
—
2.0  
3.0  
2.0  
3.0  
12  
—
2.0  
3.0  
2.0  
3.0  
12  
dis(BQ)  
L
t
C = 30 pF, 50% to 50%  
L
—
—
en(BQ)  
t
R = 2.3 kΩ, C 30 pF  
—
—
p(STH-QL)  
L
L
t
R = 2.3 kΩ, C 30 pF  
—
—
p(STH-QH)  
L
L
Output Fall Time  
Output Rise Time  
t
f
R = 2.3 kΩ, C 30 pF  
2.4  
2.4  
2.4  
2.4  
L
L
t
r
R = 2.3 kΩ, C 30 pF  
—
12  
—
12  
L
L
Output Slew Rate  
dV/dt  
R = 2.3 kΩ, C 30 pF  
4.0  
—
—
20  
—
4.0  
—
—
20  
—
V/μs  
L
L
Clock-to-Serial Data Out Delay t  
I
= ±200 μA  
50  
50  
ns  
p(CH-SQX)  
OUT  
Negative current is defined as coming out of (sourcing) the specified device terminal.  
Typical data is is for design information only and is at TA = +25°C.  
* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
6
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
TIMING REQUIREMENTS and SPECIFICATIONS  
(Logic Levels are VDD and Ground)  
C
50%  
B
CLOCK  
A
SERIAL  
DATA IN  
DATA  
50%  
t
p(CH-SQX)  
SERIAL  
DATA OUT  
DATA  
50%  
D
E
50%  
STROBE  
BLANKING  
LOW = ALL OUTPUTS ENABLED  
t
p(STH-QH)  
t
p(STH-QL)  
90%  
DATA  
OUT  
N
10%  
Dwg. WP-029  
HIGH = ALL OUTPUTS BLANKED (DISABLED)  
50%  
BLANKING  
t
dis(BQ)  
t
t
f
r
t
90%  
50%  
en(BQ)  
OUT  
N
DATA  
10%  
Dwg. WP-030A  
data information towards the SERIAL DATA OUTPUT. The  
SERIAL DATA must appear at the input prior to the rising edge  
of the CLOCK input waveform.  
A. Data Active Time Before Clock Pulse  
(Data Set-Up Time), tsu(D) ........................................ 25 ns  
B. Data Active Time After Clock Pulse  
(Data Hold Time), th(D) ............................................. 25 ns  
C. Clock Pulse Width, tw(CH) .............................................. 50 ns  
Information present at any register is transferred to the re-  
spective latch when the STROBE is high (serial-to-parallel con-  
version). The latches will continue to accept new data as long  
as the STROBE is held high. Applications where the latches are  
bypassed (STROBE tied high) will require that the BLANKING  
input be high during serial data entry.  
D. Time Between Clock Activation and Strobe, tsu(C) ...... 100 ns  
E. Strobe Pulse Width, tw(STH) ........................................... 50 ns  
NOTE – Timing is representative of a 10 MHz clock. Higher  
speeds may be attainable with increased supply voltage; op-  
eration at high temperatures will reduce the specified maximum  
clock frequency.  
When the BLANKING input is high, the output source driv-  
ers are disabled (OFF); the pnp active pull-down sink drivers are  
ON. The information stored in the latches is not affected by the  
BLANKING input. With the BLANKING input low, the outputs  
are controlled by the state of their respective latches.  
Serial Data present at the input is transferred to the shift  
register on the logic “0” to logic “1” transition of the CLOCK  
input pulse. On succeeding CLOCK pulses, the registers shift  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
7
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
EP Package, 28-Pin PLCC  
12.45±0.13  
11.51±0.08  
0.51  
2
1
28  
A
5.21±0.36  
5.21±0.36  
12.45±0.13  
11.51±0.08  
0.51 MIN  
0.74±0.08  
+0.20  
–0.18  
4.37  
28X  
C
SEATING  
PLANE  
0.10  
C
0.43±0.10  
1.27  
5.21±0.36  
5.21±0.36  
For Reference Only  
(reference JEDEC MS-018 AB)  
Dimensions in millimeters  
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions  
Exact case and lead configuration at supplier discretion within limits shown  
A
Terminal #1 mark area  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
8
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com  
DABiC-IV 20-Bit Serial-Input  
Latched Source Driver  
A6812  
LW Package, 28-Pin SOICW  
17.90±0.20  
4° ±4  
0.27  
28  
28  
+0.07  
–0.06  
2.20  
10.30±0.33  
9.60  
7.50±0.10  
A
+0.44  
–0.43  
0.84  
1
2
1
2
0.65  
1.27  
0.25  
PCB Layout Reference View  
B
28X  
C
SEATING PLANE  
GAUGE PLANE  
SEATING  
PLANE  
0.1  
C
0.41 ±0.10  
1.27  
2.65 MAX  
0.20 ±0.10  
Terminal #1 mark area  
A
B
For Reference Only  
(Reference JEDEC MS-013 AE)  
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions  
Exact case and lead configuration at supplier discretion within limits shown  
Reference pad layout (reference IPC SOIC127P1030X265-28M)  
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary  
to meet application process requirements and PCB layout tolerances  
Copyright ©2000-2009, Allegro MicroSystems, Inc.  
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.  
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-  
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the  
information being relied upon is current.  
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the  
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.  
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;  
nor for any infringement of patents or other rights of third parties which may result from its use.  
For the latest version of this document, visit our website:  
www.allegromicro.com  
Allegro MicroSystems, Inc.  
115 Northeast Cutoff  
9
Worcester, Massachusetts 01615-0036 U.S.A.  
1.508.853.5000; www.allegromicro.com