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March 2007  
74ABT541  
tm  
Octal Buffer/Line Driver with 3-STATE Outputs  
Features  
General Description  
■ Non-inverting buffers  
The ABT541 is an octal buffer and line driver with  
3-STATE outputs designed to be employed as a memory  
and address driver, clock driver, or bus-oriented trans-  
mitter/receiver. The ABT541 is similar to the ABT244  
with broadside pinout.  
■ Output sink capability of 64mA, source capability of  
32mA  
■ Guaranteed output skew  
■ Guaranteed multiple output switching specifications  
■ Output switching specified for both 50pF and 250pF  
loads  
■ Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
■ Guaranteed latchup protection  
■ High-impedance, glitch-free bus loading during entire  
power up and power down cycle  
■ Nondestructive, hot-insertion capability  
■ Flow-through pinout for ease of PC board layout  
■ Disable time less than enable time to avoid bus  
contention  
Ordering Information  
Package  
Order Number  
74ABT541CSC  
74ABT541CSJ  
Number  
Package Description  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
M20D  
74ABT541CMSA  
74ABT541CMTC  
MSA20  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,  
4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering number.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OE , OE  
Output Enable Input (Active LOW)  
1
2
I –I  
Inputs  
0
7
O –O  
Outputs  
0
7
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
Truth Table  
Inputs  
OE  
OE  
L
I
Outputs  
1
2
L
X
H
L
H
X
X
L
H
Z
Z
L
H
X
L
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Rating  
T
Storage Temperature  
–65°C to +150°C  
–55°C to +125°C  
–55°C to +150°C  
–0.5V to +7.0V  
–0.5V to +7.0V  
–30mA to +5.0mA  
STG  
T
Ambient Temperature Under Bias  
Junction Temperature Under Bias  
A
T
J
V
V
Pin Potential to Ground Pin  
CC  
CC  
(1)  
V
Input Voltage  
Input Current  
IN  
IN  
(1)  
I
V
Voltage Applied to Any Output  
Disabled or Power-Off State  
HIGH State  
O
–0.5V to 5.5V  
–0.5V to V  
CC  
Current Applied to Output in LOW State (Max.)  
DC Latchup Source Current  
Over Voltage Latchup (I/O)  
twice the rated I (mA)  
OL  
–500mA  
10V  
Note:  
1. Either voltage limit or current limit is sufficient to protect inputs.  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
Parameter  
Rating  
T
Free Air Ambient Temperature  
Supply Voltage  
–40°C to +85°C  
A
V
+4.5V to +5.5V  
CC  
∆V / ∆t  
Minimum Input Edge Rate  
Data Input  
50mV/ns  
20mV/ns  
Enable Input  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
2
DC Electrical Characteristics  
Symbol  
Parameter  
Input HIGH Voltage  
V
Conditions  
Min. Typ. Max. Units  
CC  
V
Recognized HIGH Signal  
Recognized LOW Signal  
2.0  
V
V
IH  
V
Input LOW Voltage  
0.8  
IL  
V
V
Input Clamp Diode Voltage  
Output HIGH Voltage  
Min.  
Min.  
I
I
I
I
= –18mA  
= –3mA  
–1.2  
V
CD  
IN  
2.5  
2.0  
V
OH  
OH  
OH  
OL  
= –32mA  
= 64mA  
V
V
Output LOW Voltage  
Input HIGH Current  
Min.  
0.55  
V
OL  
(3)  
I
Max.  
V
V
V
= 2.7V  
1
1
7
µA  
IH  
IN  
IN  
IN  
= V  
CC  
I
Input HIGH Current  
Breakdown Test  
Max.  
Max.  
= 7.0V  
µA  
µA  
BVI  
(3)  
I
Input LOW Current  
V
V
I
= 0.5V  
–1  
–1  
IL  
IN  
= 0.0V  
IN  
V
Input Leakage Test  
0.0  
= 1.9µA, All Other Pins  
4.75  
V
ID  
ID  
Grounded  
I
Output Leakage Current  
Output Leakage Current  
Output Short-Circuit Current  
0–5.5V  
0–5.5V  
Max.  
V
= 2.7V, OE = 2.0V  
10  
–10  
–275  
50  
µA  
µA  
mA  
µA  
OZH  
OUT  
n
I
V
= 0.5V, OE = 2.0V  
OZL  
OUT  
n
I
V
= 0.0V  
–100  
OS  
OUT  
I
Output HIGH Leakage  
Current  
Max.  
V
= V  
CEX  
OUT  
CC  
I
Bus Drainage Test  
0.0  
V
= 5.5V, All Others GND  
100  
50  
µA  
µA  
mA  
µA  
ZZ  
OUT  
I
Power Supply Current  
Power Supply Current  
Power Supply Current  
Max. All Outputs HIGH  
CCH  
I
I
Max. All Outputs LOW  
30  
CCL  
Max. OE = V , All Others at V  
CC  
50  
CCZ  
n
CC  
or Ground  
I
Additional Outputs Enabled  
V = V – 2.1V  
2.5  
2.5  
50  
mA  
mA  
µA  
CCT  
I
CC  
I
/Input  
CC  
Outputs 3-STATE  
Outputs 3-STATE  
Max. Enable Input V = V – 2.1V  
I CC  
Data Input V = V – 2.1V,  
I
CC  
All Others at V or Ground  
CC  
(3)  
I
Dynamic I No Load  
Max  
Outputs Open, OE = GND,  
One-Bit Toggling  
50% Duty Cycle  
0.1  
mA/  
MHz  
CCD  
CC  
n
,
(2)  
Notes:  
2. For 8-bit toggling, I  
< 0.8mA/MHz.  
CCD  
3. Guaranteed, but not tested.  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
3
DC Electrical Characteristics  
SOIC package.  
Conditions  
C = 50pF,  
L
Symbol  
Parameter  
V
R = 500Ω  
Min. Typ. Max. Units  
CC  
L
(4)  
V
Quiet Output Maximum Dynamic V  
Quiet Output Minimum Dynamic V  
5.0  
5.0  
5.0  
T = 25°C  
0.7  
–0.8  
3.1  
1.0  
V
V
V
OLP  
OL  
A
(4)  
V
T = 25°C  
–1.3  
2.7  
OLV  
OL  
A
(5)  
V
Minimum HIGH Level Dynamic Output  
Voltage  
T = 25°C  
OHV  
A
(6)  
V
Minimum HIGH Level Dynamic Input  
Voltage  
5.0  
5.0  
T = 25°C  
2.0  
1.4  
1.1  
V
V
IHD  
A
(6)  
V
Maximum LOW Level Dynamic Input  
Voltage  
T = 25°C  
0.6  
ILD  
A
Notes:  
4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but  
not tested.  
5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not  
tested.  
6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold  
(V ), 0V to threshold (V ). Guaranteed, but not tested.  
ILD  
IHD  
AC Electrical Characteristics  
SOIC and SSOP package.  
T = +25°C,  
CC  
T = –40°C to +85°C,  
A
A
V
= +5V,  
V
= 4.5V–5.5V,  
CC  
C = 50pF  
C = 50pF  
L
L
Symbol  
Parameter  
Min.  
1.0  
1.0  
1.5  
1.5  
1.7  
1.7  
Typ.  
2.0  
2.4  
3.1  
3.7  
3.5  
3.1  
Max.  
3.6  
Min.  
1.0  
1.0  
1.5  
1.5  
1.7  
1.7  
Max.  
3.6  
Units  
t
t
Propagation Delay,  
Data to Outputs  
ns  
PLH  
PHL  
PZH  
3.6  
3.6  
t
Output Enable Time  
6.0  
6.0  
ns  
ns  
t
6.0  
6.0  
PZL  
PHZ  
t
Output Disable Time  
6.1  
6.1  
t
5.6  
5.6  
PLZ  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
4
Extended AC Electrical Characteristics  
SOIC package.  
–40°C to +85°C,  
T = –40°C to +85°C, T = –40°C to +85°C,  
A
V
A
V
V
= 4.5V to 5.5V,  
L
= 4.5V to 5.5V,  
= 4.5V to 5.5V,  
CC  
CC  
CC  
C = 50pF,  
C = 250pF,  
C = 250pF,  
L
L
8 Outputs  
1 Output  
8 Outputs  
(7)  
(8)  
(9)  
Switching  
Switching  
Switching  
Symbol  
Parameter  
Min. Typ. Max.  
Min.  
Max.  
Mi.n  
Max.  
Units  
f
Max Toggle  
100  
MHz  
TOGGLE  
Frequency  
t
t
Propagation Delay,  
Data to Outputs  
1.5  
1.5  
1.5  
1.5  
1.0  
1.0  
5.0  
5.0  
6.5  
6.5  
6.1  
5.6  
1.5  
1.5  
2.5  
2.5  
6.0  
6.0  
7.5  
7.5  
2.5  
2.5  
2.5  
2.5  
8.5  
8.5  
ns  
ns  
ns  
PLH  
PHL  
PZH  
t
Output Enable Time  
9.5  
t
10.5  
PZL  
PHZ  
(10)  
t
Output Disable  
Time  
t
PLZ  
Notes:  
7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described  
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).  
8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors  
in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching  
only.  
9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described  
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load  
capacitors in the standard AC load.  
10. The 3-STATE delays are dominated by the RC network (500Ω, 250pF) on the output and have been excluded from  
the datasheet.  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
5
Skew  
SOIC package.  
T = –40°C to +85°C, T = –40°C to +85°C,  
A
V
A
V
= 4.5V to 5.5V,  
L
= 4.5V to 5.5V,  
L
CC  
CC  
C = 50pF,  
C = 250pF,  
8 Outputs  
8 Outputs  
(11)  
(12)  
Switching  
Max.  
1.3  
Switching  
Symbol  
Parameter  
Max.  
2.3  
Units  
ns  
(13)  
t
t
Pin to Pin Skew, HL Transitions  
Pin to Pin Skew, LH Transitions  
Duty Cycle, LH/HL Skew  
OSHL  
(13)  
1.0  
1.8  
ns  
OSLH  
(14)  
t
2.0  
3.5  
ns  
PS  
(13)  
t
Pin to Pin Skew, LH/HL Transitions  
2.0  
3.5  
ns  
OST  
(15)  
t
Device to Device Skew, LH/HL  
Transitions  
2.0  
3.5  
ns  
PV  
Notes:  
11. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described  
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)  
12. These specifications guaranteed but not tested. The limits represent propagation delays with 250pF load capacitors  
in place of the 50pF load capacitors in the standard AC load.  
13. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate  
outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (t  
), LOW-to-HIGH  
OSHL  
(t  
), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (t  
). The specification is guaranteed  
OSLH  
OST  
but not tested.  
14. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same  
pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the  
guaranteed specification. This specification is guaranteed but not tested.  
15. Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This  
CC  
specification is guaranteed but not tested.  
Capacitance  
Conditions  
Symbol  
Parameter  
T = 25°C  
= 0.0V  
Typ.  
5.0  
Units  
pF  
A
C
Input Capacitance  
Output Capacitance  
V
V
IN  
CC  
(16)  
C
= 5.0V  
9.0  
pF  
OUT  
CC  
Note:  
16. C  
is measured at frequency of f = 1 MHz, per MIL-STD-883, Method 3012.  
OUT  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
6
AC Loading  
*Includes jig and probe capacitance  
Figure 2.Test Input Signal Levels  
Figure 1. Standard AC Test Load  
Amplitude  
Rep. Rate  
t
t
t
f
W
r
3.0V  
1 MHz  
500 ns  
2.5 ns  
2.5 ns  
Figure 3.Test Input Signal Requirements  
AC Waveforms  
Figure 4. Propagation Delay Waveforms for  
Inverting and Non-Inverting Functions  
Figure 6. 3-STATE Output HIGH and  
LOW Enable and Disable Time  
Figure 5. Propagation Delay, Pulse Width Waveforms  
Figure 7. Setup Time, Hold Time and  
Recovery Time Waveforms  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
7
Physical Dimensions  
Dimensions are in inches (millimeters) unless otherwise noted.  
Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
8
Physical Dimensions (Continued)  
Dimensions are in millimeters unless otherwise noted.  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
9
Physical Dimensions (Continued)  
Dimensions are in millimeters unless otherwise noted.  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
10  
Physical Dimensions (Continued)  
Dimensions are in millimeters unless otherwise noted.  
Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
11  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an  
exhaustive list of all such trademarks.  
ACEx®  
TinyLogic®  
TINYOPTO¥  
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TruTranslation¥  
PSerDes¥  
UHC®  
UniFET¥  
VCX¥  
Wire¥  
HiSeC¥  
i-Lo¥  
Programmable Active Droop¥  
QFET®  
QS¥  
QT Optoelectronics¥  
Quiet Series¥  
RapidConfigure¥  
RapidConnect¥  
ScalarPump¥  
SMART START¥  
SPM®  
STEALTH™  
SuperFET¥  
SuperSOT¥-3  
SuperSOT¥-6  
SuperSOT¥-8  
SyncFET™  
Across the board. Around the world.¥  
ActiveArray¥  
Bottomless¥  
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IntelliMAX¥  
ISOPLANAR¥  
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MSX¥  
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CTL™  
Current Transfer Logic™  
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OPTOLOGIC®  
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DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS  
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE  
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER  
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S  
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR  
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,  
which, (a) are intended for surgical implant into the body or  
(b) support or sustain life, and (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in a significant injury of the user.  
device, or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In Design  
This datasheet contains the design specifications for product  
development. Specifications may change in any manner without notice.  
Preliminary  
First Production  
Full Production  
Not In Production  
This datasheet contains preliminary data; supplementary data will be  
published at a later date. Fairchild Semiconductor reserves the right to  
make changes at any time without notice to improve design.  
No Identification Needed  
Obsolete  
This datasheet contains final specifications. Fairchild Semiconductor  
reserves the right to make changes at any time without notice to improve  
design.  
This datasheet contains specifications on a product that has been  
discontinued by Fairchild Semiconductor. The datasheet is printed for  
reference information only.  
Rev. I24  
©1992 Fairchild Semiconductor Corporation  
74ABT541 Rev. 1.4  
www.fairchildsemi.com  
12