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ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
• Fully integrated PLL  
The ICS8431I-21 is a general purpose clock frequency  
synthesizer for IA64/32 application. The VCO operates at a  
frequency range of 250MHz to 700MHz providing an output  
frequency range of 62.5MHz to 350MHz.The output frequency  
can be programmed using the parallel interface, M0 through  
M8 to the configuration logic, and the output divider control  
pin, DIV_SEL. Spread spectrum clocking is programmed via  
the control inputs SSC_CTL0 and SSC_CTL1.  
• Differential 3.3V LVPECL output  
• Crystal oscillator interface  
• Output frequency range: 62.5MHz to 350MHz  
• Crystal input frequency range: 14MHz to 25MHz  
• VCO range: 250MHz to 700MHz  
Programmable features of the ICS8431I-21 support four • Programmable PLL loop divider for generating a variety  
of output frequencies  
operational modes. The four modes are spread spectrum  
clocking (SSC), non-spread spectrum clock and two test  
modes which are controlled by the SSC_CTL[1:0] pins.  
Unlike other synthesizers, the ICS8431I-21 can immedi-  
ately change spread-spectrum operation without having to  
reset the device.  
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation  
for environments requiring ultra low EMI  
• PLL bypass modes supporting in-circuit testing and on-chip  
functional block characterization  
• Cycle-to-cycle jitter: 30ps (maximum)  
• 3.3V supply voltage  
In SSC mode, the output clock is modulated in order to  
achieve a reduction in EMI. In one of the PLL bypass test  
modes, the PLL is disconnected as the source to the differ-  
ential output allowing an external source to be connected  
to the TEST_I/O pin. This is useful for in-circuit testing and  
allows the differential output to be driven at a lower  
frequency throughout the system clock tree. In the other  
PLL bypass mode, the oscillator divider is used as the  
source to both the M and the Fout divide by 2. This is useful  
for characterizing the oscillator and internal dividers.  
• -40°C to 85°C ambient operating temperature  
• Replaces ICS8431I-01  
• Available in both, Standard and RoHS/Lead-Free  
compliant packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
M0  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
nP_LOAD  
VCC  
XTAL_IN  
XTAL_OUT  
nc  
nc  
VCCA  
VEE  
MR  
DIV_SEL  
VCCO  
FOUT  
nFOUT  
VEE  
XTAL_IN  
OSC  
XTAL_OUT  
÷ 16  
PLL  
9
PHASE  
DETECTOR  
SSC_CTL0  
SSC_CTL1  
VEE  
TEST_I/O  
VCC  
10  
11  
12  
13  
14  
÷2  
VCO  
÷4  
FOUT  
nFOUT  
÷ M  
ICS8431I-21  
28-Lead SOIC  
TEST_I/O  
7.5mm x 18.05mm x 2.25mm package body  
M Package  
TopView  
SSC  
Control  
Logic  
Configuration  
Logic  
M0:M8  
nP_LOAD  
SSC_CTL0  
SSC_CTL1  
DIV_SEL  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
1
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
FUNCTIONAL DESCRIPTION  
The ICS8431I-21 features a fully integrated PLL and therefore The PLL loop divider or M divider is programmed by using  
requires no external components for setting the loop bandwidth. inputs M0 through M8.While the nP_LOAD input is held LOW,  
The output of the oscillator is divided by 16 prior to the phase the data present at M0:M8 is transparent to the M divider. On  
detector. With a 16MHz crystal this provides a 1MHz reference the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is  
frequency.TheVCO of the PLL operates over a range of 250MHz latched into the M divider and any further changes at the  
to 700MHz.The output of the M divider is also applied to the phase M0:M8 inputs will not be seen by the M divider until the next  
detector.  
LOW transition on nP_LOAD.  
The phase detector and the M divider force the VCO output The relationship between the VCO frequency, the crystal fre-  
frequency to be M times the reference frequency by adjusting quency and the M divider is defined as follows:  
fxtal  
16  
the VCO control voltage. Note that for some values of M (ei-  
ther too high or too low), the PLL will not achieve lock. The  
x
fVCO =  
M
output of the VCO is scaled by a divider prior to being sent to The M value and the required values of M0:M8 for programming  
the LVPECL output buffer.The divider provides a 50% output theVCO are shown in Table 3B, ProgrammableVCO Frequency  
duty cycle.  
FunctionTable.The frequency out is defined as follows:  
fVCO fxtal x M  
FOUT  
=
=
The programmable features of the ICS8431I-21 support four  
N
16 x N  
output operational modes and a programmable M divider and For the ICS8431I-21, the output divider may be set to either  
output divider.The four output operational modes are spread ÷2 or ÷4 by the DIV_SEL pin. For an input of 16 MHz, valid  
spectrum clocking (SSC), non-spread spectrum clock and M values for which the PLL will achieve lock are defined as:  
two test modes and are controlled by the SSC_CTL[1:0] pins. 250 ≤ M ≤ 511.  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
2
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
M0-M6  
M7-M8  
Type  
Pulldown  
Description  
1, 2, 3, 4,  
5, 6, 7  
Input  
Input  
Input  
Power  
M divider inputs. Data latched on LOW-to-HIGH transition  
of nP_LOAD input. LVCMOS / LVTTL pins interface levels.  
8, 9  
10, 11  
12, 15, 21  
13  
Pullup  
Pullup  
SSC CTL0,  
SSC CTL1  
SCC control pins. LVTTL / LVCMOS interface levels.  
Negative supply pins. Connect all VEE pins to board ground.  
Programmed as defined in Table 3A Function Table.  
VEE  
TEST I/O  
VCC  
Input /  
Output  
14, 27  
16, 17  
18  
Power  
Core supply pin.  
nFOUT, FOUT Output  
Differential outputs for the synthesizer. 3.3V LVPECL interface levels.  
Output supply pin.  
VCCO  
Power  
Input  
Determines the output divide value for FOUT.  
LVCMOS / LVTTL interface levels.  
19  
DIV_SEL  
Pulldown  
Active High Master Reset. When logic HIGH, the internal dividers are  
reset causing the true output FOUT to go low and the inverted output  
20  
MR  
Input  
Pulldown nFOUT to go high. When logic LOW, the internal dividers and the  
outputs are enabled. Assertion of MR does not effect loaded M and T  
values. LVCMOS / LVTTL interface levels.  
22  
VCCA  
nc  
Power  
Analog supply pin.  
No connect.  
23, 24  
Unused  
XTAL_OUT,  
XTAL_IN  
Crystal oscillator interface. XTAL_IN is the input.  
XTAL_OUT is the output.  
Parallel load input. Determines when data present at M8:M0  
25, 26  
28  
Input  
Input  
nP_LOAD  
Pulldown  
is loaded into M divider. LVTTL / LVCMOS interface levels.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Input Pin Capacitance  
Input Pullup Resistor  
4
pF  
kΩ  
kΩ  
RPULLUP  
51  
51  
RPULLDOWN Input Pulldown Resistor  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
3
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
TABLE 3A. SSC CONTROL INPUT FUNCTION TABLE  
Inputs  
Outputs  
TEST_I/O  
SSC  
Operational Modes  
FOUT, nFOUT  
Source  
SSC_CTL1 SSC_CTL0  
TEST_I/O  
DIV_SEL0 DIV_SEL1  
fXTAL ÷ 16 PLL bypass; oscillator, M and N  
0
0
1
1
0
1
0
1
Internal  
Disabled fXTAL ÷ 32 fXTAL ÷ 64  
÷ M  
dividers test mode. NOTE 1  
fXTAL x M fXTAL x M  
Enabled  
Default SSC;  
PLL  
Hi-Z  
32  
64  
Modulation Factor = ½ Percent  
PLL Bypass Mode, NOTE 1;  
(1MHz≤ Test Clk ≤ 200MHz)  
External Disabled  
Test Clk  
Test Clk  
Input  
Hi-Z  
fXTAL x M fXTAL x M  
32 64  
PLL  
Disabled  
No SSC Modulation  
NOTE 1: Used for in house debug and characterization.  
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)  
256  
M8  
0
128  
M7  
1
64  
M6  
1
32  
M5  
1
16  
8
M3  
1
4
M2  
0
2
M1  
1
1
M0  
0
VCO Frequency  
(MHz)  
M Count  
M4  
1
1
1
1
•
250  
251  
252  
253  
•
250  
251  
252  
253  
•
0
1
1
1
1
0
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
508  
509  
510  
511  
508  
509  
510  
511  
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
NOTE 1: Assumes a 16MHz crystal.  
TABLE 3C. FUNCTION TABLE  
Inputs  
Output Frequency (MHz)  
N Divider Value  
DIV_SEL  
Minimum  
125  
Maximum  
350  
0
1
2
4
62.5  
175  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
4
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
ABSOLUTE MAXIMUM RATINGS  
SupplyVoltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
device.These ratings are stress specifications only.Functional  
operation of product at these conditions or any conditions be-  
yond those listed in the DC Characteristics or AC Character-  
istics is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect product reliability.  
CC  
Inputs, V  
-0.5V to VCC + 0.5V  
I
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
PackageThermal Impedance, θ  
46.2°C/W (0 lfpm)  
-65°C to 150°C  
JA  
StorageTemperature, T  
STG  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = -40°C TO 85°C  
Symbol Parameter Test Conditions Minimum Typical Maximum Units  
VCC  
VCCO  
VCCA  
IEE  
Core Supply Voltage  
3.135  
3.135  
3.135  
3.3  
3.3  
3.3  
3.465  
3.465  
3.465  
155  
V
V
Output Supply Voltage  
Analog Supply Voltage  
Power Supply Current  
Analog Supply Current  
V
mA  
mA  
ICCA  
16  
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = -40°C TO 85°C  
Symbol  
Parameter  
M0:M8, SSC_CTL0,  
Test Conditions  
Minimum Typical Maximum Units  
SSC_CTL1, MR,  
DIV_SEL, TEST_I/O,  
nP_LOAD  
M0:M8, SSC_CTL0,  
SSC_CTL1, MR,  
DIV_SEL, TEST_I/O,  
nP_LOAD  
M7, M8, SSC_CTL0,  
SSC_CTL1, TEST_IO  
M0:M6, DIV_SEL  
nP_LOAD, MR  
VIH  
Input High Voltage  
Input Low Voltage  
Input High Current  
2
VCC + 0.3  
V
V
VIL  
-0.3  
0.8  
V
CC = VIN = 3.465V  
5
µA  
µA  
µA  
µA  
IIH  
VCC = VIN = 3.465V  
150  
M7, M8, SSC_CTL0,  
SSC_CTL1, TEST_IO  
M0:M6, DIV_SEL  
nP_LOAD, MR  
VCC = 3.465V, VIN = 0V  
VCC = 3.465V, VIN = 0V  
-150  
-5  
IIL  
Input Low Current  
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = -40°C TO 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCCO - 1.4  
VCCO - 2.0  
0.6  
Typical  
Maximum  
VCCO - 0.9  
VCCO - 1.7  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Peak-to-Peak Output Voltage Swing  
V
V
V
VOL  
VSWING  
NOTE 1: Output terminated with 50Ω to VCCO - 2V. See Parameter Measurement Section, 3.3V Output Load Test Circuit.  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
5
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
TABLE 5. CRYSTAL CHARACTERISTICS  
Parameter  
Test Conditions  
Minimum Typical Maximum  
Units  
Mode of Oscillation  
Frequency  
Fundamental  
14  
3
16  
25  
40  
7
MHz  
Ω
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
pF  
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = -40°C TO 85°C  
Symbol Parameter  
FOUT Output Frequency  
jit(cc)  
Test Conditions  
FOUT ≥ 100MHz  
20% to 80%  
Minimum Typical Maximum  
Units  
MHz  
ps  
62.5  
350  
30  
Cycle-to-Cycle Jitter; NOTE 1, 5  
Output Duty Cycle  
19  
50  
t
odc  
48  
200  
14  
52  
%
tR / tF  
Fxtal  
Output Rise/Fall Time  
700  
25  
ps  
Crystal Input Range; NOTE 2, 3  
SSC Modulation Frequency; NOTE 4  
SSC Modulation Factor; NOTE 4  
Spectral Reduction; NOTE 4  
Power-up to Stable Clock Output  
16  
MHz  
KHz  
%
FM  
FOUT = 200MHz  
FOUT = 200MHz  
FOUT = 200MHz  
29  
33.33  
0.6  
FMF  
0.4  
10  
SSCred  
tSTABLE  
7
dB  
10  
ms  
See Figures in the Parameter Measurement Information section.  
NOTE 1: Jitter performance using XTAL inputs.  
NOTE 2: Only valid within the VCO operating range.  
NOTE 3: For XTAL input, refer to Application Note.  
NOTE 4: Spread Spectrum clocking enabled.  
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
6
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
PARAMETER MEASUREMENT INFORMATION  
2V  
nFOUT  
FOUT  
SCOPE  
VCC  
VCCA, VCCO  
,
Qx  
➤
➤
tcycle n  
tcycle n+1  
➤
LVPECL  
➤
nQx  
VEE  
tjit(cc) = tcycle n –tcycle n+1  
1000 Cycles  
-1.3V 0.165V  
3.3V OUTPUT LOAD AC TEST CIRCUIT  
CYCLE-TO-CYCLE JITTER  
nFOUT  
80%  
tF  
80%  
FOUT  
VSWING  
20%  
tPW  
Clock  
20%  
tPERIOD  
Outputs  
tR  
tPW  
odc =  
x 100%  
tPERIOD  
OUTPUT RISE/FALL TIME  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
7
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
APPLICATION INFORMATION  
POWER SUPPLY FILTERING TECHNIQUES  
As in any high speed analog circuitry, the power supply pins  
are vulnerable to random noise. The ICS8431I-21 provides  
separate power supplies to isolate any high switching noise  
from the outputs to the internal PLL.VCC, VCCA, and VCCO should  
be individually connected to the power supply plane through  
vias, and bypass capacitors should be used for each pin. To  
achieve optimum jitter performance, better power supply iso-  
lation is required. Figure 1 illustrates how a 10Ω along with  
a 10μF and a .01μF bypass capacitor should be connected  
to each VCCA pin.  
3.3V  
VCC  
.01μF  
.01μF  
10Ω  
VCCA  
10μF  
FIGURE 1. POWER SUPPLY FILTERING  
TERMINATION FOR LVPECL OUTPUTS  
The clock layout topology shown below is typical for  
IA64/32 platforms. The two different layouts mentioned are  
recommended only as guidelines.  
drive 50Ω transmission lines. Matched impedance techniques  
should be used to maximize operating frequency and minimize  
signal distortion. Figures 2A and 2B show two different layouts  
which are recommended only as guidelines. Other suitable clock  
layouts may exist and it would be recommended that the board  
designers simulate to guarantee compatibility across all printed  
circuit and clock component process variations.  
FOUT and nFOUT are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs.Therefore, terminat-  
ing resistors (DC current path to ground) or current sources  
must be used for functionality. These outputs are designed to  
3.3V  
Z
o = 50Ω  
125Ω  
125Ω  
FOUT  
FIN  
Z
o = 50Ω  
o = 50Ω  
Zo = 50Ω  
FOUT  
FIN  
50Ω  
50Ω  
Z
VCC - 2V  
1
RTT =  
Zo  
RTT  
84Ω  
84Ω  
((VOH + VOL) / (VCC – 2)) – 2  
FIGURE 2A. LVPECL OUTPUT TERMINATION  
FIGURE 2B. LVPECL OUTPUT TERMINATION  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
8
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
CRYSTAL INPUT INTERFACE  
were chosen to minimize the ppm error. The optimum C1 and C2  
values can be slightly adjusted for different board layouts.  
The ICS8431I-21 has been characterized with 18pF parallel resonant  
crystals.The capacitor values, C1 and C2, shown in Figure 3 below  
were determined using a 25MHz, 18pF parallel resonant crystal and  
XTAL_OUT  
XTAL_IN  
C1  
22p  
X1  
18pF Parallel Crystal  
C2  
22p  
FIGURE 3. CRYSTAL INPUT INTERFACE  
SPREAD SPECTRUM  
The ICS8431I-21 triangle modulation frequency deviation will  
not exceed 0.6% down-spread from the nominal clock fre-  
quency (+0.0%/-0.5%). An example of the amount of down  
spread relative to the nominal clock frequency can be seen in  
the frequency domain, as shown in Figure 4B. The ratio of  
this width to the fundamental frequency is typically 0.4%, and  
will not exceed 0.6%.The resulting spectral reduction will be  
greater than 7dB, as shown in Figure 4B. It is important to  
note the ICS8431I-21 7dB minimum spectral reduction is the  
component-specific EMI reduction, and will not necessarily  
be the same as the system EMI reduction.  
Spread-spectrum clocking is a frequency modulation tech-  
nique for EMI reduction. When spread-spectrum is enabled,  
a 30kHz triangle waveform is used with 0.5% down-spread  
(+0.0% / -0.5%) from the nominal 200MHz clock frequency.  
An example of a triangle frequency modulation profile is shown  
in Figure 4A below. The ramp profile can be expressed as:  
• Fnom = Nominal Clock Frequency in Spread OFF mode  
(200MHz with 16MHz IN)  
• Fm = Nominal Modulation Frequency (30kHz)  
• δ = Modulation Factor (0.5% down spread)  
1
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <  
,
2 fm  
1
2 fm  
1
fm  
(1 - δ) fnom - 2 fm x δ x fnom x t when  
< t <  
Δ − 10 dBm  
Fnom  
A
B
➤
(1 - δ) Fnom  
δ = .4%  
➤
➤
0.5/fm  
1/fm  
FIGURE 4A. TRIANGLE FREQUENCY MODULATION  
FIGURE 4B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN  
(A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON  
8431AMI-21  
www.idt.com  
REV. A NOVEMBER 22, 2010  
9
ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
LAYOUT GUIDELINE  
The schematic of the ICS8431I-21 layout example used in in Figure 5B. This layout example is used as a general guide-  
this layout guideline is shown in Figure 5A. The ICS8431I-21 line. The layout in the actual system will depend on the se-  
recommended PCB board layout for this example is shown lected component types and the density of the P.C. board.  
Logic Input Pin Examples  
Set Logic  
Input to  
'1'  
Set Logic  
Input to  
'0'  
VCC=3.3V  
VCC  
VCC  
SP=Spare, not installed  
RU1  
1K  
RU2  
SP  
VCC  
C6  
0.01uF  
To Logic  
Input  
To Logic  
Input  
U1  
pins  
pins  
C8  
22pF  
22pF  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
RD1  
SP  
RD2  
1K  
M0  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
nP_LOAD  
VCC  
XTAL_IN  
XTAL_OU T  
NC  
X1  
C7  
NC  
VCCA  
VEE  
VCC  
R5  
10  
VCC  
VCCA  
M8  
MR  
SSC_CTL0  
SSC_CTL1  
VEE  
TEST_IO  
VCC  
DIV_SEL  
VCCO  
FOUT  
nFOUT  
VEE  
VCC  
C3  
0.01uF  
C4  
10uF  
R1  
125  
R3  
125  
VCC  
Zo = 50 Ohm  
Zo = 50 Ohm  
+
-
ICS8431I-21  
C1  
0.1uF  
C2  
0.1uF  
R2  
84  
R4  
84  
FIGURE 5A. SCHEMATIC EXAMPLE  
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• Avoid sharp angles on the clock trace.Sharp angle turns  
cause the characteristic impedance to change on the  
transmission lines.  
The following component footprints are used in this layout  
example:  
All the resistors and capacitors are size 0603.  
• Keep the clock traces on the same layer.Whenever pos-  
sible, avoid placing vias on the clock traces. Placement  
of vias on the traces can affect the trace characteristic  
impedance and hence degrade signal integrity.  
POWER AND GROUNDING  
Place the decoupling capacitors C1, C2 and C6, as close as  
possible to the power pins. If space allows, placment of the  
decoupling capacitor on the component side is preferred. This  
can reduce unwanted inductance between the decoupling ca-  
pacitor and the power pin generated by the via.  
• To prevent cross talk, avoid routing other signal traces in  
parallel with the clock traces. If running parallel traces is  
unavoidable, allow a separation of at least three trace  
widths between the differential clock trace and the other  
signal trace.  
Maximize the power and ground pad sizes and number of vias  
capacitors.This can reduce the inductance between the power  
and ground planes and the component power and ground pins.  
• Make sure no other signal traces are routed between the  
clock trace pair.  
The RC filter consisting of R5, C3, and C4 should be placed as  
close to the VCCA pin as possible.  
• The matching termination resistors should be located as  
close to the receiver input pins as possible.  
CLOCK TRACES AND TERMINATION  
The matching termination resistors R1, R2, R3 and R4 should  
be located as close to the receiver input pins as possible.  
Other termination scheme can also be used but is not shown  
in the example.  
Poor signal integrity can degrade the system performance or  
cause system failure. In synchronous high-speed digital systems,  
the clock signal is less tolerant to poor signal integrity than other  
signals. Any ringing on the rising or falling edge or excessive ring  
back can cause system failure. The shape of the trace and the  
CRYSTAL  
trace delay might be restricted by the available space on the board The crystal X1 should be located as close as possible to the pins  
and the component location.While routing the traces, the clock 25 (XTAL_OUT) and 26 (XTAL_IN).The trace length between the  
signal traces should be routed first and should be locked prior to X1 and U1 should be kept to a minimum to avoid unwanted para-  
routing other signal traces.  
sitic inductance and capacitance. Other signal traces should not  
be routed near the crystal traces.  
• The 50Ω output trace pair should have same length.  
C8  
GND  
U1  
VCC  
ICS8431-21  
Signals  
C6  
VIA  
X1  
C3  
C4  
R5  
C7  
C2  
Zo=50 Ohm  
Zo=50 Ohm  
C1  
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8431I-21  
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POWER CONSIDERATIONS  
This section provides information on power dissipation and junction temperature for the ICS8431I-21.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the ICS8431I-21 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW  
Power (outputs)MAX = 30mW/Loaded Output pair  
If all outputs are loaded, the total power is 1 * 30mW = 30mW  
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 30mW = 567.1mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the  
device. The maximum recommended junction temperature for the devices is 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = JunctionTemperature  
θJA = Junction-to-AmbientThermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = AmbientTemperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a  
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W perTable 7 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.567W * 39.7°C/W = 107.5°C. This is below the limit of 125°C.  
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,  
and the type of board (single layer or multi-layer).  
Table 7. THERMAL RESISTANCE θJA FOR 28-PIN SOIC, FORCED CONVECTION  
θJA byVelocity (Linear Feet per Minute)  
0
200  
500  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
76.2°C/W  
60.8°C/W  
53.2°C/W  
46.2°C/W  
39.7°C/W  
36.8°C/W  
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.  
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3. Calculations and Equations.  
The purpose of this section is to derive the power dissipated into the load.  
LVPECL output driver circuit and termination are shown in Figure 6.  
VCCO  
Q1  
VOUT  
R L  
50  
VCCO - 2V  
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION  
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination  
voltage ofV - 2V.  
CCO  
•
•
For logic high, VOUT = V  
= V  
– 0.9V  
OH_MAX  
CCO_MAX  
)
= 0.9V  
OH_MAX  
(V  
- V  
CCO_MAX  
For logic low, VOUT = V  
= V  
– 1.7V  
OL_MAX  
CCO_MAX  
)
= 1.7V  
OL_MAX  
(V  
- V  
CCO_MAX  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
))  
Pd_H = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
/R ] * (V  
- V ) =  
OH_MAX  
OH_MAX  
CCO_MAX  
CCO_MAX  
OH_MAX  
_MAX  
OH_MAX  
CCO_MAX  
L
CCO  
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW  
))  
Pd_L = [(V – (V - 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
/R ] * (V  
- V  
) =  
OL_MAX  
CCO_MAX  
CCO_MAX  
OL_MAX  
_MAX  
OL_MAX  
CCO_MAX  
OL_MAX  
L
CCO  
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW  
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RELIABILITY INFORMATION  
TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD SOIC  
θJA byVelocity (Linear Feet per Minute)  
0
200  
60.8°C/W  
39.7°C/W  
500  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
76.2°C/W  
53.2°C/W  
46.2°C/W  
36.8°C/W  
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.  
TRANSISTOR COUNT  
The transistor count for ICS8431I-21 is: 4790  
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PACKAGE OUTLINE - M SUFFIX FOR 28 LEAD SOIC  
TABLE 9. PACKAGE DIMENSIONS  
Millimeters  
MINIMUM MAXIMUM  
SYMBOL  
N
A
28  
--  
2.65  
--  
A1  
A2  
B
0.10  
2.05  
0.33  
0.18  
17.70  
7.40  
2.55  
0.51  
0.32  
18.40  
7.60  
C
D
E
e
1.27 BASIC  
H
h
10.00  
0.25  
0.40  
0°  
10.65  
0.75  
1.27  
8°  
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119  
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TABLE 10. ORDERING INFORMATION  
Part/Order Number  
8431AMI-21  
Marking  
Package  
Shipping Packaging  
Tube  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
ICS8431AMI-21  
ICS8431AMI-21  
28 Lead SOIC  
8431AMI-21T  
28 Lead SOIC  
1000 tape & reel  
Tube  
8431AMI-21LF  
8431AMI-21LFT  
ICS8431AMI-21LF  
ICS8431AMI-21LF  
28 Lead "Lead-Free" SOIC  
28 Lead "Lead-Free" SOIC  
1000 tape & reel  
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc.(IDT) assumes no responsibility for either its use or for infringement of  
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial  
applications.Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves  
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
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REVISION HISTORY SHEET  
Description of Change  
Rev  
Table  
Page  
Date  
Updated datasheet's header/footer with IDT from ICS.  
Ordering Information Table - removed ICS prefix from Part/Order Number  
column. Added lead-free marking.  
T10  
17  
19  
A
11/22/10  
Added Contact Page.  
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We’ve Got Your Timing Solution.  
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San Jose, CA 95138  
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Tech Support  
netcom@idt.com  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.  
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of  
their respective owners.  
Printed in USA  
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