82C83H
state). The 82C8X series gated inputs mean that this condi-
Functional Diagram
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
D Q
DO0
DI0
CLK
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DI1
DI2
DI3
DI4
DI5
DI6
DI7
V
CC
P
OE
P
INTERNAL
DATA
DATA IN
V
CC
N
N
P
N
STB
OE
FIGURE 2. 82C86H/87H GATED INPUTS
Gated Inputs
Decoupling Capacitors
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
and typically cause an increase in power dissipation in I = C (dv/dt)
L
CMOS devices by creating a low resistance path between
Assuming that all outputs change state at the same time and
that dv/dt is constant;
V
and GND when the signal is at or near the input switch-
CC
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
(V
× 80 percent)
(EQ. 1)
CC
I = C --------------------------------------------------------
L
t
⁄ t
F
R
where t = 20ns, V
R
= 5.0V, C = 300pF on each eight out-
L
CC
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
puts.
-12
-9
I = (8 x 300 x 10 ) x (5.0V x 0.8)/(20 x 10 ) = 480mA
This current spike may cause a large negative voltage spike on
inputs disconnect the input circuitry from the V
and
CC
V
which could cause improper operation of the device. To fil-
CC
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between V and GND at each device,
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
CC
from V
to GND occurs during input transitions and invalid
CC
with placement being as near to the device as possible.
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
ALE
MULTI-
PLEXED
BUS
V
V
CC
ADDRESS
ADDRESS
CC
P
ICC
P
V
V
CC
CC
N
STB
P
P
INTERNAL
DATA
DATA IN
P
N
N
N
STB
DATA IN
P
INTERNAL
DATA
N
N
FIGURE 1. 82C82/83H
D.C. input voltage levels can also cause an increase in ICC
if these input levels approach the minimum V or maximum
IH
conditions. This is due to the operation of the input cir-
V
IL
cuitry in its linear operating region (partially conducting
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
282
