853013AM--Datasheet/数据表在线中文翻译

LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-

2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

ICS853013

General Description

Features

The ICS853013 is a low skew, high performance

• Two differential LVPECL/ECL bank outputs

• Two differential LVPECL clock input pairs

S

IC

dual 1-to-3 Differential-to-2.5V/3.3V/5V LVPECL/

ECL Fanout Buffer and a member of the

Hiperclocks^TMfamily of High Performance Clock

Solutions from IDT. The ICS853013 operates with a

HiPerClockS™

• PCLKx, nPCLKx pairs can accept the following

differential input levels: LVPECL, LVDS, CML, SSTL

• Output frequency: >2GHz (typical)

positive or negative power supply at 2.5V, 3.3V, or 5V. Guaranteed

output and part-to-part skew characteristics make the ICS853013

ideal for those clock distribution applications demanding well

defined performance and repeatability.

• Translates any single-ended input signal to LVPECL levels with

resistor bias on nPCLKx input

• Output skew: 40ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Propagation delay: 5780ps (maximum)

• Additive phase jitter, RMS: 0.03ps (typical)

• LVPECL mode operating voltage supply range:

V_CC= 2.375V to 5.25V, V_EE= 0V

• ECL mode operating voltage supply range:

V_CC= 0V, V_EE= -5.25V to -2.375V

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Block Diagram

Pin Assignment

QA0

nQA0

QA0

1

2

20 QA1

Pulldown

nQA0

PCLKA

19

nQA1

Pullup/Pulldown

V^CC

PCLKA

3

4

18

17

QA2

nQA2

V^CC

QB2

nQB2

QB1

nPCLKA

QA1

nQA1

nPCLKA

PCLKB

nPCLKB

5

6

7

8

9

16

15

14

13

QA2

nQA2

V^CC

nQB0

QB0 10

12 nQB1

11

V^EE

QB0

Pulldown

nQB0

PCLKB

ICS853013

Pullup/Pulldown

nPCLKB

QB1

20-Lead SOIC

7.5mm x 12.8mm x 2.3mm package body

nQB1

M Package

Top View

QB2

nQB2

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

1

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 2

Output

Power

Input

Differential output pair. LVPECL interface levels.

Power supply pins.

nQA0, QA0

V_CC

3, 8, 16

4

PCLKA

Pulldown Non-inverting differential LVPECL clock input.

Pullup/

5

6

7

nPCLKA

PCLKB

Input

Inverting differential LVPECL clock input. V_CC/2 default when left floating.

Pulldown

Pulldown Non-inverting differential LVPECL clock input.

Pullup/

nPCLKB

Inverting differential LVPECL clock input. V_CC/2 default when left floating.

Pulldown

9, 10

11

Output

Power

Output

Differential output pair. LVPECL interface levels.

Negative supply pin.

nQB0, QB0

V_EE

12, 13

14, 15

17, 18

19, 20

Differential output pair. LVPECL interface levels.

nQB1, QB1

nQB2, QB2

nQA2, QA2

nQA1, QA1

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

R_PULLDOWNInput Pulldown Resistor

R_VCC/2Pullup/Pulldown Resistors

Parameter

Test Conditions

Minimum

Typical

75

Maximum

Units

kΩ

50

kΩ

Function Table

Table 3. Clock Input Function Table

Inputs

Outputs

PCLKA or PCLKB

nPCLKA or nPCLKB

QA0:Q2,

nQA0:nQA2,

QB0:QB2 nQB0:nQB2

Input to Output Mode

Differential to Differential

Single-Ended to Differential

Polarity

0

1

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

Non-Inverting

Inverting

1

0

Biased; NOTE 1

1

Biased; NOTE 1

0

1

Inverting

NOTE 1: Please refer to the Application Information, Wiring the Differential Input to Accept Single Ended Levels.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

2

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

Negative Supply Voltage, V_EE

Inputs, V_I(LVPECL mode)

Inputs, V_I(ECL mode)

5.5V (LVPECL mode, V_EE= 0V)

-5.5V (ECL mode, V_CC= 0V)

-0.5V to V_CC+ 0.5V

0.5V to V_EE– 0.5V

Outputs, I_O

Continuos Current

Surge Current

50mA

100mA

Operating Temperature Range, T_A

Package Thermal Impedance, θ_JA

Storage Temperature, T_STG

-40°C to +85°C

46.2°C/W (0 lfpm)

-65°C to 150°C

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V_CC= 2.375V to 5.25V; V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

V_CCPositive Supply Voltage

I_EEPower Supply Current

Test Conditions

Minimum

Typical

Maximum

5.25

Units

V

2.375

3.3

60

mA

Table 4B. LVPECL DC Characteristics, V_CC= 3.3V, V_EE= 0V; T_A= -40°C to 85°C

-40°C

Typ

25°C

Typ

80°C

Symbol Parameter

Min

2.175

1.405

2.075

1.43

Max

2.38

1.68

2.36

1.765

1200

Min

2.225

1.425

2.075

1.43

Max

2.37

Min

2.295

1.44

2.075

1.43

150

Typ

2.33

Max

Units

V_OH

V_OL

V_IH

V_IL

Output High Voltage; NOTE 1

2.275

1.545

2.295

1.52

2.365

1.63

V

Output Low Voltage; NOTE 1

Input High Voltage (Single-ended)

Input Low Voltage (Single-ended)

Peak-to-Peak Input Voltage

1.615

2.36

1.535

2.36

1.765

1200

1.765

1200

V_PP

150

800

150

800

Input High Voltage Common Mode

Range; NOTE 2, 3

V_CMR

I_IH

1.2

3.3

1.2

3.3

1.2

3.3

V

Input

PCLKA, PCLKB

200

µA

High Current nPCLKA, nPCLKB

PCLKA, PCLKB

Input

-10

µA

I_IL

Low Current

nPCLKA, nPCLKB

-200

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CC– 2V.

NOTE 2: Common mode voltage is defined as V_IH.

NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is V_CC+ 0.3V.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

3

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

.Table 4C. LVPECL DC Characteristics, V_CC= 2.5V, V_EE= 0V; T_A= -40°C to 85°C

-40°C

Typ

25°C

Typ

80°C

Typ

Symbol Parameter

Min

1.375

0.605

1.275

0.63

Max

1.58

0.88

1.56

0.965

1200

Min

1.425

0.625

1.275

0.63

Max

1.57

Min

1.495

0.64

1.275

0.63

150

Max

1.565

0.83

Units

V_OH

V_OL

V_IH

V_IL

Output High Voltage; NOTE 1

1.475

0.745

1.495

0.72

1.53

V

Output Low Voltage; NOTE 1

Input High Voltage (Single-ended)

Input Low Voltage (Single-ended)

Peak-to-Peak Input Voltage

0.815

1.56

0.735

-0.8

0.965

1200

0.965

1200

V_PP

150

800

150

800

Input High Voltage Common Mode

Range; NOTE 2, 3

V_CMR

I_IH

1.2

2.5

1.2

2.5

1.2

2.5

V

Input

PCLKA, PCLKB

200

µA

High Current nPCLKA, nPCLKB

PCLKA, PCLKB

Input

-10

µA

I_IL

Low Current

nPCLKA, nPCLKB -200

-200

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CC– 2V.

NOTE 2: Common mode voltage is defined as V_IH.

NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is V_CC+ 0.3V.

Table 4D. LVPECL DC Characteristics, V_CC= 5V, V_EE= 0V; T_A= -40°C to 85°C

-40°C

Typ

25°C

Typ

80°C

Typ

Symbol Parameter

Min

Max

Min

Max

Min

Max Units

V_OH

V_OL

Output High Voltage; NOTE 1

-1.125 -1.025 -0.92

-1.895 -1.755 -1.62

-1.075 -1.005 -0.93

-1.005

-0.97 -0.935

V

-1.76

-1.67

5

Output Low Voltage; NOTE 1

-1.875

-1.78 -1.685

-1.86

V_IH

V_IL

Input High Voltage (Single-ended)

Input Low Voltage (Single-ended)

Peak-to-Peak Input Voltage

-1.225

-1.87

150

-0.94

-1.535

1200

-1.225

-1.87

150

-0.94

-1.225

-1.87

150

-0.94

V

-1.535

V_PP

800

1200

0

800

1200

0

Input High Voltage Common

Mode Range; NOTE 2, 3

V_CMR

I_IH

V_EE+1.2

0

V_EE+1.2

V

Input

PCLKA, PCLKB

200

µA

High Current nPCLKA, nPCLKB

PCLKA, PCLKB

Input

-10

µA

I_IL

Low Current

nPCLKA, nPCLKB

-200

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CC– 2V.

NOTE 2: Common mode voltage is defined as V_IH.

NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is V_CC+ 0.3V.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

4

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Table 4E. ECL DC Characteristics, V_CC= 0V, V_EE= -5.25V to -2.375V; T_A= -40°C to 85°C

-40°C

Typ

25°C

Typ

80°C

Typ

Symbol Parameter

Min

Max

Min

Max

Min

-1.005

-1.86

-1.225

-1.87

150

Max Units

V_OH

V_OL

V_IH

V_IL

Output High Voltage; NOTE 1

-1.125 -1.025 -0.92

-1.895 -1.755 -1.62

-1.075 -1.005 -0.93

-0.97 -0.935

-1.765 -1.67

-0.94

V

Output Low Voltage; NOTE 1

Input High Voltage (Single-ended)

Input Low Voltage (Single-ended)

Peak-to-Peak Input Voltage

-1.875

-1.225

-1.87

150

-1.78 -1.685

-0.94

-1.225

-1.87

150

-0.94

-1.535

1200

-1.535

V_PP

800

1200

0

800

1200

0

Input High Voltage Common

Mode Range; NOTE 2, 3

V_CMR

I_IH

V_EE+1.2

0

V_EE+1.2

V

Input

PCLKA, PCLKB

200

µA

High Current nPCLKA, nPCLKB

PCLKA, PCLKB

Input

-10

µA

I_IL

Low Current

nPCLKA, nPCLKB

-200

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CC– 2V.

NOTE 2: Common mode voltage is defined as V_IH.

NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is V_CC+ 0.3V

AC Electrical Characteristics

Table 5. AC Characteristics, V_CC= 0V, V_EE= -5.25V to -2.375V or; V_CC= 2.375V to 5.25V, V_EE= 0V; T_A= -40°C to 85°C

-40°C

Typ

>2

25°C

Typ

>2

80°C

Typ

>2

Symbol Parameter

f_MAXOutput Frequency

Min

Max

Min

Max

Min

Max

Units

GHz

PropagationDelay;Low-to-High;

NOTE 1

tP_LH

300

410

510

330

425

520

360

465

570

ps

PropagationDelay;High-to-Low;

NOTE 1

tP_HL

tsk(o)

Output Skew; NOTE 2, 4

40

ps

tsk(odc) Output Duty Cycle Skew

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

250

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jjitter Section

tjit

0.03

180

0.03

180

0.03

180

ps

Output

t_R/ t_F

20% to 80%

Rise/Fall Time

120

250

120

250

120

250

All parameters are measured at f ≤ 1GHz, unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

5

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the

to the power in the fundamental. When the required offset is

fundamental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise power

present in a 1Hz band at a specified offset from the fundamental

frequency to the power value of the fundamental. This ratio is

expressed in decibels (dBm) or a ratio of the power in the 1Hz band

specified, the phase noise is called a dBc value, which simply

means dBm at a specified offset from the fundamental. By

investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

0

-10

-20

-30

Additive Phase Jitter @ 156.25MHz

= 0.03ps (typical)

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k

10k

100k

1M

10M

100M

Offset Frequency (Hz)

As with most timing specifications, phase noise measurements

has issues relating to the limitations of the equipment. Often the

noise floor of the equipment is higher than the noise floor of the

device. This is illustrated above. The device meets the noise floor

of what is shown, but can actually be lower. The phase noise is

dependent on the input source and measurement equipment.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

6

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information

2V

V

CC

SCOPE

nPCLKx

V_CC

Qx

V_PP

V_CMR

Cross Points

PCLKx

LVPECL

nQx

V_EE

V

EE

-3.25V to -0.375V

LVPECL Output Load AC Test Circuit

Differential Input Level

nQx

Qx

Part 1

nQx

Qx

nQy

Part 2

nQy

Qy

tsk(o)

tsk(pp)

Part-to-Part Skew

Output Skew

nPCLKx

PCLKx

80%

t_F

80%

V_SWING

20%

Clock

20%

nQA[0:2],

nQB[0:2]

Outputs

t_R

QA[0:2],

QB[0:2]

tp_LH

tp_HL

Output Rise/Fall Time

Propagation Delay

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

7

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information, continued

nPCLKx

PCLKx

nQA[0:2],

nQB[0:2]

QA[0:2],

QB[0:2]

tp_LH

tp_HL

tsk(odc) =  tp_LH- tp_HL



Output Duty Cycle Skew

Application Information

Wiring the Differential Input to Accept Single-ended LVCMOS Levels

Figure 1 shows an example of the differential input that can be

wired to accept single-ended LVCMOS levels. The reference

voltage level V_BBgenerated from the device is connected to the

negative input. The C1 capacitor should be located as close as

possible to the input pin.

V_CC

R1

1K

Single Ended Clock Input

PCLKx

V_REF

nPCLKx

C1

0.1u

R2

1K

Figure 1. Single-Ended LVCMOS Signal Driving Differential Input

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

8

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

LVPECL Clock Input Interface

The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other

differential signals. Both V_SWINGand V_OHmust meet the V_PPand

V_CMRinput requirements. Figures 2A to 2F show interface

examples for the HiPerClockS PCLK/nPCLK input driven by the

most common driver types. The input interfaces suggested here

are examples only. If the driver is from another vendor, use their

termination recommendation. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

3.3V

Zo = 50Ω

3.3V

R1

50

R2

50

Zo = 50Ω

PCLK

R1

100

PCLK

nPCLK

Zo = 50Ω

HiPerClockS

nPCLK

CML Built-In Pullup

PCLK/nPCLK

HiPerClockS

PCLK/nPCLK

CML

Figure 2B. HiPerClockS PCLK/nPCLK Input

Driven by a Built-In Pullup CML Driver

Figure 2A. HiPerClockS PCLK/nPCLK Input

Driven by an Open Collector CML Driver

3.3V

R3

125

R4

125

R3

84

R4

84

C1

C2

Zo = 50Ω

3.3V LVPECL

PCLK

nPCLK

HiPerClockS

PCLK/nPCLK

HiPerClockS

Input

R5

100 - 200

R6

100 - 200

LVPECL

R1

125

R2

125

R1

84

R2

84

Figure 2D. HiPerClockS PCLK/nPCLKInput Driven by

a 3.3V LVPECL Driver with AC Couple

Figure 2C. HiPerClockS PCLK/nPCLK Input

Driven by a 3.3V LVPECL Driver

3.3V

2.5V

3.3V

2.5V

R3

1k

R4

1k

R3

R4

Zo = 50Ω

120

C1

C2

Zo = 60Ω

PCLK

R5

100

nPCLK

HiPerClockS

PCLK/nPCLK

LVDS

HiPerClockS

PCLK/nPCLK

SSTL

R1

1k

R2

1k

R1

120

R2

120

Figure 2F. HiPerClockS PCLK/nPCLK Input

Driven by a 3.3V LVDS Driver

Figure 2E. HiPerClockS PCLK/nPCLK Input

Driven by an SSTL Driver

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

9

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Recommendations for Unused Output Pins

Inputs:

Outputs:

PCLK/nPCLK INPUTS

LVPECL Outputs

For applications not requiring the use of a differential input, both

the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1kΩ resistor can be tied

from PCLK to ground. For applications

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal

distortion. Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and

clock component process variations.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50Ω

3.3V

Z

_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

1

RTT =

Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

84Ω

Figure 3A. 3.3V LVPECL Output Termination

Figure 3B. 3.3V LVPECL Output Termination

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

10

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Termination for 2.5V LVPECL Outputs

Figure 4A and Figure 4B show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating

50Ω to V_CC– 2V. For V_CC= 2.5V, the V_CC– 2V is very close to

ground level. The R3 in Figure 4B can be eliminated and the

termination is shown in Figure 4C.

2.5V

V_CC= 2.5V

2.5V

V_CC= 2.5V

R1

R3

50Ω

250

+

–

50Ω

+

–

50Ω

2.5V LVPECL Driver

R1

50

R2

50

2.5V LVPECL Driver

R2

62.5

R4

62.5

R3

18

Figure 4A. 2.5V LVPECL Driver Termination Example

Figure 4B. 2.5V LVPECL Driver Termination Example

2.5V

V_CC= 2.5V

50Ω

+

50Ω

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 4C. 2.5V LVPECL Driver Termination Example

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

11

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Termination for 5V LVPECL Outputs

This section shows examples of 5V LVPECL output termination.

Figure 5A shows standard termination for 5V LVPECL. The

termination requires matched load of 50Ω resistors pull down to

V_CC– 2V = 3V at the receiver. Figure 5B shows Thevenin

equivalence of Figure 5A. In actual application where the 3V DC

power supply is not available, this approached is normally used.

5V

R3

84

R4

84

PECL

Zo = 50 Ohm

PECL

Zo = 50 Ohm

+

-

+

-

PECL

R1

125

R2

125

R1

50

R2

50

3V

Figure 5A. 5V LVPECL Driver Termination Example

Figure 5B. 5V LVPECL Driver Termination Example

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

12

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS853013.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853013 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 5.25V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 5.25V * 60mA = 315mW

Power (outputs)_MAX= 30.94mW/Loaded Output pair

If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW

Total Power__MAX(3.8V, with all outputs switching) = 315mW + 185.64mW = 500.64mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.

The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = Junction Temperature

θ_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 46.2°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.501W * 46.2°C/W = 108.1°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type

of board (single layer or multi-layer).

Table 6. Thermal Resistance θ_JAfor 20 Lead SOIC Forced Convection

θ_JAby Velocity

Linear Feet per Minute

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

83.2°C/W

46.2°C/W

65.7°C/W

39.7°C/W

57.5°C/W

36.8°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

13

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 6.

V_CC

Q1

V_OUT

RL

50Ω

V_CC- 2V

Figure 6. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage

of V_CC– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CC_MAX}– 0.935V

(V_{CC_MAX}– V_{OH_MAX}) = 0.935V

For logic low, V_OUT= V_{OL_MAX}= V_{CC_MAX}– 1.67V

(V_{CC_MAX}– V_{OL_MAX}) = 1.67V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) = [(2V – (V_{CC_MAX}– V_{OH_MAX}))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) =

[(2V – 0.935V)/50Ω] * 0.935V = 19.92mW

Pd_L = [(V_{OL_MAX}– (V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) = [(2V – (V_{CC_MAX}– V_{OL_MAX}))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) =

[(2V – 1.67V)/50Ω] * 1.67V = 11.02mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

14

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Reliability Information

Table 7. θ_JAvs. Air Flow Table for a 20 Lead SOIC

θ_JAvs. Air Flow

Linear Feet per Minute

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

83.2°C/W

46.2°C/W

65.7°C/W

39.7°C/W

57.5°C/W

36.8°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Transistor Count

The transistor count for ICS853013 is: 226

Pin compatible with MC100LVEL13 and MC100EL13

Package Outline and Package Dimensions

Package Outline - M Suffix for 20 Lead SOIC

Table 8. Package Dimensions for 20 Lead SOIC

300 Millimeters

All Dimensions in Millimeters

Symbol

Minimum

Maximum

N

A

A1

A2

B

C

D

E

20

2.65

0.10

2.05

0.33

0.18

12.60

7.40

2.55

0.51

0.32

13.00

7.60

e

1.27 Basic

H

h

10.00

0.25

0.40

0°

10.65

0.75

1.27

7°

L

α

Reference Document: JEDEC Publication 95, MS-013,

MS-119

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

15

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Ordering Information

Table 9. Ordering Information

Part/Order Number

853013AM

853013AMT

853013AMLF

853013AMLFT

Marking

Package

20 Lead SOIC

Shipping Packaging

Tube

1000 Tape & Reel

Tube

Temperature

-40°C to 85°C

ICS853013AM

ICS853013AMLF

“Lead-Free” 20 Lead SOIC

1000 Tape & Reel

NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for

the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT

product for use in life support devices or critical medical instruments.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

16

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Revision History Sheet

Rev

Table

Page

Description of Change

Date

8

16

Added Recommendations for Unused Input and Output Pins.

Ordering Information Table - added Lead-Free marking.

A

10/19/05

T8

T4B

3

4

5

3.3V LVPECL DC Characteristics - changed I_IHmax. from 150µA to 200µA.

Changed I_ILmin. from -150µA to -200µA.

2.5V LVPECL DC Characteristics - changed I_IHmax. from 150µA to 200µA.

Changed I_ILmin. from -150µA to -200µA.

5V LVPECL DC Characteristics - changed I_IHmax. from 150µA to 200µA.

Changed I_ILmin. from -150µA to -200µA.

ECL DC Characteristics - changed I_IHmax. from 150µA to 200µA.

Changed I_ILmin. from -150µA to -200µA.

T4C

T4D

T4E

B

2/7/08

9

Updated LVPECL Clock Input Interface Section.

12

13

Added Termination for 5V LVPECL Outputs.

Power Considerations - updated Junction Temperature equation with worst

case thermal resistance of 46.2°C/W.

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

17

ICS853013AM REV. B OCTOBER 24, 2008

ICS853013

LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

netcom@idt.com

480-763-2056

Corporate Headquarters Asia

Japan

Europe

Integrated Device Technology, Inc. Integrated Device Technology NIPPON IDT KK

IDT Europe, Limited

6024 Silver Creek Valley Road

San Jose, CA 95138

United States

IDT (S) Pte. Ltd.

Sanbancho Tokyu, Bld. 7F,

8-1 Sanbancho

Chiyoda-ku, Tokyo 102-0075 KT22 7TU

321 Kingston Road

Leatherhead, Surrey

1 Kallang Sector, #07-01/06

Kolam Ayer Industrial Park

Singapore 349276

800 345 7015

+81 3 3221 9822

England

+408 284 8200 (outside U.S.)

+65 67443356

Fax: +65 67441764

Fax: +81 3 3221 9824

+44 (0) 1372 363 339

Fax: +44 (0) 1372 37885

idteurope@idt.com

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

www.IDT.com

Printed in USA