ICL232
Pin Descriptions (Continued)
PDIP, CERDIP
SOIC
9
PIN NAME
DESCRIPTION
9
R2out
Receiver 2 TTL/CMOS output.
10
11
12
13
14
15
16
10
11
T2
T1
Transmitter 2 TTL/CMOS input, with internal 400K pullup resistor to V
Transmitter 1 TTL/CMOS input, with internal 400K pullup resistor to V
Receiver 1 TTL/CMOS output.
.
.
IN
IN
CC
CC
12
13
14
15
16
R1
OUT
R1
RS-232 Receiver 1 input, with internal 5K pulldown resistor to GND.
RS-232 Transmitter 1 output ±10V (typical).
Supply Ground.
IN
T1
OUT
GND
V
Positive Power Supply +5V ±10%
CC
VOLTAGE DOUBLER
VOLTAGE INVERTER
+
+
S2
S5
S1
S3
C2
C1
V+ = 2V
S6
CC
V
GND
CC
+
-
+
-
+
-
+
-
C3
C2
C4
C1
V
GND
CC
V- = -(V+)
GND
C1-
S4
C2-
S7
S8
RC
OSCILLATOR
FIGURE 5. DUAL CHARGE PUMP
Detailed Description
The ICL232 is a dual RS-232 transmitter/receiver powered by
a single +5V power supply which meets all ElA RS232C
specifications and features low power consumption. The
functional diagram illustrates the major elements of the
ICL232. The circuit is divided into three sections: a voltage
doubler/inverter, dual transmitters, and dual receivers Voltage
Converter.
T1 , T2
IN
IN
90%
10%
V
V
OH
T1
, T2
OUT
OUT
OL
t
t
f
r
(0.8) (V
- V
OL
)
(0.8) (V - V
)
Instantaneous
OH
t
OL OH
=
or
Slew Rate (SR)
t
f
r
An equivalent circuit of the dual charge pump is illustrated in
Figure 5.
FIGURE 6. SLEW RATE DEFINITION
Transmitters
The voltage quadrupler contains two charge pumps which use
two phases of an internally generated clock to generate +10V
and -10V. The nominal clock frequency is 16kHz. During
The transmitters are TTL/CMOS compatible inverters which
translate the inputs to RS-232 outputs. The input logic
threshold is about 26% of V , or 1.3V for V
= 5V. A logic
CC CC
phase one of the clock, capacitor C1 is charged to V
.
CC
1 at the input results in a voltage of between -5V and V- at the
output, and a logic 0 results in a voltage between +5V and (V+
- 0.6V). Each transmitter input has an internal 400kΩ pullup
resistor so any unused input can be left unconnected and its
output remains in its low state. The output voltage swing
meets the RS-232C specification of ±5V minimum with the
worst case conditions of: both transmitters driving 3kΩ
During phase two, the voltage on C1 is added to V
CC
,
producing a signal across C2 equal to twice V . At the same
CC
time, C3 is also charged to 2V , and then during phase one,
CC
it is inverted with respect to ground to produce a signal across
C4 equal to -2V . The voltage converter accepts input
CC
voltages up to 5.5V. The output impedance of the doubler (V+)
is approximately 200Ω, and the output impedance of the
inverter (V-) is approximately 450Ω. Typical graphs are
presented which show the voltage converters output vs input
voltage and output voltages vs load characteristics. The test
circuit (Figure 3) uses 1µF capacitors for C1-C4, however, the
value is not critical. Increasing the values of C1 and C2 will
lower the output impedance of the voltage doubler and
inverter, and increasing the values of the reservoir capacitors,
C3 and C4, lowers the ripple on the V+ and V- supplies.
minimum load impedance, V
= 4.5V, and maximum
CC
allowable operating temperature. The transmitters have an
internally limited output slew rate which is less than 30V/µs.
The outputs are short circuit protected and can be shorted to
ground indefinitely. The powered down output impedance is a
FN3020.7
5
July 28, 2005
