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June 1991  
Revised September 2000  
74ACTQ652  
Quiet Series Transceiver/Register  
General Description  
Features  
The ACTQ652 consists of bus transceiver circuits with D-  
type flip-flops, and control circuitry arranged for multiplexed  
transmission of data directly from the input bus or from  
internal registers. Data on the A or B bus will be clocked  
into the registers as the appropriate clock pin goes to the  
HIGH logic level. Output Enable pins (OEAB, OEBA) are  
provided to control the transceiver function.  
■ Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
■ Guaranteed pin-to-pin skew AC performance  
■ Independent registers for A and B buses  
■ Multiplexed real-time and stored data  
■ Outputs source/sink 24 mA  
■ TTL-compatible inputs  
The ACTQ652 utilizes Fairchild FACT Quiet Series tech-  
nology to guarantee quiet output switching and improved  
dynamic threshold performance. FACT Quiet Series fea-  
tures GTO output control and undershoot corrector in  
addition to split ground bus for superior performance.  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ652SC  
74ACTQ652MTC  
74ACTQ652SPC  
M24B  
MTC24  
N24C  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
A0–A7, B0–B7  
CPAB, CPBA  
SAB, SBA  
A and B Inputs/3-STATE Outputs  
Clock Inputs  
Select Inputs  
OEAB, OEBA  
Output Enable Inputs  
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS010933  
www.fairchildsemi.com  
Function Table  
Inputs  
Inputs/Outputs (Note 1)  
Operating Mode  
A0 thru A7  
B0 thru B7  
OEAB OEBA CPAB  
CPBA  
SAB  
X
SBA  
X
L
L
H
H
H
H
X
L
H or L  
H or L  
Isolation  
Store A and B Data  
Input  
Input  
X
X
X
H
L
H or L  
X
X
Input  
Input  
Not Specified Store A, Hold B  
X
X
Output  
Input  
Store A in Both Registers  
H or L  
X
X
Not Specified  
Output  
Hold A, Store B  
L
X
X
Input  
Store B in Both Registers  
Real-Time B Data to A Bus  
Store B Data to A Bus  
Real-Time A Data to B Bus  
Stored A Data to B Bus  
Stored A Data to B Bus and  
Stored B Data to A Bus  
L
L
X
X
X
H or L  
X
X
L
Output  
Input  
Input  
L
L
X
H
X
H
H
H
H
X
L
Output  
Output  
H or L  
X
H
X
H
L
H or L  
H or L  
H
H
Output  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
= LOW-to-HIGH Clock Transition  
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,  
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
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2
Functional Description  
In the transceiver mode, data present at the HIGH imped-  
ance port may be stored in either the A or B register or  
both.  
Data on the A or B data bus, or both can be stored in the  
internal D-type flip-flop by LOW-to-HIGH transitions at the  
appropriate Clock Inputs (CPAB, CPBA) regardless of the  
Select or Output Enable Inputs. When SAB and SBA are in  
the real time transfer mode, it is also possible to store data  
without using the internal D-type flip-flops by simulta-  
neously enabling OEAB and OEBA. In this configuration  
each Output reinforces its Input. Thus when all other data  
sources to the two sets of bus lines are in a HIGH imped-  
ance state, each set of bus lines will remain at its last state.  
The select (SAB, SBA) controls can multiplex stored and  
real-time.  
The examples in Figure 1 demonstrate the four fundamen-  
tal bus-management functions that can be performed with  
the Octal bus transceivers and receivers.  
Note A: Real-Time  
Note B: Real-Time  
Transfer Bus B to Bus A  
Transfer Bus A to Bus B  
OEAB OEBA CPAB CPBA SAB  
SBA  
L
OEAB OEBA CPAB CPBA SAB  
SBA  
X
L
L
X
X
X
H
H
X
X
L
Note C: Storage  
Note D: Transfer Storage  
Data to A or B  
OEAB OEBA CPAB CPBA SAB  
SBA  
X
OEAB OEBA CPAB CPBA SAB  
H or L H or L  
SBA  
H
X
L
L
H
X
H
X
X
X
X
H
L
H
X
X
X
FIGURE 1.  
3
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Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
)
−0.5V to +7.0V  
DC Input Diode Current (IIK  
VI = −0.5V  
)
Supply Voltage (VCC  
)
4.5V to 5.5V  
0V to VCC  
−20 mA  
+20 mA  
Input Voltage (VI)  
VI = VCC + 0.5V  
Output Voltage (VO)  
0V to VCC  
DC Input Voltage (VI)  
−0.5V to VCC + 0.5V  
Operating Temperature (TA)  
−40°C to +85°C  
DC Output Diode Current (IOK  
)
Minimum Input Edge Rate ∆V/∆t  
V
V
O = −0.5V  
−20 mA  
+20 mA  
V
IN from 0.8V to 2.0V  
O = VCC + 0.5V  
VCC @ 4.5V, 5.5V  
125 mV/ns  
DC Output Voltage (VO)  
DC Output Source  
−0.5V to VCC + 0.5V  
or Sink Current (IO)  
± 50 mA  
DC VCC or Ground Current  
per Output Pin (ICC or IGND  
)
± 50 mA  
Note 2: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, with-  
out exception, to ensure that the system design is reliable over its power  
supply, temperature, and output/input loading variables. Fairchild does not  
recommend operation of FACT circuits outside databook specifications.  
Storage Temperature (TSTG  
DC Latch-Up Source  
or Sink Current  
)
−65°C to +150°C  
± 300 mA  
140°C  
Junction Temperature (TJ)  
PDIP  
DC Electrical Characteristics  
VCC  
T
A = +25°C  
TA = −40°C to +85°C  
Symbol  
VIH  
Parameter  
Units  
Conditions  
(V)  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
Typ  
1.5  
Guaranteed Limits  
Minimum HIGH Level  
Input Voltage  
2.0  
2.0  
2.0  
0.8  
0.8  
4.4  
5.4  
V
OUT = 0.1V  
or VCC − 0.1V  
OUT = 0.1V  
or VCC − 0.1V  
V
V
V
1.5  
2.0  
0.8  
0.8  
4.4  
5.4  
VIL  
Maximum LOW Level  
Input Voltage  
1.5  
V
1.5  
VOH  
Minimum HIGH Level  
Output Voltage  
4.49  
5.49  
I
OUT = −50 µA  
IN = VIL or VIH  
V
4.5  
5.5  
4.5  
5.5  
3.86  
4.86  
0.1  
3.76  
4.76  
0.1  
V
V
V
I
I
OH = −24 mA  
OH = −24 mA (Note 3)  
VOL  
Maximum LOW Level  
Output Voltage  
0.001  
0.001  
I
OUT = 50 µA  
0.1  
0.1  
V
IN = VIL or VIH  
4.5  
5.5  
0.36  
0.36  
0.44  
0.44  
I
I
OL = 24 mA  
OL = 24 mA (Note 3)  
IIN  
Maximum Input  
5.5  
5.5  
± 0.1  
± 0.6  
± 1.0  
± 6.0  
µA  
µA  
VI = VCC, GND  
Leakage Current  
IOZT  
Maximum I/O  
VI = VIL, VIH  
Leakage Current  
V
O = VCC, GND  
ICCT  
IOLD  
IOHD  
ICC  
Maximum ICC/Input  
Minimum Dynamic  
Output Current (Note 4)  
Maximum Quiescent  
Supply Current  
5.5  
5.5  
5.5  
0.6  
1.5  
75  
mA  
mA  
mA  
VI = VCC − 2.1V  
V
V
OLD = 1.65V Max  
OHD = 3.85V Min  
−75  
5.5  
5.0  
5.0  
5.0  
5.0  
8.0  
1.5  
80.0  
µA  
V
V
IN = VCC or GND  
VOLP  
VOLV  
VIHD  
VILD  
Maximum HIGH Level  
Output Noise  
Figures 2, 3  
1.1  
−0.6  
1.9  
(Note 5)(Note 6)  
Figures 2, 3  
Maximum LOW Level  
Output Noise  
−1.2  
2.2  
V
(Note 5)(Note 6)  
Minimum HIGH Level  
Dynamic Input Voltage  
Maximum LOW Level  
Dynamic Input Voltage  
V
(Note 5)(Note 7)  
(Note 5)(Note 7)  
1.2  
0.8  
V
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4
DC Electrical Characteristics (Continued)  
Note 3: All outputs loaded; thresholds on input associated with output under test.  
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.  
Note 5: PDIP package.  
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.  
Note 7: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),  
0V to threshold (VIHD), f = 1 MHz.  
AC Electrical Characteristics  
VCC  
T
A = +25°C  
T
A = −40°C to +85°C  
L = 50 pF  
Max  
C
L = 50 pF  
C
Symbol  
Parameter  
(V)  
(Note 8)  
5.0  
Units  
Min  
Typ  
Max  
Min  
fMAX  
Maximum Clock Frequency  
Propagation Delay  
Clock to Bus  
MHz  
ns  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
tPZH  
tPZL  
tPHZ  
tPLZ  
tS(H)  
tS(L)  
tH(H)  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
2.0  
2.0  
2.5  
2.0  
1.0  
2.0  
1.0  
3.0  
1.5  
4.0  
7.0  
6.5  
6.5  
7.0  
5.0  
7.0  
5.0  
9.5  
9.0  
2.0  
2.0  
2.5  
2.0  
1.0  
2.0  
1.0  
3.0  
1.5  
4.0  
10.0  
9.5  
Propagation Delay  
Bus to Bus  
ns  
ns  
Propagation Delay  
SBA or SAB to A or B  
Enable Time  
10.0  
10.5  
8.0  
10.5  
11.0  
8.5  
OEBA to A (Note 8)  
Disable Time  
ns  
OEBA to A (Note 8)  
Enable Time  
10.5  
8.0  
11.0  
8.5  
OEAB to B  
Disable Time  
ns  
ns  
ns  
ns  
OEAB to B  
Setup Time, HIGH or  
LOW, Bus to Clock  
Hold Time, HIGH or  
LOW, Bus to Clock  
Clock Pulse Width  
HIGH or LOW  
t
H(L)  
tW(H)  
tW(L)  
tOSHL  
tOSLH  
Output to Output Skew (Note 9)  
A to B, B to A or  
Clock to Output  
5.0  
0.5  
1.0  
1.0  
ns  
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.  
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any separate outputs of the same device. The spec-  
ification applies to any output switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.  
Capacitance  
Symbol  
Parameter  
Input Capacitance  
Power Dissipation Capacitance  
Typ  
4.5  
54  
Units  
pF  
Conditions  
CIN  
V
V
CC = 5.0V  
CC = 5.0V  
CPD  
pF  
5
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FACT Noise Characteristics  
The setup of a noise characteristics measurement is critical  
to the accuracy and repeatability of the tests. The following  
is a brief description of the setup used to measure the  
noise characteristics of FACT.  
VOLP/VOLV and VOHP/V OHV:  
•
Determine the quiet output pin that demonstrates the  
greatest noise levels. The worst case pin will usually be  
the furthest from the ground pin. Monitor the output volt-  
ages using a 50Ω coaxial cable plugged into a standard  
SMB type connector on the test fixture. Do not use an  
active FET probe.  
Equipment:  
Hewlett Packard Model 8180A Word Generator  
PC-163A Test Fixture  
•
•
Measure VOLP and VOLVon the quiet output during the  
Tektronics Model 7854 Oscilloscope  
Procedure:  
worst case transition for active and enable. Measure  
VOHP and VOHV on the quiet output during the worst  
1. Verify Test Fixture Loading: Standard Load 50 pF,  
case active and enable transition.  
500Ω.  
Verify that the GND reference recorded on the oscillo-  
scope has not drifted to ensure the accuracy and repeat-  
ability of the measurements.  
2. Deskew the HFS generator so that no two channels  
have greater than 150 ps skew between them. This  
requires that the oscilloscope be deskewed first. It is  
important to deskew the HFS generator channels  
before testing. This will ensure that the outputs switch  
simultaneously.  
V
ILD and VIHD:  
•
Monitor one of the switching outputs using a 50Ω coaxial  
cable plugged into a standard SMB type connector on  
the test fixture. Do not use an active FET probe.  
3. Terminate all inputs and outputs to ensure proper load-  
ing of the outputs and that the input levels are at the  
correct voltage.  
•
•
•
First increase the input LOW voltage level, VIL, until the  
output begins to oscillate or steps out a min of 2 ns.  
Oscillation is defined as noise on the output LOW level  
that exceeds VIL limits, or on output HIGH levels that  
4. Set the HFS generator to toggle all but one output at a  
frequency of 1 MHz. Greater frequencies will increase  
DUT heating and effect the results of the measure-  
ment.  
exceed VIH limits. The input LOW voltage level at which  
oscillation occurs is defined as VILD  
.
5. Set the HFS generator input levels at 0V LOW and 3V  
HIGH for ACT devices and 0V LOW and 5V HIGH for  
AC devices. Verify levels with an oscilloscope.  
Next decrease the input HIGH voltage level, VIH until the  
output begins to oscillate or steps out a min of 2 ns.  
Oscillation is defined as noise on the output LOW level  
that exceeds V limits, or on output HIGH levels that  
IL  
exceed VIH limits. The input HIGH voltage level at which  
oscillation occurs is defined as V IHD  
.
Verify that the GND reference recorded on the oscillo-  
scope has not drifted to ensure the accuracy and repeat-  
ability of the measurements.  
Note A: VOHV and VOLP are measured with respect to ground reference.  
Note B: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns,  
t
f = 3 ns, skew < 150 ps.  
FIGURE 2. Quiet Output Noise Voltage Waveforms  
FIGURE 3. Simultaneous Switching Test Circuit  
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6
Physical Dimensions inches (millimeters) unless otherwise noted  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
Package Number M24B  
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC24  
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Package Number N24C  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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9
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