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February 5, 2009  
ADC081C021/ADC081C027  
I2C-Compatible, 8-Bit Analog-to-Digital Converter with  
Alert Function  
General Description  
Features  
The ADC081C021 is  
a
low-power, monolithic, 8-bit,  
I2C-Compatible 2-wire Interface which supports standard  
■
analog-to-digital converter (ADC) that operates from a +2.7  
to 5.5V supply. The converter is based on a successive ap-  
proximation register architecture with an internal track-and-  
hold circuit that can handle input frequencies up to 11MHz.  
The ADC081C021 operates from a single supply which also  
serves as the reference. The device features an  
I2C-compatible serial interface that operates in all three speed  
modes, including high speed mode (3.4MHz).  
(100kHz), fast (400kHz), and high speed (3.4MHz) modes  
Extended power supply range (+2.7V to +5.5V)  
■
■
■
■
■
■
Up to nine pin-selectable chip addresses (MSOP-8 only)  
Out-of-range Alert Function  
Automatic Power-down mode while not converting  
Very small TSOT-6 and MSOP-8 packages  
±8kV HBM ESD protection (SDA, SCL)  
The ADC's Alert feature provides an interrupt that is activated  
when the analog input violates a programmable upper or low-  
er limit value. The device features an automatic conversion  
mode, which frees up the controller and I2C interface. In this  
mode, the ADC continuously monitors the analog input for an  
"out-of-range" condition and provides an interrupt if the mea-  
sured voltage goes out-of-range.  
Key Specifications  
Resolution  
Conversion Time  
INL & DNL  
Throughput Rate  
Power Consumption (at 22ksps)  
8 bits; no missing codes  
1µs (typ)  
■
■
■
■
■
±0.2 LSB (max)  
188.9ksps (max)  
The ADC081C021 comes in two packages: a small TSOT-6  
package with an alert output, and an MSOP-8 package with  
an alert output and two address selection inputs. The  
ADC081C027 comes in a small TSOT-6 package with an ad-  
dress selection input. The ADC081C027 provides three pin-  
selectable addresses while the MSOP-8 version of the  
ADC081C021 provides nine pin-selectable addresses. Pin-  
compatible alternatives to the TSOT-6 options are available  
with additional address options.  
3V Supply  
5V Supply  
0.26 mW (typ)  
0.78 mW (typ)  
—
—
Applications  
System Monitoring  
■
■
■
■
Peak Detection  
Portable Instruments  
Normal power consumption using a +3V or +5V supply is  
0.26mW or 0.78mW, respectively. The automatic power-  
down feature reduces the power consumption to less than  
1µW while not converting. Operation over the industrial tem-  
perature range of −40°C to +105°C is guaranteed. Their low  
power consumption and small packages make this family of  
ADCs an excellent choice for use in battery operated equip-  
ment.  
Medical Instruments  
Test Equipment  
■
Pin-Compatible Alternatives  
All devices are fully pin and function compatible.  
Resolution TSOT-6 (Alert only) TSOT-6 (Addr only)  
and MSOP-8  
The ADC081C021 and ADC081C027 are part of a family of  
pin-compatible ADCs that also provide 10- and 12-bit resolu-  
tion. For 10-bit ADCs see the ADC101C021 and  
ADC101C027. For 12-bit ADCs see the ADC121C021 and  
ADC121C027.  
12-bit  
10-bit  
8-bit  
ADC121C021  
ADC101C021  
ADC081C021  
ADC121C027  
ADC101C027  
ADC081C027  
Connection Diagrams  
30052102  
30052110  
30052101  
I2C® is a registered trademark of Phillips Corporation.  
© 2009 National Semiconductor Corporation  
300521  
www.national.com  
Ordering Information  
Order Code  
Option  
Alert pin  
Package  
TSOT-6  
Top Mark  
X34C  
ADC081C021CIMK  
ADC081C021CIMKX  
ADC081C027CIMK  
ADC081C027CIMKX  
ADC081C021CIMM  
ADC081C021CIMMX  
Alert pin  
TSOT-6 Tape-and-Reel  
TSOT-6  
X34C  
Address pin  
X35C  
Address pin  
TSOT-6 Tape-and-Reel  
MSOP-8  
X35C  
Alert and Address pins  
Alert and Address pins  
X36C  
MSOP-8  
X36C  
Shipped with the ADC081C021  
(TSOT-6). Also compatible with  
the ADC081C027 option.  
Please order samples.  
ADC081C021EB  
Evaluation Board  
Block Diagram  
30052103  
www.national.com  
2
Pin Descriptions  
Symbol  
Type  
Equivalent Circuit  
Description  
Power and unbufferred reference voltage. VA must be free  
of noise and decoupled to GND.  
VA  
Supply  
GND  
VIN  
Ground  
Ground for all on-chip circuitry.  
Analog input. This signal can range from GND to VA.  
Analog Input  
See Figure 4  
Alert output. Can be configured as active high or active  
low. This is an open drain data line that must be pulled to  
the supply (VA) with an external pull-up resistor.  
ALERT  
Digital Output  
Digital Input  
Serial Clock Input. SCL is used together with SDA to  
control the transfer of data in and out of the device. This is  
an open drain data line that must be pulled to the supply  
(VA) with an external pull-up resistor. This pin's extended  
ESD tolerance( 8kV HBM) allows extension of the I2C bus  
across multiple boards without extra ESD protection.  
SCL  
Serial Data bi-directional connection. Data is clocked into  
or out of the internal 16-bit register with SCL. This is an  
open drain data line that must be pulled to the supply  
(VA) with an external pull-up resistor. This pin's extended  
ESD tolerance( 8kV HBM) allows extension of the I2C bus  
across multiple boards without extra ESD protection.  
Digital  
Input/Output  
SDA  
Tri-level Address Selection Input. Sets Bits A0 & A1 of the  
7-bit slave address. (see Table 1)  
ADDR0  
ADDR1  
Digital Input,  
three levels  
Tri-level Address Selection Input. Sets Bits A2 & A3 of the  
7-bit slave address. (see Table 1)  
Package Pinouts  
VA  
VIN  
GND  
ALERT  
SCL  
SDA  
ADR0  
ADR1  
ADC081C021  
1
2
3
4
5
6
N/A  
N/A  
TSOT-6  
ADC081C027  
1
5
2
7
3
4
N/A  
2
5
1
6
8
4
3
N/A  
6
TSOT-6  
ADC081C021  
MSOP-8  
3
www.national.com  
Absolute Maximum Ratings  
(Notes 1, 2)  
Operating Ratings (Notes 1, 2)  
Operating Temperature Range  
−40°C ≤ TA ≤ +105°C  
Supply Voltage, VA  
+2.7V to 5.5V  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
Analog Input Voltage, VIN  
Digital Input Voltage (Note 7)  
Sample Rate  
0V to VA  
0V to 5.5V  
Supply Voltage, VA  
-0.3V to +6.5V  
up to 188.9 ksps  
Voltage on any Analog Input Pin to  
GND  
Voltage on any Digital Input Pin to  
GND  
Input Current at Any Pin (Note 3)  
Package Input Current (Note 3)  
Power Dissipation at TA = 25°C  
−0.3V to (VA +0.3V)  
Package Thermal Resistances  
Package  
θJA  
−0.3V to 6.5V  
±15 mA  
6-Lead TSOT  
8-Lead MSOP  
250°C/W  
200°C/W  
±20 mA  
Soldering  
process  
must  
comply  
with  
National  
See (Note 4)  
Semiconductor's Reflow Temperature Profile specifications.  
Refer to www.national.com/packaging. (Note 6)  
ESD Susceptibility (Note 5)  
VA, GND, VIN, ALERT,  
ADR pins:  
ꢀ
2500V  
250V  
1250V  
ꢀ
Human Body Model  
Machine Model  
Charged Device Model  
(CDM)  
SDA, SCL pins:  
Human Body Model  
Machine Model  
8000V  
400V  
Junction Temperature  
Storage Temperature  
+150°C  
−65°C to +150°C  
Electrical Characteristics  
The following specifications apply for VA = +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz,  
fIN = 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C  
unless otherwise noted.  
Typical  
(Note 9)  
Limits  
(Note 9)  
Symbol  
Parameter  
Conditions  
Units (Limits)  
STATIC CONVERTER CHARACTERISTICS  
Resolution with No Missing Codes  
8
Bits  
VA = +2.7V to +3.6V  
±0.04  
±0.1  
±0.2  
LSB (max)  
Integral Non-Linearity (End Point  
Method)  
INL  
VA = +2.7V to +5.5V. fSCL up to 400kHz  
(Note 13)  
±0.25  
±0.2  
±0.25  
±0.5  
±0.5  
±0.4  
LSB (max)  
LSB (max)  
LSB (max)  
LSB (max)  
LSB (max)  
LSB (max)  
VA = +2.7V to +3.6V  
+0.04  
±0.08  
+0.26  
+0.25  
-0.01  
DNL  
Differential Non-Linearity  
VA = +2.7V to +5.5V. fSCL up to 400kHz  
(Note 13)  
VA = +2.7V to +3.6V  
VOFF  
GE  
Offset Error  
Gain Error  
VA = +2.7V to +5.5V. fSCL up to 400kHz  
(Note 13)  
DYNAMIC CONVERTER CHARACTERISTICS  
ENOB  
SNR  
Effective Number of Bits  
Signal-to-Noise Ratio  
7.98  
49.8  
7.8  
49  
Bits (min)  
dB (min)  
dB (max)  
dB (min)  
dB (min)  
THD  
Total Harmonic Distortion  
−70.6  
49.8  
−64  
49  
SINAD Signal-to-Noise Plus Distortion Ratio  
SFDR  
Spurious-Free Dynamic Range  
-68.8  
65  
VA = +3.0V,  
Intermodulation Distortion, Second  
Order Terms (IMD2)  
IMD  
−75.5  
−71.8  
dB  
dB  
fa = 1.035 kHz, fb = 1.135 kHz  
VA = +3.0V,  
Intermodulation Distortion, Third  
Order Terms (IMD3)  
fa = 1.035 kHz, fb = 1.135 kHz  
www.national.com  
4
Typical  
(Note 9)  
Limits  
(Note 9)  
Symbol  
Parameter  
Conditions  
Units (Limits)  
VA = +3.0V  
VA = +5.0V  
8
MHz  
MHz  
FPBW  
Full Power Bandwidth (−3dB)  
11  
ANALOG INPUT CHARACTERISTICS  
VIN  
0 to VA  
Input Range  
V
µA (max)  
pF  
IDCL  
DC Leakage Current (Note 10)  
±1  
Track Mode  
Hold Mode  
30  
3
CINA  
Input Capacitance  
pF  
SERIAL INTERFACE INPUT CHARACTERISTICS (SCL, SDA)  
VIH  
VIL  
0.7 x VA  
0.3 x VA  
±1  
Input High Voltage  
Input Low Voltage  
Input Current (Note 10)  
Input Pin Capacitance  
Input Hysteresis  
V (min)  
V (max)  
µA (max)  
pF  
IIN  
CIN  
3
VHYST  
0.1 x VA  
V (min)  
ADDRESS SELECTION INPUT CHARACTERISTICS (ADDR)  
VIH  
VIL  
IIN  
VA - 0.5V  
0.5  
Input High Voltage  
Input Low Voltage  
V (min)  
V (max)  
µA (max)  
Input Current (Note 10)  
±1  
LOGIC OUTPUT CHARACTERISTICS, OPEN-DRAIN (SDA, ALERT)  
ISINK = 3 mA  
0.4  
0.6  
V (max)  
V (max)  
VOL  
IOZ  
Output Low Voltage  
ISINK = 6 mA  
High-Impedence Output  
Leakage Current (Note 10)  
±1  
µA (max)  
Output Coding  
Straight (Natural) Binary  
5
www.national.com  
Typical  
(Note 9)  
Limits  
(Note 9)  
Symbol  
Parameter  
Conditions  
Units (Limits)  
POWER REQUIREMENTS  
Supply Voltage Minimum  
Supply Voltage Maximum  
Continuous Operation Mode -- 2-wire interface active.  
2.7  
5.5  
V (min)  
V (max)  
VA  
VA = 2.7V to 3.6V  
0.08  
0.16  
0.37  
0.74  
0.26  
0.78  
1.22  
3.67  
0.14  
0.30  
0.55  
0.99  
mA (max)  
mA (max)  
mA (max)  
mA (max)  
mW  
fSCL=400kHz  
VA = 4.5V to 5.5V  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 3.0V  
IN  
Supply Current  
fSCL=3.4MHz  
fSCL=400kHz  
fSCL=3.4MHz  
VA = 5.0V  
mW  
PN  
Power Consumption  
VA = 3.0V  
mW  
VA = 5.0V  
mW  
Automatic Conversion Mode -- 2-wire interface stopped and quiet (SCL = SDA = VA). fSAMPLE = TCONVERT * 32  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 3.0V  
0.41  
0.78  
1.35  
3.91  
0.59  
1.2  
mA (max)  
mA (max)  
mW  
IA  
Supply Current  
PA  
Power Consumption  
VA = 5.0V  
mW  
Power Down Mode (PD1) -- 2-wire interface stopped and quiet. (SCL = SDA = VA).(Note 10)  
IPD1  
Supply Current  
0.1  
0.5  
0.2  
0.9  
µA (max)  
µW (max)  
PPD1  
Power Consumption  
Power Down Mode (PD2) -- 2-wire interface active. Master communicating with a different device on the bus.  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 3.0V  
13  
27  
45  
80  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
mW  
fSCL=400kHz  
fSCL=3.4MHz  
fSCL=400kHz  
fSCL=3.4MHz  
IPD2  
Supply Current  
89  
150  
250  
168  
0.04  
0.14  
0.29  
0.84  
VA = 5.0V  
mW  
PPD2  
Power Consumption  
VA = 3.0V  
mW  
VA = 5.0V  
mW  
www.national.com  
6
A.C. and Timing Characteristics  
The following specifications apply for VA = +2.7V to +5.5V. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at  
TA = 25°C, unless otherwise specified.  
Limits  
(Notes 9,  
12)  
Typical  
(Note 9)  
Units  
(Limits)  
Symbol  
Parameter  
Conditions (Note 12)  
CONVERSION RATE  
Conversion Time  
1
µs  
fSCL = 100kHz  
5.56  
22.2  
94.4  
188.9  
ksps  
ksps  
ksps  
ksps  
fSCL = 400kHz  
fSCL = 1.7MHz  
fSCL = 3.4MHz  
fCONV  
Conversion Rate  
DIGITAL TIMING SPECS (SCL, SDA)  
Standard Mode  
Fast Mode  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
100  
400  
3.4  
kHz (max)  
kHz (max)  
MHz (max)  
MHz (max)  
fSCL  
Serial Clock Frequency  
SCL Low Time  
1.7  
Standard Mode  
Fast Mode  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
4.7  
1.3  
160  
320  
us (min)  
us (min)  
ns (min)  
ns (min)  
tLOW  
Standard Mode  
Fast Mode  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
4.0  
0.6  
60  
us (min)  
us (min)  
ns (min)  
ns (min)  
tHIGH  
SCL High Time  
120  
Standard Mode  
Fast Mode  
High Speed Mode  
250  
100  
10  
ns (min)  
ns (min)  
ns (min)  
tSU;DAT  
Data Setup Time  
0
3.45  
us (min)  
us (max)  
Standard Mode (Note 14)  
Fast Mode (Note 14)  
0
0.9  
us (min)  
us (max)  
tHD;DAT  
Data Hold Time  
0
70  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
0
150  
ns (min)  
ns (max)  
Standard Mode  
Fast Mode  
High Speed Mode  
4.7  
0.6  
160  
us (min)  
us (min)  
ns (min)  
Setup time for a start or a repeated  
start condition  
tSU;STA  
Standard Mode  
Fast Mode  
High Speed Mode  
4.0  
0.6  
160  
us (min)  
us (min)  
ns (min)  
Hold time for a start or a repeated start  
condition  
tHD;STA  
Bus free time between a stop and start Standard Mode  
4.7  
1.3  
us (min)  
us (min)  
tBUF  
condition  
Fast Mode  
Standard Mode  
Fast Mode  
High Speed Mode  
4.0  
0.6  
160  
us (min)  
us (min)  
ns (min)  
tSU;STO  
Setup time for a stop condition  
7
www.national.com  
Limits  
(Notes 9,  
12)  
Typical  
(Note 9)  
Units  
(Limits)  
Symbol  
Parameter  
Conditions (Note 12)  
Standard Mode  
1000  
20+0.1Cb  
300  
ns (max)  
ns (min)  
ns (max)  
Fast Mode  
trDA  
Rise time of SDA signal  
10  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
20  
160  
ns (min)  
ns (max)  
High Speed Mode, Cb = 400pF  
Standard Mode  
250  
20+0.1Cb  
250  
ns (max)  
ns (min)  
ns (max)  
Fast Mode  
tfDA  
trCL  
trCL1  
tfCL  
Fall time of SDA signal  
10  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
20  
160  
ns (min)  
ns (max)  
High Speed Mode, Cb = 400pF  
Standard Mode  
1000  
20+0.1Cb  
300  
ns (max)  
ns (min)  
ns (max)  
Fast Mode  
Rise time of SCL signal  
10  
40  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
20  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 400pF  
Standard Mode  
1000  
20+0.1Cb  
300  
ns (max)  
ns (min)  
ns (max)  
Fast Mode  
Rise time of SCL signal after a  
repeated start condition and after an  
acknowledge bit.  
10  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
20  
160  
ns (min)  
ns (max)  
High Speed Mode, Cb = 400pF  
Standard Mode  
300  
20+0.1Cb  
300  
ns (max)  
ns (min)  
ns (max)  
Fast Mode  
Fall time of a SCL signal  
10  
40  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
20  
80  
ns (min)  
ns (max)  
Capacitive load for each bus line (SCL  
and SDA)  
Cb  
400  
pF (max)  
Pulse Width of spike suppressed  
(Note 11)  
Fast Mode  
High Speed Mode  
50  
10  
ns (max)  
ns (max)  
tSP  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed  
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test  
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.  
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.  
Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited per the Absolute Maximum Ratings. The  
maximum package input current rating limits the number of pins that can safely exceed the power supplies.  
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the  
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values  
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond  
the operating ratings, or the power supply polarity is reversed).  
Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charged  
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.  
Note 6: Reflow temperature profiles are different for lead-free packages.  
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8
 
 
 
 
 
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For  
example, if VA is 3V, the digital input pins can be driven with a 5V logic device.  
30052104  
Note 8: To guarantee accuracy, it is required that VA be well bypassed and free of noise.  
Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality  
Level).  
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.  
Note 11: Spike suppression filtering on SCL and SDA will suppress spikes that are less than 50ns for standard and fast modes, and less than 10ns for hs-mode.  
Note 12: Cb refers to the capacitance of one bus line. Cb is expressed in pF units.  
Note 13: The ADC will meet Minimum/Maximum specifications for fSCL up to 3.4MHz and VA = 2.7V to 3.6V when operating in the Quiet Interface Mode (Section  
1.11).  
Note 14: The ADC081C021 will provide a minimum data hold time of 300ns to comply with the I2C Specification.  
Timing Diagrams  
30052160  
FIGURE 1. Serial Timing Diagram  
9
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Specification Definitions  
ACQUISITION TIME is the time required for the ADC to ac-  
quire the input voltage. During this time, the hold capacitor is  
charged by the input voltage.  
OFFSET ERROR is the deviation of the first code transition  
(000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB).  
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in  
dB, of the rms value of the input signal to the rms value of the  
sum of all other spectral components below one-half the sam-  
pling frequency, not including harmonics or d.c.  
APERTURE DELAY is the time between the start of a con-  
version and the time when the input signal is internally ac-  
quired or held for conversion.  
CONVERSION TIME is the time required, after the input volt-  
age is acquired, for the ADC to convert the input voltage to a  
digital word.  
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or  
SINAD) Is the ratio, expressed in dB, of the rms value of the  
input signal to the rms value of all of the other spectral com-  
ponents below half the clock frequency, including harmonics  
but excluding d.c.  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of  
the maximum deviation from the ideal step size of 1 LSB.  
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-  
ence, expressed in dB, between the desired signal amplitude  
to the amplitude of the peak spurious spectral component,  
where a spurious spectral component is any signal present in  
the output spectrum that is not present at the input and may  
or may not be a harmonic.  
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE  
BITS) is another method of specifying Signal-to-Noise and  
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02  
and says that the converter is equivalent to a perfect ADC of  
this (ENOB) number of bits.  
FULL POWER BANDWIDTH is a measure of the frequency  
at which the reconstructed output fundamental drops 3 dB  
below its low frequency value for a full scale input.  
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-  
pressed in dBc, of the rms total of the first n harmonic com-  
ponents at the output to the rms level of the input signal  
frequency as seen at the output. THD is calculated as  
GAIN ERROR is the deviation of the last code transition  
(111...110) to (111...111) from the ideal (VREF - 1.5 LSB), after  
adjusting for offset error.  
INTEGRAL NON-LINEARITY (INL) is a measure of the de-  
viation of each individual code from a line drawn from negative  
full scale (½ LSB below the first code transition) through pos-  
itive full scale (½ LSB above the last code transition). The  
deviation of any given code from this straight line is measured  
from the center of that code value.  
where Af1 is the RMS power of the input frequency at the out-  
put and Af2 through Afn are the RMS power in the first n  
harmonic frequencies.  
INTERMODULATION DISTORTION (IMD) is the creation of  
additional spectral components as a result of two sinusoidal  
frequencies being applied to an individual ADC input at the  
same time. It is defined as the ratio of the power in both the  
second and third order intermodulation products to the power  
in one of the original frequencies. Second order products are  
fa ± fb, where fa and fb are the two sine wave input frequencies.  
Third order products are (2fa ± fb ) and (fa ± 2fb). IMD is usually  
expressed in dB.  
THROUGHPUT TIME is the minimum time required between  
the start of two successive conversions. It is the acquisition  
time plus the conversion time.  
LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-  
est value or weight of all bits in a word. This value is  
LSB = VA / 2n  
where VA is the supply voltage for this product, and "n" is the  
resolution in bits, which is 8 for the ADC081C021.  
MISSING CODES are those output codes that will never ap-  
pear at the ADC output. The ADC081C021 is guaranteed not  
to have any missing codes.  
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest  
value or weight of all bits in a word. Its value is 1/2 of VA.  
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10  
Typical Performance Characteristics fSCL = 400kHz, fSAMPLE = 22ksps, fIN = 1kHz, VA = 5.0V, TA = +25°  
C, unless otherwise stated.  
INL vs. Code - VA=3V  
INL vs. Code - VA=5V  
INL vs. Supply  
DNL vs. Code - VA=3V  
DNL vs. Code - VA=5V  
DNL vs. Supply  
30052122  
30052123  
30052124  
30052125  
30052126  
30052127  
11  
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ENOB vs. Supply  
SINAD vs. Supply  
30052128  
30052129  
FFT Plot - VA=3V  
FFT Plot - VA=3V  
30052130  
30052131  
Offset Error vs. Temperature  
Gain Error vs. Temperature  
30052132  
30052133  
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12  
Continuous Operation Supply Current vs. VA  
Automatic Conversion Supply Current vs. VA  
30052134  
30052135  
Power Down (PD1) Supply Current vs. VA  
30052136  
13  
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1.2 ANALOG INPUT  
1.0 Functional Description  
An equivalent circuit for the input of the ADC081C021 is  
shown in Figure 4. The diodes provide ESD protection for the  
analog input. The operating range for the analog input is 0 V  
to VA. Going beyond this range will cause the ESD diodes to  
conduct and result in erratic operation. For this reason, these  
diodes should NOT be used to clamp the input signal.  
The ADC081C021 and the ADC081C027 are successive-ap-  
proximation analog-to-digital converters designed around a  
charge-redistribution digital-to-analog converter. Unless oth-  
erwise stated, references to the ADC081C021 in this section  
will apply to both the ADC081C021 and the ADC081C027.  
The capacitor C1 in Figure 4 has a typical value of 3 pF and  
is mainly the package pin capacitance. Resistor R1 is the on  
resistance (RON) of the multiplexer and track / hold switch and  
is typically 500Ω. Capacitor C2 is the ADC081C021 sampling  
capacitor, and is typically 30 pF. The ADC081C021 will de-  
liver best performance when driven by a low-impedance  
source (less than 100Ω). This is especially important when  
using the ADC081C021 to sample dynamic signals. A buffer  
amplifier may be necessary to limit source impedance. Use a  
precision op-amp to maximize circuit performance. Also im-  
portant when sampling dynamic signals is a band-pass or low-  
pass filter to reduce noise at the input.  
1.1 CONVERTER OPERATION  
Simplified schematics of the ADC081C021 in both track and  
hold operation are shown in Figure 2 and Figure 3 respec-  
tively. In Figure 2, the ADC081C021 is in track mode. SW1  
connects the sampling capacitor to the analog input channel  
and SW2 equalizes the comparator inputs. The ADC is in this  
state for approximately 0.4µs at the beginning of every con-  
version cycle, which begins at the ACK fall of SDA. Conver-  
sions occur when the conversion result register is read and  
when the ADC is in automatic conversion mode. (see Section  
1.9 AUTOMATIC CONVERSION MODE).  
Figure 3 shows the ADC081C021 in hold mode. SW1 con-  
nects the sampling capacitor to ground and SW2 unbalances  
the comparator. The control logic then instructs the charge-  
redistribution DAC to add or subtract fixed amounts of charge  
to or from the sampling capacitor until the comparator is bal-  
anced. When the comparator is balanced, the digital word  
supplied to the DAC is also the digital representation of the  
analog input voltage. This digital word is stored in the con-  
version result register and read via the 2-wire interface.  
In the Normal (non-Automatic) Conversion mode, a new con-  
version is started after the previous conversion result is read.  
In the Automatic Mode, conversions are started at set inter-  
vals, as determined by bits D7 through D5 of the Configuration  
Register. The intent of the Automatic mode is to provide a  
"watchdog" function to ensure that the input voltage remains  
within the limits set in the Alert Limit Registers. The minimum  
and maximum conversion results can then be read from the  
Lowest Conversion Register and the Highest Conversion  
Register, as described in Section 1.6 INTERNAL REGIS-  
TERS.  
30052167  
FIGURE 4. Equivalent Input Circuit  
The analog input is sampled for eight internal clock cycles, or  
for typically 400 ns, after the fall of SDA for acknowledgement.  
This time could be as long as about 530 ns. The sampling  
switch opens and the conversion begins this time after the fall  
of ACK. This time are typical at room temperature and may  
vary with temperature.  
1.3 ADC TRANSFER FUNCTION  
The output format of the ADC081C021 is straight binary.  
Code transitions occur midway between successive integer  
LSB values. The LSB width for the ADC081C021 is VA / 256.  
The ideal transfer characteristic is shown in Figure 5. The  
transition from an output code of 0000 0000 0000 to a code  
of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA / 512.  
Other code transitions occur at intervals of 1 LSB.  
30052165  
FIGURE 2. ADC081C021 in Track Mode  
30052168  
30052166  
FIGURE 5. Ideal Transfer Characteristic  
FIGURE 3. ADC081C021 in Hold Mode  
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14  
 
 
 
 
1.4 REFERENCE VOLTAGE  
The ADC081C021 uses the supply (VA) as the reference, so  
VA must be treated as a reference. The analog-to-digital con-  
version will only be as precise as the reference (VA), so the  
supply voltage should be free of noise. The reference should  
be driven by a low output impedance voltage source.  
The Applications section provides recommended ways to pro-  
vide the supply voltage appropriately. Refer to Section 2.1  
TYPICAL APPLICATION CIRCUIT for details.  
1.5 POWER-ON RESET  
An internal power-on reset (POR) occurs when the supply  
voltage transitions above the power-on reset threshold. Each  
of the registers contains a defined value upon POR and this  
data remains there until any of the following occurs:  
•
The first conversion is completed, causing the Conversion  
Result and Status registers to be updated.  
•
•
A different data word is written to a writeable register.  
The ADC is powered down.  
The internal registers will lose their contents if the supply volt-  
age goes below 2.4V. Should this happen, it is important that  
the VA supply be lowered to a maximum of 200mV before the  
supply is raised again to properly reset the device and ensure  
that the ADC performs as specified.  
1.6 INTERNAL REGISTERS  
The ADC081C021 has 8 internal data registers and one ad-  
dress pointer. The registers provide additional ADC functions  
such as storing minimum and maximum conversion results,  
setting alert threshold levels, and storing data to configure the  
operation of the device. Figure 6 shows all of the registers and  
their corresponding address pointer values. All of the regis-  
ters are read/write capable except the conversion result reg-  
ister which is read-only.  
30052169  
FIGURE 6. Register Structure  
1.6.1 Address Pointer Register  
The address pointer determines which of the data registers is  
accessed by the I2C interface. The first data byte of every  
write operation is stored in the address pointer register. This  
value selects the register that the following data bytes will be  
written to or read from. Only the three LSBs of this register  
are variable. The other bits must always be written to as zeros.  
After a power-on reset, the pointer register defaults to all ze-  
ros (conversion result register).  
Default Value: 00h  
P7  
P6  
P5  
P4  
P3  
P2  
P1  
P0  
0
0
0
0
0
Register Select  
P2  
0
P1  
0
P0  
0
REGISTER  
Conversion Result (read only)  
Alert Status (read/write)  
0
0
1
0
1
0
Configuration (read/write)  
Low Limit (read/write)  
0
1
1
1
0
0
High Limit (read/write)  
1
0
1
Hysteresis (read/write)  
1
1
0
Lowest Conversion (read/write)  
Highest Conversion (read/write)  
1
1
1
15  
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1.6.2 Conversion Result Register  
This register holds the result of the most recent conversion. In the normal mode, a new conversion is started whenever this register  
is read. The conversion result data is in straight binary format with the MSB at D11.  
Pointer Address 00h (Read Only)  
Default Value: 0000h  
D15  
D14  
D13  
D12  
D4  
D11  
D3  
D10  
D9  
D8  
D0  
Alert Flag  
Reserved  
Conversion Result [7:4]  
D7  
D6  
D5  
D2  
D1  
Conversion Result [3:0]  
Reserved  
Bits  
Name  
Description  
15  
Alert Flag  
This bit indicates when an alert condition has occurred. When the Alert Bit Enable is set in the  
Configuration Register, this bit will be high if either alert flag is set in the Alert Status Register.  
Otherwise, this bit is a zero. The I2C controller will typically read the Alert Status register and  
other data registers to determine the source of the alert.  
14:12  
11:4  
Reserved  
Always reads zeros.  
Conversion Result  
The Analog-to-Digital conversion result. The Conversion result data is a 8-bit data word in straight  
binary format. The MSB is D11.  
3:0  
Reserved  
Always reads zeros.  
1.6.3 Alert Status Register  
This register indicates if a high or a low threshold has been violated. The bits of this register are active high. That is, a high indicates  
that the respective limit has been violated.  
Pointer Address 01h (Read/Write)  
Default Value: 00h  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Over Range Under Range  
Alert Alert  
D0  
Reserved  
Bits  
7:2  
1
Name  
Description  
Always reads zeros. Zeros must be written to these bits.  
Reserved  
Over Range  
Alert Flag  
Bit is set to 1 when the measured voltage exceeds the VHIGH limit stored in the programmable  
VHIGH limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The  
controller writes a one to this bit. (2) The measured voltage decreases below the programmed  
VHIGH limit minus the programmed VHYST value (See Figure 9) . The alert will only self-clear if the  
Alert Hold bit is cleared in the Configuration register. If the Alert Hold bit is set, the only way to  
clear an over range alert is to write a one to this bit.  
0
Under Range  
Alert Flag  
Bit is set to 1 when the measured voltage falls below the VLOW limit stored in the programmable  
VLOW limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The  
controller writes a one to this bit. (2) The measured voltage increases above the programmed  
VLOW limit plus the programmed VHYST value. The alert will only self-clear if the Alert Hold bit is  
cleared in the Configuration register. If the Alert Hold bit is set, the only way to clear an under  
range alert is to write a one to this bit.  
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16  
1.6.4 Configuration Register  
Pointer Address 02h (Read/Write)  
Default Value: 00h  
D7 D6 D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Tconvert x 32  
Tconvert x 64  
27  
13.5  
6.7  
3.4  
1.7  
0.9  
0.4  
Cycle Time [2:0] Alert  
Hold  
Alert  
Flag  
Enable Enable  
Alert  
Pin  
0
Polarity  
Tconvert x 128  
Tconvert x 256  
Tconvert x 512  
Tconvert x 1024  
Tconvert x 2048  
Cycle Time[2:0]  
Conversion  
Interval  
Typical  
fconvert  
(ksps)  
D7  
D6  
D5  
0
0
0
Mode Disabled  
0
Bits  
Name  
Description  
7:5  
Cycle Time  
Alert Hold  
Configures Automatic Conversion mode. When these bits are set to zeros, the automatic  
conversion mode is disabled. This is the case at power-up.  
When these bits are set to a non-zero value, the ADC will begin operating in automatic conversion  
mode. (See Section 1.9 AUTOMATIC CONVERSION MODE). The Cycle Time table shows how  
different values provide various conversion intervals.  
4
0: Alerts will self-clear when the measured voltage moves within the limits by more than the  
hysteresis register value.  
1: Alerts will not self-clear and are only cleared when a one is written to the alert high flag or the  
alert low flag in the Alert Status register.  
3
2
Alert Flag Enable  
Alert Pin Enable  
0: Disables alert status bit [D15] in the Conversion Result register.  
1: Enables alert status bit [D15] in the Conversion Result register.  
0: Disables the ALERT output pin. The ALERT output will TRI-STATE when the pin is disabled.  
1: Enables the ALERT output pin.  
*This bit does not apply to the ADC081C027.  
1
0
Reserved  
Polarity  
Always reads zeros. Zeros must be written to these bits.  
This bit configures the active level polarity of the ALERT output pin.  
0: Sets the ALERT pin to active low.  
1: Sets the ALERT pin to active high.  
*This bit does not apply to the ADC081C027.  
1.6.5 VLOW -- Alert Limit Register - Under Range  
This register holds the lower limit threshold used to determine the alert condition. If the conversion moves lower than this limit, a  
VLOW alert is generated.  
Pointer Address 03h (Read/Write)  
Default Value: 0000h  
D15  
D14  
D13  
D5  
D12  
D4  
D11  
D3  
D10  
D9  
D1  
D8  
D0  
Reserved  
VLOW Limit [7:4]  
D7  
D6  
D2  
VLOW Limit [3:0]  
Reserved  
Bits  
Name  
Description  
Always reads zeros. Zeros must be written to these bits.  
15:12  
11:4  
Reserved  
VLOW Limit  
Sets the lower limit threshold used to determine the alert condition. If the conversion moves lower  
than this limit, a VLOW alert is generated.  
3:0  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
17  
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1.6.6 VHIGH -- Alert Limit Register - Over Range  
This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher than this limit, a  
VHIGH alert is generated.  
Pointer Address 04h (Read/Write)  
Default Value: 0FFFh  
D15  
D14  
D13  
D5  
D12  
D4  
D11  
D3  
D10  
D9  
D1  
D8  
D0  
Reserved  
VHIGH Limit [7:4]  
D7  
D6  
D2  
VHIGH Limit [3:0]  
Reserved  
Bits  
Name  
Description  
Always reads zeros. Zeros must be written to these bits.  
15:12  
11:4  
Reserved  
VHIGH Limit  
Sets the upper limit threshold used to determine the alert condition. If the conversion moves  
higher than this limit, a VHIGH alert is generated.  
3:0  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
1.6.7 VHYST -- Alert Hysteresis Register  
This register holds the hysteresis value used to determine the alert condition. After a VHIGH or VLOW alert occurs, the conversion  
result must move within the VHIGH or VLOW limit by more than this value to clear the alert condition. Note: If the Alert Hold bit is set  
in the configuration register, alert conditions will not self-clear.  
Pointer Address 05h (Read/Write)  
Default Value: 0000h  
D15  
D14  
D13  
D5  
D12  
D4  
D11  
D3  
D10  
D9  
D1  
D8  
D0  
Reserved  
Hysteresis [7:4]  
D7  
D6  
D2  
Hysteresis [3:0]  
Reserved  
Bits  
Name  
Description  
15:12  
11:4  
3:0  
Reserved  
Hysteresis  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
Hysteresis value. D11 is MSB.  
Always reads zeros. Zeros must be written to these bits.  
1.6.8 VMIN -- Lowest Conversion Register  
This register holds the Lowest Conversion result when in the automatic conversion mode. Each conversion result is compared  
against the contents of this register. If the value is lower, it becomes the lowest conversion and replaces the current value. If the  
value is higher, the register contents remain unchanged. The lowest conversion value can be cleared at any time by writing 0FFFh  
to this register. The value of this register will update automatically when the automatic conversion mode is enabled, but is NOT  
updated in the normal mode.  
Pointer Address 06h (Read/Write)  
Default Value: 0FFFh  
D15  
D14  
D13  
D5  
D12  
D4  
D11  
D3  
D10  
D9  
D8  
D0  
Reserved  
Lowest Conversion [7:4]  
D7  
D6  
D2  
D1  
Lowest Conversion [3:0]  
Reserved  
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18  
Bits  
15:12  
11:4  
3:0  
Name  
Description  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
Lowest conversion result data. D11 is MSB.  
Always reads zeros. Zeros must be written to these bits.  
Lowest Conversion  
Reserved  
1.6.9 VMAX -- Highest Conversion Register  
This register holds the Highest Conversion result when in the Automatic mode. Each conversion result is compared against the  
contents of this register. If the value is higher, it replaces the previous value. If the value is lower, the register contents remain  
unchanged. The highest conversion value can be cleared at any time by writing 0000h to this register. The value of this register  
will update automatically when the automatic conversion mode is enabled, but is NOT updated in the normal mode.  
Pointer Address 07h (Read/Write)  
Default Value: 0000h  
D15  
D14  
D13  
D5  
D12  
D4  
D11  
D3  
D10  
D9  
D8  
D0  
Reserved  
Highest Conversion [7:4]  
D7  
D6  
D2  
D1  
Highest Conversion [3:0]  
Reserved  
Bits  
Name  
Description  
15:12  
11:4  
3:0  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
Highest conversion result data. D11 is MSB.  
Highest Conversion  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
1.7 SERIAL INTERFACE  
driving the SDA bus low. If the address doesn't match a  
device's slave address, it not-acknowledges (NACKs) the  
master by letting SDA be pulled high. ACKs also occur on the  
bus when data is being transmitted. When the master is writ-  
ing data, the slave ACKs after every data byte is successfully  
received. When the master is reading data, the master ACKs  
after every data byte is received to let the slave know it wants  
to receive another data byte. When the master wants to stop  
reading, it NACKs after the last data byte and creates a stop  
condition on the bus.  
The I2C-compatible interface operates in all three speed  
modes. Standard mode (100kHz) and Fast mode (400kHz)  
are functionally the same and will be referred to as Standard-  
Fast mode in this document. High-Speed mode (3.4MHz) is  
an extension of Standard-Fast mode and will be referred to  
as Hs-mode in this document.  
The following diagrams describe the timing relationships of  
the clock (SCL) and data (SDA) signals. Pull-up resistors or  
current sources are required on the SCL and SDA busses to  
pull them high when they are not being driven low. A logic zero  
is transmitted by driving the output low. A logic high is trans-  
mitted by releasing the output and allowing it to be pulled-up  
externally. The appropriate pull-up resistor values will depend  
upon the total bus capacitance and operating speed. The AD-  
C081C021 offers extended ESD tolerance (8kV HBM) for the  
I2C bus pins (SCL & SDA) allowing extension of the bus  
across multiple boards without extra ESD protection.  
All communication on the bus begins with either a Start con-  
dition or a Repeated Start condition. The protocol for starting  
the bus varies between Standard-Fast mode and Hs-mode.  
In Standard-Fast mode, the master generates  
a
Start condition by driving SDA from high to low while SCL is  
high. In Hs-mode, starting the bus is more complicated.  
Please refer to Section 1.7.3 High-Speed (Hs) Mode for the  
full details of a Hs-mode Start condition.  
A Repeated Start is generated to address a different device  
or register, or to switch between read and write modes. The  
master generates a Repeated Start condition by driving SDA  
low while SCL is high. Following the Repeated Start, the mas-  
ter sends out the slave address and a read/write bit as shown  
in Figure 7. The bus continues to operate in the same speed  
mode as before the Repeated Start condition.  
1.7.1 Basic I2C Protocol  
The I2C interface is bi-directional and allows multiple devices  
to operate on the same bus. The bus consists of master de-  
vices and slave devices which can communicate back and  
forth over the I2C interface. Master devices control the bus  
and are typically microcontrollers, FPGAs, DSPs, or other  
digital controllers. Slave devices are controlled by a master  
and are typically peripheral devices such as the  
ADC081C021. To support multiple devices on the same bus,  
each slave has a unique hardware address which is referred  
to as the "slave address." To communicate with a particular  
device on the bus, the controller (master) sends the slave ad-  
dress and listens for a response from the slave. This response  
is referred to as an acknowledge bit. If a slave on the bus is  
addressed correctly, it acknowledges (ACKs) the master by  
All communication on the bus ends with a Stop condition. In  
either Standard-Fast mode or Hs-Mode, a Stop condition oc-  
curs when SDA is pulled high while SCL is high. After a Stop  
condition, the bus remains idle until a master generates an-  
other Start condition.  
Please refer to the Philips I2C® Specification (Version 2.1  
Jan, 2000) for a detailed description of the serial interface.  
19  
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30052111  
FIGURE 7. Basic Operation.  
1.7.2 Standard-Fast Mode  
er before reading from the desired register. This type of read  
requires a start, the slave address, a write bit, the address  
pointer, a Repeated Start (if appropriate), the slave address,  
and a read bit (refer to Figure 12). Following this sequence,  
the ADC sends out the upper 8-bits of the register. For a single  
byte read operation, the Master must then send a NACK to  
the ADC and generate a Stop condition to end communica-  
tion. For a 2-Byte write operation, the Master sends an ACK  
to the ADC. Then, the ADC sends out the lower 8-bits of the  
ADC register. At this point, the master sends either an ACK  
to receive more data, or a NACK followed by a Stop or Re-  
peated Start. If the master sends an ACK, the ADC sends  
another pair of data bytes, and the read cycle will repeat. The  
number of data words that can be read is unlimited.  
In Standard-Fast mode, the master generates a start condi-  
tion by driving SDA from high to low while SCL is high. The  
start condition is always followed by a 7-bit slave address and  
a Read/Write bit. After these 8 bits have been transmitted by  
the master, SDA is released by the master and the  
ADC081C021 either ACKs or NACKs the address. If the slave  
address matches, the ADC081C021 ACKs the master. If the  
address doesn't match, the ADC081C021 NACKs the master.  
For a write operation, the master follows the ACK by sending  
the 8-bit register address pointer to the ADC. Then the  
ADC081C021 ACKs the transfer by driving SDA low. Next,  
the master sends the upper 8-bits to the ADC081C021. Then  
the ADC081C021 ACKs the transfer by driving SDA low. For  
a single byte transfer, the master should generate a stop con-  
dition at this point. For a 2-byte write operation, the lower 8-  
bits are sent by the master. The ADC081C021 then ACKs the  
transfer, and the master either sends another pair of data  
bytes, generates a Repeated Start condition to read or write  
another register, or generates a Stop condition to end com-  
munication.  
1.7.3 High-Speed (Hs) Mode  
For Hs-mode, the sequence of events to begin communica-  
tion differs slightly from Standard-Fast mode. Figure 8 de-  
scribes this in further detail. Initially, the bus begins running  
in Standard-Fast mode. The master generates  
a
Start condition and sends the 8-bit Hs master code  
(00001XXX) to the ADC081C021. Next, the ADC081C021  
responds with a NACK. Once the SCL line has been pulled to  
a high level, the master switches to Hs-mode by increasing  
the bus speed and generating a second Repeated Start con-  
dition (driving SDA low while SCL is pulled high). At this point,  
the master sends the slave address to the ADC081C021, and  
communication continues as shown above in the "Basic Op-  
eration" Diagram (see Figure 7).  
A read operation can take place either of two ways:  
If the address pointer is pre-set before the read operation, the  
desired register can be read immediately following the slave  
address. In this case, the upper 8-bits of the register, set by  
the pre-set address pointer, are sent out by the ADC. For a  
single byte read operation, the Master sends a NACK to the  
ADC and generates a Stop condition to end communication  
after receiving 8-bits of data. For a 2-Byte read operation, the  
Master continues the transmission by sending an ACK to the  
ADC. Then, the ADC sends out the lower 8-bits of the ADC  
register. At this point, the master either sends; an ACK to re-  
ceive more data or, a NACK followed by a Stop or Repeated  
Start. If the master sends an ACK, the ADC sends the next  
upper data byte, and the read cycle repeats.  
When the master generates a Repeated Start condition while  
in Hs-mode, the bus stays in Hs-mode awaiting the slave ad-  
dress from the master. The bus continues to run in Hs-mode  
until a Stop condition is generated by the master. When the  
master generates a Stop condition on the bus, the bus must  
be started in Standard-Fast mode again before increasing the  
bus speed and switching to Hs-mode.  
If the ADC081S021 address pointer needs to be set, the  
master needs to write to the device and set the address point-  
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20  
 
 
30052112  
FIGURE 8. Beginning Hs-Mode Communication  
1.7.4 I2C Slave (Hardware) Address  
The ADC has a seven-bit hardware address which is also referred to as a slave address. For the MSOP-8 version of the AD-  
C081C021, this address is configured by the ADR0 and ADR1 addres selection inputs. For the ADC081C027, the address is  
configured by the ADR0 address selection input. ADR0 and ADR1 can be grounded, left floating, or tied to VA. If desired, ADR0  
can be set to VA/2 rather than left floating. The state of these inputs sets the hardware address that the ADC responds to on the  
I2C bus (see Table 1). For the TSOT-6 version of the ADC081C021, the hardware address is not pin-configurable and is set to  
1010100. The diagrams in Section 1.10 COMMUNICATING WITH THE ADC081C021 describe how the I2C controller should  
address the ADC via the I2C interface.  
Pin compatible alternatives that provide additional address options to the TSOT-6 version of the ADC081C021 and the AD-  
C081C027 are available.  
TABLE 1. Slave Addresses  
ADC081C027  
ADC081C021  
ADC081C021  
(TSOT-6)  
(TSOT-6)  
(MSOP-8)  
Slave Address  
[A6 - A0]  
ADR0  
Floating  
ALERT  
ADR1  
ADR0  
Floating  
GND  
VA  
1010000  
1010001  
1010010  
1010100  
1010101  
1010110  
1011000  
1011001  
1011010  
-----------------  
-----------------  
-----------------  
Single Address  
-----------------  
-----------------  
-----------------  
-----------------  
-----------------  
Floating  
Floating  
Floating  
GND  
GND  
GND  
VA  
GND  
VA  
-----------------  
-----------------  
-----------------  
-----------------  
-----------------  
-----------------  
Floating  
GND  
VA  
Floating  
GND  
VA  
VA  
VA  
1.8 ALERT FUNCTION  
can be configured as an active high or active low output via  
the Polarity bit in the Configuration register. If the Polarity bit  
is cleared, the ALERT output is configured as active low. If  
the Polarity bit is set, the ALERT output is configured as active  
high.  
The ALERT function is an "out-of-range" indicator. At the end  
of every conversion, the measured voltage is compared to the  
values in the VHIGH and VLOW registers. If the measured volt-  
age exceeds the value stored in VHIGH or falls below the value  
stored in VLOW, an alert condition occurs. The Alert condition  
is indicated in up to three places. First, the alert condition al-  
ways causes either or both of the alert flags in the Alert Status  
register to go high. If the measured voltage exceeds the  
VHIGH limit, the Over Range Alert Flag is set. If the measured  
voltage falls below the VLOW limit, the Under Range Alert Flag  
is set. Second, if the Alert Flag Enable bit is set in the Con-  
figuration register, the alert condition also sets the MSB of the  
Conversion Result register. Third, if the Alert Pin Enable bit is  
set in the Configuration register, the ALERT output becomes  
active (see Figure 9). The ALERT output (ADC081S021 only)  
The Over Range Alert condition is cleared when one of the  
following two conditions is met:  
1. The controller writes a one to the Over Range Alert Flag  
bit.  
2. The measured voltage goes below the programmed  
VHIGH limit minus the programmed VHYST value and the  
Alert Hold bit is cleared in the Configuration register. (see  
Figure 9). If the Alert Hold bit is set, the alert condition  
persists and only clears when a one is written to the Over  
Range Alert Flag bit.  
21  
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The Under Range Alert condition is cleared when one of the  
following two conditions is met:  
1.9 AUTOMATIC CONVERSION MODE  
The automatic conversion mode configures the ADC to con-  
tinually perform conversions without receiving "read" instruc-  
tions from the controller over the I2C interface. The mode is  
activated by writing a non-zero value into the Cycle Time bits  
- D[7:5] - of the Configuration register (see Section 1.6.4 Con-  
figuration Register). Once the ADC081C021 enters this  
mode, the internal oscillator is always enabled. The ADC's  
control logic samples the input at the sample rate set by the  
cycle time bits. Although the conversion result is not trans-  
mitted by the 2-wire interface, it is stored in the conversion  
result register and updates the various status registers of the  
device.  
1. The controller writes a one to the Under Range Alert Flag  
bit.  
2. The measured voltage goes above the programmed  
VLOW limit plus the programmed VHYST value and the  
Alert Hold bit is cleared in the Configuration register. If  
the Alert Hold bit is set, the alert condition persists and  
only clears when a one is written to the Under Range  
Alert Flag bit.  
If the alert condition has been cleared by writing a one to the  
alert flag while the measured voltage still violates the VHIGH  
or VLOW limits, an alert condition will occur again after the  
completion of the next conversion (see Figure 10).  
In automatic conversion mode, the out-of-range alert function  
is active and updates after every conversion. The ADC can  
operate independently of the controller in automatic conver-  
sion mode. When the input signal goes "out-of-range", an  
alert signal is sent to the controller. The controller can then  
read the status registers and determine the source of the alert  
condition. Also, comparison and updating of the VMIN and  
VMAX registers occurs after every conversion in automatic  
conversion mode. The controller can occasionally read the  
VMIN and/or VMAX registers to determine the sampled input  
extremes. These register values persist until the user resets  
the VMIN and VMAX registers. These two features are useful in  
system monitoring, peak detection, and sensing applications.  
Alert conditions only occur if the input voltage exceeds the  
VHIGH limit or falls below the VLOW limit at the sample-hold  
instant. The input voltage can exceed the VHIGH limit or fall  
below the VLOW limit briefly between conversions without  
causing an alert condition.  
30052174  
FIGURE 9. Alert condition cleared when measured  
voltage crosses VHIGH - VHYST  
30052175  
FIGURE 10. Alert condition cleared by writing a "1" to the  
Alert Flag.  
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22  
 
 
 
1.10 COMMUNICATING WITH THE ADC081C021  
updated for a read cycle, a write operation must precede the  
read operation to set the pointer address correctly. On the  
other hand, if the pointer is preset correctly, a read operation  
can occur without writing the address pointer register. The  
following timing diagrams describe the various read and write  
operations supported by the ADC.  
The ADC081C021's data registers are selected by the ad-  
dress pointer (see Section 1.6.1 Address Pointer Register).  
To read/write a specific data register, the pointer must be set  
to that register's address. The pointer is always written at the  
beginning of a write operation. When the pointer needs to be  
1.10.1 Reading from a 2-Byte ADC Register  
The following diagrams indicate the sequence of actions re-  
quired for a 2-Byte read from an ADC081C021 Register.  
30052163  
FIGURE 11. (a) Typical Read from a 2-Byte ADC Register with Preset Pointer  
30052170  
FIGURE 12. (b) Typical Pointer Set Followed by Immediate Read of a 2-Byte ADC Register  
23  
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1.10.2 Reading from a 1-Byte ADC Register  
The following diagrams indicate the sequence of actions re-  
quired for a single Byte read from an ADC081C021 Register.  
30052171  
FIGURE 13. (a) Typical Read from a 1-Byte ADC Register with Preset Pointer  
30052172  
FIGURE 14. (b) Typical Pointer Set Followed by Immediate Read of a 1-Byte ADC Register  
1.10.3 Writing to an ADC Register  
The following diagrams indicate the sequence of actions re-  
quired for writing to an ADC081C021 Register.  
30052164  
FIGURE 15. (a) Typical Write to a 1-Byte ADC Register  
ꢀ
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24  
30052173  
FIGURE 16. (b) Typical Write to a 2-Byte ADC Register  
1.11 QUIET INTERFACE MODE  
at least 1µs before the MSB of every upper data byte. The  
diagram assumes that the address pointer register is set to  
its default value.  
To improve performance at High Speed, operate the ADC in  
Quiet Interface Mode. This mode provides improved INL and  
DNL performance in I2C Hs-Mode (3.4MHz). The Quiet Inter-  
face mode provides a maximum throughput rate of 162ksps.  
Figure 17 describes how to read the conversion result register  
in this mode. Basically, the Master needs to release SCL for  
Quiet Interface mode will only improve INL and DNL perfor-  
mance in Hs-Mode. Standard and Fast mode performance is  
unaffected by the Quiet Interface mode.  
30052176  
FIGURE 17. Reading in Quiet Interface Mode  
25  
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If the controller's supply is noisy, an appropriate bypass ca-  
pacitor should be added between the controller's supply pin  
and the pull-up resistors. For Hs-mode applications, this by-  
pass capacitance will improve the accuracy of the ADC.  
2.0 Applications Information  
2.1 TYPICAL APPLICATION CIRCUIT  
A typical application circuit is shown in Figure 18. The analog  
supply is bypassed with a capacitor network located close to  
the ADC081C021. The ADC uses the analog supply (VA) as  
its reference voltage, so it is very important that VA be kept as  
clean as possible. Due to the low power requirements of the  
ADC081C021, it is possible to use a precision reference as a  
power supply.  
The value of the pull-up resistors (RP) depends upon the  
characteristics of each particular I2C bus. The I2C specifica-  
tion describes how to choose an appropriate value. As a  
general rule-of-thumb, we suggest using a 1kΩ resistor for  
Hs-mode bus configurations and a 5kΩ resistor for Standard  
or Fast Mode bus configurations. Depending upon the bus  
capacitance, these values may or may not be sufficient to  
meet the timing requirements of the I2C bus specification.  
Please see the I2C specification for further information.  
The bus pull-up resistors (RP) should be powered by the  
controller's supply. It is important that the pull-up resistors are  
pulled to the same voltage potential as VA. This will ensure  
that the logic levels of all devices on the bus are compatible.  
30052120  
FIGURE 18. Typical Application Circuit  
2.2 BUFFERED INPUT  
input must have a DC bias level that keeps the ADC input  
signal from swinging below GND or above the supply (+5V in  
this case).  
A buffered input application circuit is shown in Figure 19. The  
analog input is buffered by a National Semiconductor  
LMP7731. The non-inverting amplifier configuration provides  
a buffered gain stage for a single ended source. This appli-  
cation circuit is good for single-ended sensor interface. The  
The LM4132, with its 0.05% accuracy over temperature, is an  
excellent choice as a reference source for the ADC081C021.  
30052121  
FIGURE 19. Buffered Input Circuit  
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26  
 
 
 
2.3 INTELLIGENT BATTERY MONITOR  
The accurate voltage reading and the alert feature will allow  
a controller to improve the efficiency of a battery-powered  
device. During the discharge cycle, the controller can switch  
to a low-battery mode, safely suspend operation, or report a  
precise battery level to the user. During the recharge cycle,  
the controller can implement an intelligent recharge cycle,  
decreasing the charge rate when the battery charge nears  
capacity.  
The ADC081C021 is easily used as an intelligent battery  
monitor. The simple circuit shown in Figure 20, uses the  
ADC081C021, the LP2980 fixed reference, and a resistor di-  
vider to implement an intelligent battery monitor with a window  
supervisory feature. The window supervisory feature is im-  
plemented by the "out of range" alert function. When the  
battery is recharging, the Over Range Alert will indicate that  
the charging cycle is complete (see Figure 21). When the  
battery is nearing depletion, the Under Range Alert will indi-  
cate that the battery is low (see Figure 22).  
2.3.1 Trickle Charge Controller  
While a battery is discharging, the ADC081C021 can be used  
to control a trickle charge to keep the battery near full capacity  
(see Figure 23). When the alert output is active, the battery  
will recharge. An intelligent recharge cycle will prevent over-  
charging and damaging the battery. With a trickle charge, the  
battery powered device can be disconnected from the charger  
at any time with a full charge.  
30052177  
FIGURE 20. Intelligent Battery Monitor Circuit  
30052180  
FIGURE 23. Trickle Charge  
2.4 LAYOUT, GROUNDING, AND BYPASSING  
For best accuracy and minimum noise, the printed circuit  
board containing the ADC081C021 should have separate  
analog and digital areas. The areas are defined by the loca-  
tions of the analog and digital power planes. Both of these  
planes should be located on the same board layer. A single,  
solid ground plane is preferred if digital return current does  
not flow through the analog ground area. Frequently a single  
ground plane design will utilize a "fencing" technique to pre-  
vent the mixing of analog and digital ground currents. Sepa-  
rate ground planes should only be utilized when the fencing  
technique is inadequate. The separate ground planes must  
be connected in one place, preferably near the ADC121C021.  
Special care is required to guarantee that signals do not pass  
over power plane boundaries. Return currents must always  
have a continuous return path below their traces.  
30052178  
FIGURE 21. Recharge Cycle  
The ADC081C021 power supply should be bypassed with a  
4.7µF and a 0.1µF capacitor as close as possible to the device  
with the 0.1µF right at the device supply pin. The 4.7µF ca-  
pacitor should be a tantalum type and the 0.1µF capacitor  
should be a low ESL type. The power supply for the  
ADC081C021 should only be used for analog circuits.  
30052179  
Avoid crossover of analog and digital signals and keep the  
clock and data lines on the component side of the board. The  
clock and data lines should have controlled impedances.  
FIGURE 22. Discharge Cycle  
In addition to the window supervisory feature, the  
ADC081C021 will allow the controller to read the battery volt-  
age at any time during operation.  
27  
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Physical Dimensions inches (millimeters) unless otherwise noted  
6-Lead TSOT  
Order Numbers ADC081C021CIMK & ADC081C027CIMK  
NS Package Number MK06A  
8-Lead MSOP  
Order Numbers ADC081C021CIMM  
NS Package Number MUA08A  
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28  
Notes  
29  
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