BUK9MNN-65PKK--Datasheet/数据表在线中文翻译

BUK9MNN-65PKK

Dual TrenchPLUS FET Logic Level FET

Rev. 03 — 15 July 2010

Product data sheet

1. Product profile

1.1 General description

Dual N-channel enhancement mode field-effect power transistor in SO20. Device is

manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring

very low on-state resistance, integrated current sensing transistors and over temperature

protection diodes.

1.2 Features and benefits

Integrated current sensors

Integrated temperature sensors

1.3 Applications

Lamp switching

Power distribution

Solenoid drivers

Motor drive systems

1.4 Quick reference data

Table 1.

Symbol

Quick reference data

Parameter

Conditions

Min Typ Max Unit

FET1 and FET2 static characteristics

R_DSon

drain-source on-state V_GS= 5 V; I_D= 5 A; T_j= 25 °C;

resistance see Figure 16; see Figure 17

-

30.6 36

2242 2491 2740 A/A

65

mΩ

I_D/I_sense

V_(BR)DSS

ratio of drain current to T_j= 25 °C; V_GS= 5 V;

sense current

see Figure 18

drain-source

breakdown voltage

I_D= 250 µA; V_GS= 0 V;

T_j= 25 °C

-

V

BUK9MNN-65PKK

NXP Semiconductors

Dual TrenchPLUS FET Logic Level FET

2. Pinning information

Table 2.

1

Pinning information

Symbol Description

Simplified outline

Graphic symbol

G1

IS1

D1

A1

gate 1

20

11

10

D1

A1

D2

A2

2

current sense 1

drain

3

FET1

FET2

4

anode 1

5

C1

G2

IS2

D2

A2

cathode 1

gate 2

6

1

7

current sense 2

drain 2

SOT163-1 (SO20)

G1

IS1 S1 KS1 C1 G2

IS2 S2 KS2 C2

8

003aaa745

9

anode 2

10

11

12

13

14

15

16

17

18

19

20

C2

D2

KS2

S2

cathode 2

drain 2

Kelvin source 2

source 2

drain 2

S2

D2

D1

KS1

S1

drain 1

Kelvin source 1

source 1

drain 1

S1

D1

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

Version

BUK9MNN-65PKK

SO20

plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

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4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

FET1 and FET2

V_DS

V_DGR

V_GS

I_D

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

25 °C ≤ T_j≤ 150 °C

-

65

V

A

R_GS= 20 kΩ; 25 °C ≤ T_j≤ 150 °C

-

65

-15

15

[1]

V_GS= 5 V; T_sp= 25 °C; see Figure 1

V_GS= 5 V; T_sp= 100 °C; see Figure 1

-

7.1

4.5

96.6

[2][1]

I_DM

peak drain current

T_sp= 25 °C; single pulse; t_p≤ 10 µs;

see Figure 4

P_tot

total power dissipation

storage temperature

junction temperature

T_sp= 25 °C; see Figure 2

-

3.57

150

100

W

°C

V

T_stg

-55

-

T_j

V_{isol(FET-TSD)}

FET to temperature sense

diode isolation voltage

FET1 and FET2 source-drain diode

[2][1]

I_S

source current

T_sp= 25 °C

-

5

A

I_SM

peak source current

single pulse; t_p≤ 10 µs; T_sp= 25 °C

96.6

FET1 and FET2 avalanche ruggedness

[3][4][5]

E_DS(AL)S

non-repetitive drain-source

avalanche energy

I_D= 7.1 A; V_sup= 65 V; V_GS= 5 V;

T_j(init)= 25 °C; unclamped; see Figure 3

-

165

mJ

FET1 and FET2 electrostatic discharge

V_ESD

electrostatic discharge voltage HBM; C = 100 pF; R = 1.5 kΩ; all pins

-

0.15

4

kV

HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11

and 15 to pins 6, 7, 12, 13 and 14

shorted

HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16

and 20 to pins 1, 2, 17, 18 and 19

shorted

-

4

kV

[1] Current is limited by package.

[2] Single device conducting.

[3] Single-pulse avalanche rating limited by maximum junction temperature of 150 °C.

[4] Repetitive rating defined in avalanche rating figure.

[5] Refer to application note AN10273 for further information.

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Dual TrenchPLUS FET Logic Level FET

001aal886

003aab388

8

120

I

D

P_der

(%)

(A)

6

4

2

0

80

40

0

50

100

150

200

0

50

100

150

200

T_sp(°C)

T

sp

(°C)

Fig 1. Continuous drain current as a function of

solder point temperature, FET1 and FET2

Fig 2. Normalized total power dissipation as a

function of solder point temperature, FET1 and

FET2

001aal682

10

(1)

I

AL

(A)

(2)

(3)

1

−1

10

−2

10

−3

−2

−1

10

1

10

t

AL

(ms)

Fig 3. Single-Pulse and repetitive avalanche rating; avalanche current as a function of avalanche time.

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Dual TrenchPLUS FET Logic Level FET

001aal757

3

10

I

D

(A)

2

Limit R

= V / I

DS

10

DSon

D

t

p

= 10 μs

100 μs

10

1 ms

1

DC

10 ms

100 ms

−1

10

−2

10

−1

2

1

10

V

DS

(V)

Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

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5. Thermal characteristics

Table 5.

Symbol

R_th(j-sp)

Thermal characteristics

Parameter

Conditions

FET1

Min

Typ

Max

35

-

Unit

K/W

thermal resistance from

junction to solder point

-

FET2

-

R_th(j-a)

thermal resistance from

junction to ambient

mounted on a printed-circuit board; both

channels conducting; zero heat sink area;

see Figure 5; see Figure 6

73

mounted on a printed-circuit board; both

channels conducting; 200 mm² copper

heat sink area; see Figure 7; see Figure 6

-

60

51

105

90

70

-

K/W

mounted on a printed-circuit board; both

channels conducting; 400 mm² copper

heat sink area; see Figure 8; see Figure 6

mounted on a printed-circuit board; one

channel conducting; zero heat sink area;

see Figure 5; see Figure 6

mounted on a printed-circuit board; one

channel conducting; 200 mm² copper heat

sink area; see Figure 7; see Figure 6

mounted on a printed-circuit board; one

channel conducting; 400 mm² copper heat

sink area; see Figure 8; see Figure 6

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Dual TrenchPLUS FET Logic Level FET

003aac472

120

R_th(j-a)

(K/W)

(1)

(2)

80

001aae478

40

0

100

200

300

400

A (mm²)

Fig 5. PCB used for thermal tests; zero heat sink area Fig 6. Thermal resistance from junction to ambient as

a function of printed-circuit board (PCB) heat

sink area

001aae479

001aae480

Fig 7. PCB used for thermal tests; heat sink area

200 mm²

Fig 8. PCB used for thermal tests; heat sink area

400 mm²

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Dual TrenchPLUS FET Logic Level FET

001aal807

2

10

Z

th(j-a)

δ = 0.5

(K/W)

0.2

0.1

10

0.05

0.02

1

t

p

P

δ =

T

−1

10

t

p

single shot

T

−2

10

−6

−5

−4

−3

−2

−1

2

3

4

10

1

10

t

(s)

p

Fig 9. Transient thermal impedance from junction to ambient as a function of pulse duration, FET1 and FET2

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6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

FET1 and FET2 static characteristics

V_(BR)DSS

drain-source breakdown voltage I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

65

59

1

-

V

-

V_GSth

gate-source threshold voltage

I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

see Figure 14; see Figure 15

1.5

2

I_D= 1 mA; V_DS= V_GS; T_j= 150 °C;

see Figure 14; see Figure 15

0.5

-

V

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

see Figure 14; see Figure 15

2.3

I_DSS

drain leakage current

gate leakage current

V_DS= 52 V; V_GS= 0 V; T_j= 25 °C

V_DS= 52 V; V_GS= 0 V; T_j= 150 °C

V_DS= 0 V; V_GS= 15 V; T_j= 25 °C

-

0.02

3

µA

nA

mΩ

-

125

300

39.8

I_GSS

2

-

R_DSon

drain-source on-state resistance V_GS= 4.5 V; I_D= 5 A; T_j= 25 °C;

see Figure 16; see Figure 17

V_GS= 5 V; I_D= 5 A; T_j= 25 °C;

see Figure 16; see Figure 17

-

30.6

36

mΩ

V_GS= 5 V; I_D= 5 A; T_j= 150 °C;

-

70.8

32.8

see Figure 16; see Figure 17

V_GS= 10 V; I_D= 5 A; T_j= 25 °C;

see Figure 16; see Figure 17

I_D/I_sense

S_F(TSD)

V_F(TSD)

ratio of drain current to sense

current

V_GS= 5 V; T_j= 25 °C; see Figure 18

2242 2491 2740 A/A

temperature sense diode

temperature coefficient

I_F= 250 µA; 25 °C ≤ T_j≤ 150 °C;

see Figure 19

-5.4

-5.7

-6

mV/K

V

temperature sense diode

forward voltage

I_F= 250 µA; T_j= 25 °C;

see Figure 19

2.855 2.9

2.945

FET1 and FET2 dynamic characteristics

Q_G(tot)

Q_GS

Q_GD

C_iss

C_oss

C_rss

t_d(on)

t_r

total gate charge

I_D= 5 A; V_DS= 52 V; V_GS= 5 V;

see Figure 20

-

15

-

nC

pF

ns

gate-source charge

gate-drain charge

input capacitance

output capacitance

reverse transfer capacitance

turn-on delay time

rise time

3.9

5.9

1180

169

56

V_GS= 0 V; V_DS= 25 V; f = 1 MHz;

T_j= 25 °C; see Figure 21

V_DS= 30 V; R_L= 6 Ω; V_GS= 5 V;

R_G(ext)= 10 Ω

20

25

ns

t_d(off)

t_f

turn-off delay time

fall time

86

ns

50

ns

L_D

internal drain inductance

internal source inductance

from pin to center of die

0.9

2

nH

L_S

from source lead to source bonding

pad

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Dual TrenchPLUS FET Logic Level FET

Table 6.

Symbol

Characteristics …continued

Parameter

Conditions

Min

Typ

Max

Unit

FET1 and FET2 source-drain diode

V_SD

source-drain voltage

I_S= 5 A; V_GS= 0 V; T_j= 25 °C;

see Figure 22

-

0.85

1.2

V

t_rr

reverse recovery time

recovered charge

I_S= 5 A; dI_S/dt = -100 A/µs;

V_GS= -10 V; V_DS= 30 V

-

39

-

ns

Q_r

0.073

nC

001aal884

001aal994

100

80

10.0

5.0

4.5

R

DSon

(mΩ)

I

D

(A)

80

60

4.0

3.5

60

40

20

0

40

20

0

3.0

V

GS

(V) = 2.5 V

0

2

4

6

8

10

(V)

0

2

4

6

8

10

(V)

V

GS

V

DS

Fig 10. Drain-source on-state resistance as a function

of gate-source voltage; typical values.

Fig 11. Output characteristics: drain current as a

function of drain-source voltage; typical values.

001aal995

003aae495

50

I

D

g

fs

(A)

(S)

40

30

20

10

0

30

20

10

0

T = 150 °C

25 °C

j

0

1

2

3

4

5

0

10

20

30

40

50

V

GS

(V)

I (A)

D

Fig 12. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

Fig 13. Forward transconductance as a function of

drain current; typical values.

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Dual TrenchPLUS FET Logic Level FET

001aam030

001aam029

−1

10

2.5

I

V

GS(th)

(V)

D

(A)

−2

10

2.0

1.5

1.0

0.5

0

max

min

typ

max

−3

10

typ

−4

min

10

−5

10

−6

10

0

1

2

3

−60

0

60

120

180

V

(V)

T (°C)

j

GS

Fig 14. Sub-threshold drain current as a function of

gate-source voltage.

Fig 15. Gate-source threshold voltage as a function of

junction temperature.

003aad928

003aad933

2

2.0

2.5

3.5

4.0 4.5

R_DSon

(m

5.0

a

)

W

140

1.5

100

60

1

0.5

0

V

_GS(V) =10 V

20

-60

0

60

120

180

0

20

40

60

80

T_j( C)

I_D(A)

Fig 16. Normalized Drain-source on-state resistance

factor as a function of junction temperature.

Fig 17. Drain-source on-state resistance as a function

of drain current; typical values, FET1 and FET2

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Dual TrenchPLUS FET Logic Level FET

003aad929

003aad930

4000

4

v_F

(TSD)

I_D/I_sense

3000

2000

1000

0

3

2

1

2

4

6

8

10

0

50

100

150

V_GS(V)

T_j( C)

Fig 18. Ratio of drain current to sense current as a

function of gate-source voltage; typical values,

FET1 and FET2

Fig 19. Temperature sense diode forward voltage as a

function of junction temperature; typical

values, FET1 and FET2

003aad932

001aam019

10⁴

5

V

(V)

GS

C

(pF)

4

3

2

1

0

C_{is s}

10³

V

= 14 V

V

= 52 V

DS

C_oss

10²

C_{rs s}

10

0

4

8

12

16

10^-1

1

10

10²

V_DS(V)

Q

G

(nC)

Fig 20. Gate-source as a function of turn-on gate

charge; typical values, FET1 and FET2

Fig 21. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values.

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Dual TrenchPLUS FET Logic Level FET

001aal885

50

I

S

(A)

40

30

20

10

0

T = 150 °C

T = 25 °C

j

0

0.4

0.8

1.2

1.6

(V)

V

SD

Fig 22. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.

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Dual TrenchPLUS FET Logic Level FET

7. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25

0.01

0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 23. Package outline SOT163-1 (SO20)

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8. Revision history

Table 7.

Document ID

BUK9MNN-65PKK v.3 20100715

Revision history

Release date

Data sheet status

Change notice

Supersedes

Product data sheet

-

BUK9MNN-65PKK v.2

Modifications:

• Various changes to content.

BUK9MNN-65PKK v.2 20100616

BUK9MNN-65PKK v.1 20100527

Product data sheet

-

BUK9MNN-65PKK v.1

-

Objective data sheet

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9. Legal information

9.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

9.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

suitable for use in medical, military, aircraft, space or life support equipment,

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application/use or the application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Application planned. Customer has to do all necessary

testing for the Application in order to avoid a default of the Application and the

product. NXP Semiconductors does not accept any liability in this respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in the

Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

9.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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All information provided in this document is subject to legal disclaimers.

Product data sheet

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Dual TrenchPLUS FET Logic Level FET

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,

FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,

ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,

QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,

TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

9.4 Trademarks

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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All information provided in this document is subject to legal disclaimers.

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Rev. 03 — 15 July 2010

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11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3

Thermal characteristics . . . . . . . . . . . . . . . . . . .6

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .9

Package outline . . . . . . . . . . . . . . . . . . . . . . . . .14

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .15

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .16

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .16

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .17

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .17

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 July 2010

Document identifier: BUK9MNN-65PKK