A6810KLW--Datasheet/数据表在线中文翻译

A6810

10-Bit Serial Input Latched Source Driver

Features and Benefits

Description

ƒ Controlled output slew rate

ƒ High-speed data storage

The A6810 combines 10-bit CMOS shift registers,

accompanying data latches, and control circuitry with bipolar

sourcing outputs and PNP active pull-downs. Designed

primarily to drive vacuum-fluorescent (VF) displays, the 60 V

and –40 mAoutput ratings also allow this device to be used in

many other peripheral power driver applications. The A6810

features an increased data input rate (compared with the older

UCN/UCQ5810-F) and a controlled output slew rate.

ƒ 60 V minimum output breakdown

ƒ High data-input rate

ƒ PNP active pull-downs

ƒ Low output-saturation voltages

ƒ Low-power CMOS logic and latches

ƒ Improved replacements for TL4810x, UCN5810x, and

UCQ5810x

The CMOS shift register and latches allow direct interfacing

with microprocessor-based systems. With a 3.3 or 5 V logic

supply, serial data-input rates of at least 10 MHz can be

attained

Packages:

A CMOS serial data output permits cascaded connections in

applications requiring additional drive lines. Similar devices

are available as the A6812 (20-bit) and A6818 (32-bit).

TheA6810outputsourcedriversareNPNDarlingtons,capable

ofsourcingupto40mA.Thecontrolledoutputslewratereduces

electromagnetic noise, which is an important consideration in

systemsthatincludetelecommunicationsandmicroprocessors,

and to meet government emissions regulations. For inter-digit

18-pin DIP

(A package)

20-pin SOICW

(LW package)

Not to scale

Continued on the next page…

Functional Block Diagram

26182.124F

A6810

10-Bit Serial Input Latched Source Driver

Description (continued)

DIP (package A) and surface-mount SOIC (package LW). Copper

leadframes,lowlogic-powerdissipation,andlowoutput-saturation

voltages allow all devices to source 25 mA from all outputs

continuously over the full operating temperature range.

blanking, all output drivers can be disabled and all sink drivers

turned on with a BLANKING input high. The PNP active pull-

downs can sink at least 2.5 mA.

The A6810 is available in three temperature ranges for optimum

performance in commercial (S), industrial (E), and automotive (K)

applications. It is provided in two package styles, through-hole

The lead (Pb) free versions have 100% matte tin leadframe

plating.

Selection Guide

Part Number

Pb-free

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Packing

Ambient Temperature, T_A(°C)

Package

A6810SA*

A6810SA-T

A6810EA*

A6810EA-T

A6810KA*

A6810KA-T

A6810SLW*

A6810SLW-T

A6810SLWTR*

A6810SLWTR-T

A6810ELW*

A6810ELW-T

A6810ELWTR*

A6810ELWTR-T

A6810KLW*

A6810KLW-T

A6810KLWTR

A6810KLWTR-T

21 pieces/tube

–20 to 85

21 pieces/tube

–40 to 85

18-pin DIP

–40 to 125

37 pieces/tube

–20 to 85

–40 to 85

–40 to 125

1000 pieces/13-in. reel

37 pieces/tube

20-pin SOIC-W

1000 pieces/13-in. reel

37 pieces/tube

Yes

–

Yes

1000 pieces/13-in. reel

*Certain variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates

that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The

variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer avail-

able. Status date change October 29, 2007. Deadline for receipt of LAST TIME BUY orders is April 25, 2008. These variants include:

A6810EA, A6810ELW, A6810ELWTR, A6810KLW, A6810SA, A6810SLW, and A6810SLWTR.

Absolute Maximum Ratings*

Characteristic

Symbol

V_DD

Notes

Rating

7.0

Units

V

Logic Supply Voltage

Driver Supply Voltage

V_BB

60

V

Input Voltage Range

V_IN

–0.3 to V_DD+ 0.3

–40 to 15

–40 to 85

–40 to 125

–20 to 85

150

V

Continuous Output Current Range

I_OUT

mA

ºC

Range E

Range K

Range S

Operating Ambient Temperature

T_A

Maximum Junction Temperature

Storage Temperature

T_J(max)

T

stg

–55 to 125

*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high

static electrical charges.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

2

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A6810

10-Bit Serial Input Latched Source Driver

Pin-out Diagrams

Thermal Characteristics

Characteristic

Symbol

Test Conditions*

Value Units

Package A, 1-layer PCB with copper limited to solder pads

65

ºC/W

Package Thermal Resistance

R_șJA

Package LW, 1-layer PCB with copper limited to solder pads

90

ºC/W

*Additional thermal information available on the Allegro website.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

3

A6810

10-Bit Serial Input Latched Source Driver

ELECTRICAL CHARACTERISTICS at T = +25°C (A6810S-) or over operating temperature range (A6810E-),

A

V

= 60 V; unless otherwise noted

BB

Limits @ V

= 3.3 V Limits @ V

= 5 V

DD

Characteristic

Symbol

Test Conditions

= 0 V

Mln.

—

Typ.

Max.

-15

—

Min. Typ. Max.

<-0.1 -15

Units

A

V

Output Leakage Current

Output Voltage

I

V

<-0.1

58.3

1.0

—

CEX

OUT

V

I

= -25 mA

= 1 mA

57.5

—

57.5 58.3

—

1.5

—

OUT(1)

OUT(0)

OUT

1.5

—

2.5

3.3

—

1.0

5.0

—

V

Output Pull-Down Current

Input Voltage

I

V

= 5 V to V

2.5

2.2

—

5.0

mA

V

OUT

BB

V

—

IN(1)

IN(0)

IN(1)

IN(0)

—

1.1

1.0

—

1.7

V

Input Current

I

V

= V

—

<0.01

—

<0.01 1.0

<-0.01 -1.0

A

V

IN

DD

= 0 V

—

<-0.01 -1.0

—

IN

Input Clamp Voltage

V

I

= -200 A

—

-0.8

3.05

0.15

—

-1.5

—

-0.8

4.75

0.15

—

-1.5

—

IK

IN

Serial Data Output Voltage

V

= -200 A

= 200 A

2.8

—

4.5

—

V

OUT(1)

OUT(0)

OUT

0.3

—

0.3

—

V

Maximum Clock Frequency

Logic Supply Current

f

10*

—

10*

—

MHz

mA

A

s

c

I

All Outputs High

All Outputs Low

0.25

1.5

0.2

0.7

1.8

0.7

1.8

—

0.75

3.0

20

0.3

1.5

0.2

0.7

1.8

0.7

1.8

—

1.0

3.0

20

DD(1)

DD(0)

I

—

Load Supply Current

I

All Outputs High, No Load

All Outputs Low

—

BB(1)

BB(0)

I

—

Blanking-to-Output Delay

Strobe-to-Output Delay

t

C = 30 pF, 50% to 50%

—

2.0

3.0

2.0

3.0

12

—

2.0

3.0

2.0

3.0

12

dis(BQ)

L

t

C = 30 pF, 50% to 50%

—

en(BQ)

L

t

R = 2.3 k, C 30 pF

—

p(STH-QL)

L

t

R = 2.3 k, C 30 pF

—

p(STH-QH)

L

Output Fall Time

Output Rise Time

t

R = 2.3 k, C 30 pF

2.4

f

L

t

R = 2.3 k, C 30 pF

—

12

—

12

r

L

Output Slew Rate

dV/dt

R = 2.3 k, C 30 pF

4.0

—

20

—

4.0

—

20

—

V/s

L

Clock-to-Serial Data Out Delay t

I

= 200 A

50

ns

p(CH-SQX)

OUT

Negative current is deﬁned as coming out of (sourcing) the speciﬁed device terminal.

Typical data is is for design information only and is at T_A= +25°C.

*Operation at a clock frequency greater than the speciﬁed minimum value is possible but not warranteed.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

4

A6810

10-Bit Serial Input Latched Source Driver

TIMING REQUIREMENTS and SPECIFICATIONS

(Logic Levels are V_DDand Ground)

C

50%

CLOCK

A

B

SERIAL

DATA IN

DATA

50%

t

p(CH-SQX)

SERIAL

DATA OUT

DATA

50%

D

E

50%

STROBE

BLANKING

LOW = ALL OUTPUTS ENABLED

t

p(STH-QH)

t

p(STH-QL)

90%

DATA

OUT

N

10%

Dwg. WP-029

HIGH = ALL OUTPUTS BLANKED (DISABLED)

50%

BLANKING

OUT

t

dis(BQ)

t

f

r

t

90%

50%

en(BQ)

DATA

N

10%

Dwg. WP-030A

A. Data Active Time Before Clock Pulse

(Data Set-Up Time), t_su(D)........................................... 25 ns

B. Data Active Time After Clock Pulse

SERIAL DATA must appear at the input prior to the rising edge

of the CLOCK input waveform.

(Data Hold Time), t_h(D)................................................ 25 ns

C. Clock Pulse Width, t_w(CH)................................................. 50 ns

D. Time Between Clock Activation and Strobe, t_su(C)......... 100 ns

E. Strobe Pulse Width, t_w(STH).............................................. 50 ns

NOTE – Timing is representative of a 10 MHz clock. Higher

speeds may be attainable; operation at high temperatures will

reduce the speciﬁed maximum clock frequency.

Information present at any register is transferred to the

respective latch when the STROBE is high (serial-to-parallel

conversion). The latches will continue to accept new data as

long as the STROBE is held high. Applications where the

latches are bypassed (STROBE tied high) will require that the

BLANKING input be high during serial data entry.

When the BLANKING input is high, the output source

drivers are disabled (OFF); the PNP active pull-down sink

drivers are ON. The information stored in the latches is not

affected by the BLANKING input. With the BLANKING input

low, the outputs are controlled by the state of their respective

latches.

Serial Data present at the input is transferred to the shift

register on the logic “0” to logic “1” transition of the CLOCK

input pulse. On succeeding CLOCK pulses, the registers shift

data information towards the SERIAL DATA OUTPUT. The

Allegro MicroSystems, Inc.

5

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A6810

10-Bit Serial Input Latched Source Driver

TRUTH TABLE

Serial

Data Clock

Input Input I

Shift Register Contents

Serial

Data Strobe

Output Input

Latch Contents

Output Contents

I

...

I

...

I

Blanklng

I

... I

I

1

2

3

N-1

N

1

2

3

N-1

N

1

2

3

N-1 N

H

L

H

L

R

X

R

X

...

R

X

R

X

R

X

1

2

3

N-2

N-1

N

N-1

N

X

R

X

1

L

R

...

R

1

2

3

N-1

N

P

H

P

X

P

X

P

X

P

X

P

L

P

L

P

L

P

L

... P

P

N-1 N

1

2

3

N-1

N

1

2

3

N-1

N

1

2

3

X

H

... L

L

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

6

A6810

10-Bit Serial Input Latched Source Driver

Package A 18-Pin DIP

11.86 0.5ꢀ

ꢀ8

+0.ꢀ0

–0.05

0.15

+0.38

–0.15

+0.76

–0.15

ꢀ0.91

7.61

6.35

A

ꢀ

1

C

5.33 MAX

+0.5ꢀ

SEATING

PLANE

3.30

–0.38

All dimensions nominal, not for tooling use

(reference JEDEC MS-00ꢀ AC)

Dimensions in inches

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

1.54

+0.15

–0.38

ꢀ.51

0.46 0.ꢀ1

A

Terminal #ꢀ mark area

Package LW 20-Pin SOICW

ꢀ1.80 0.10

4°

4

10

+0.07

–0.06

1.15

0.17

ꢀ0.30 0.33

7.50 0.ꢀ0

9.50

ꢀ.17

A

+0.44

0.84

0.15

–0.43

ꢀ

1

ꢀ

1

0.65

PCB Layout Reference View

B

10X

C

SEATING PLANE

GAUGE PLANE

SEATING

0.ꢀ0

C

PLANE

ꢀ.17

0.4ꢀ 0.ꢀ0

1.65 MAX

0.10 0.ꢀ0

Terminal #ꢀ mark area

For Reference Only

A

B

Dimensions in millimeters

Reference pad layout (reference IPC SOICꢀ17Pꢀ030X165-10M)

All pads a minimum of 0.10 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

(Reference JEDEC MS-0ꢀ3 AC)

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Allegro MicroSystems, Inc.

115 Northeast Cutoff

7

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A6810

10-Bit Serial Input Latched Source Driver

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-

mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;

nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, Inc.

8

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com