转到网站首页
转为中文步骤：
1、请用电脑端360浏览器打开本页地址，如您电脑未安装360浏览器，请点这里下载;
2、点击360浏览器右上角的翻译插件，如右图红圈中所示:
3、点击所弹出窗口里的右下角的按钮 “翻译当前网页”;
4、弹窗提示翻译完毕后关闭弹窗即可；
ASM1232LP, ASM1232LPS  
5 V mP Power Supply  
Monitor and Reset Circuit  
Description  
The ASM1232LP/LPS is a fully integrated microprocessor  
Supervisor. It can halt and restart a “hung−up” microprocessor, restart  
a microprocessor after a power failure. It has a watchdog timer and  
external reset override.  
http://onsemi.com  
A precision temperature−compensated reference and comparator  
circuits monitor the 5 V, V input voltage status. During power−up or  
CC  
when the V power supply falls outside selectable tolerance limits,  
CC  
both RESET and RESET become active. When V rises above the  
CC  
threshold voltage, the reset signals remain active for an additional  
250 ms minimum, allowing the power supply and system  
microprocessor to stabilize. The trip point tolerance signal, TOL,  
selects the trip level tolerance to be either 5% or 10%.  
PDIP−8  
P SUFFIX  
CASE 646AA  
MICRO−8  
U SUFFIX  
CASE 846AA  
Each device has both a push−pull, active HIGH reset output and an  
open drain active LOW reset output. A debounced manual reset input,  
PBRST, activates the reset outputs for a minimum period of 250 ms.  
There is a watchdog timer to stop and restart a microprocessor that is  
“hung−up”. The watchdog timeouts periods are selectable: 150 ms,  
610 ms and 1200 ms. If the ST input is not strobed LOW before the  
time−out period expires, a reset is generated.  
SOIC−8  
S SUFFIX  
CASE 751BD  
SOIC−16  
S SUFFIX  
CASE 751BG  
PIN CONFIGURATIONS  
1
Devices are available in 8−pin DIP, 16−pin SO and compact 8−pin  
MicroSO packages.  
V
CC  
PBRST  
TD  
Features  
ST  
• 5 V Supply Monitor  
RESET  
RESET  
TOL  
• Selectable Watchdog Period  
• Debounce Manual Push−button Reset Input  
GND  
• Precision Temperature−compensated Voltage Reference and  
DIP/SO/MicroSO  
(Top View)  
1
Comparator  
• Power−up, Power−down and Brown Out Detection  
• 250 ms Minimum Reset Time  
NC  
NC  
• Active LOW Open Drain Reset Output and Active HIGH Push−pull  
PBRST  
NC  
V
CC  
Output  
NC  
ST  
NC  
• Selectable Trip Point Tolerance: 5% or 10%  
TD  
• Low−cost Surface Mount Packages: 8−pin/16−pin SO, 8−pin DIP and  
8−pin Micro SO Packages  
NC  
• Wide Operating Temperature −40°C to +85°C (N Suffixed Devices)  
TOL  
NC  
RESET  
NC  
Applications  
• Microprocessor Systems  
• Computers  
• Controllers  
GND  
RESET  
SO  
(Top View)  
• Portable Equipment  
• Intelligent Instruments  
• Automotive Systems  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 12 of this data sheet.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
August, 2011 − Rev. 3  
ASM1232LP/D  
ASM1232LP, ASM1232LPS  
Figure 1. Typical Operating Circuit  
Figure 2. Block Diagram  
http://onsemi.com  
2
ASM1232LP, ASM1232LPS  
Table 1. PIN DESCRIPTION  
Pin #  
Pin #  
Pin  
8−Pin Package  
16−Pin Package  
Name  
Function  
Debounced manual pushbutton RESET input.  
Watchdog time delay selection. (t = 150 ms for T = GND, t = 610 ms  
1
2
2
4
PBRST  
T
D
TD  
D
TD  
for T = Open, and t = 1200 ms for T = V ).  
D
TD  
D
CC  
3
6
T
OL  
Selects 5% (T connected to GND) or 10% (T connected to V ) trip  
OL OL CC  
point tolerance.  
4
5
8
9
GND  
Ground.  
RESET  
Active HIGH reset output. RESET is active:  
1. If V falls below the reset voltage trip point.  
CC  
2. If PBRST is LOW.  
3. If ST is not strobed LOW before the timeout period set by T expires.  
D
4. During power−up.  
Active LOW reset output. (See RESET).  
Strobe input.  
6
7
8
11  
RESET  
ST  
13  
15  
V
CC  
5 V power.  
1,3,5,7,10,12,14,16  
NC  
No internal connection.  
Table 2. ABSOLUTE MAXIMUM RATINGS  
Parameter  
Min  
−0.5  
−0.5  
−0.5  
−40  
0
Max  
Unit  
V
Voltage on VCC (Note 1)  
7
Voltage on ST, TD (Note 1)  
V
V
+ 0.5  
V
CC  
Voltage on PBRST, RESET, RESET (Note 1)  
+ 0.5  
V
CC  
Operating Temperature Range (N suffixed devices)  
Operating Temperature Range (others)  
Soldering Temperature (for 10 sec)  
Storage Temperature  
+85  
°C  
°C  
°C  
°C  
KV  
V
70  
+260  
+125  
2
−55  
ESD rating  
HBM  
MM  
200  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. Voltages are measured with respect to ground  
http://onsemi.com  
3
 
ASM1232LP, ASM1232LPS  
Table 3. DC ELECTRICAL CHARACTERISTICS (Unless otherwise stated, 4.5 V ≤ V ≤ 5.5 V and over the operating  
CC  
temperature range of 0°C to 70°C (−40°C to +85°C. for N devices). All Voltages are referenced to ground.)  
Parameter  
Symbol  
Conditions  
Min  
4.5  
Typ  
Max  
Unit  
V
Supply Voltage  
V
CC  
5.5  
ST and PBRST Input High Level  
ST and PBRST Input Low Level  
V
2
V
CC  
+ 0.3  
V
IH  
V
−0.3  
4.50  
4.25  
62.5  
500  
250  
0.8  
4.74  
4.49  
250  
V
IL  
V
Trip Point (T = GND)  
V
4.62  
4.37  
150  
V
CC  
CC  
OL  
CCTP  
CCTP  
V
Trip Point (T = V  
)
V
V
OL  
CC  
Watchdog Timeout Period  
Watchdog Timeout Period  
Watchdog Timeout Period  
Output Voltage  
t
TD  
t
TD  
t
TD  
T
= GND  
ms  
ms  
ms  
V
D
T
= V  
1200  
610  
2000  
1000  
D
CC  
T
D
Floating  
V
OH  
I = −500 mA  
(Note 4)  
V
CC  
− 0.5  
V
− 0.1  
CC  
Output Current  
I
Output = 2.4 V  
(Note 3)  
−8  
−10  
mA  
OH  
Output Current  
I
Output = 0.4 V  
(Note 2)  
10  
mA  
mA  
V
OL  
Input Leakage  
I
−1.0  
1.0  
0.4  
IL  
RESET Low Level  
Internal Pull−up Resistor  
V
(Note 4)  
OL  
(Note 2)  
40  
kW  
mA  
pF  
pF  
ms  
Operating Current (CMOS)  
Input Capacitance  
I
30  
5
CC1  
C
IN  
Output Capacitance  
C
10  
OUT  
PBRST Manual Reset  
Minimum Low Time  
t
PB  
PBRST = V  
(Note 5)  
IL  
20  
250  
20  
Reset Active Time  
ST Pulse Width  
t
610  
5
1000  
8
ms  
ns  
ms  
RST  
t
ST  
V
CC  
V
CC  
Fail Detect to RESET or RESET  
Slew Rate  
t
RPD  
t
F
4.75 V to 4.25 V  
300  
ms  
PBRST Stable LOW to RESET and  
RESET Active  
t
20  
ms  
PDLY  
V
CC  
V
CC  
Detect to RESET or RESET inactive  
Slew Rate  
t
t = 5 ms  
RISE  
250  
0
610  
1000  
ms  
ns  
RPU  
t
R
4.25 V to 4.75 V  
2. PBRST is internally pulled HIGH to V through a nominal 40 kW resistor.  
CC  
3. RESET is an open drain output.  
4. RESET remains within 0.5 V of V on power−down until V falls below 2 V. RESET remains within 0.5 V of ground on power−down until  
CC  
CC  
V
CC  
falls below 2.0 V.  
5. Must not exceed the minimum watchdog time−out period (t ). The watchdog circuit cannot be disabled. To avoid a reset, ST must be strobed.  
TD  
http://onsemi.com  
4
 
ASM1232LP, ASM1232LPS  
Detailed Description  
Trip Point Tolerance Selection  
The ASM1232LP/LPS monitors the microprocessor or  
micro controller power supply and generates reset signal,  
both active HIGH and Active LOW, that halt processor  
operation whenever the power supply voltage levels are  
outside a predetermined tolerance.  
The TOL input is used to determine the level V can vary  
below 5 V without asserting a reset. With TOL connected to  
CC  
V
, RESET and RESET become active whenever V  
CC  
CC  
falls below 4.5 V. RESET and RESET become active when  
the V falls below 4.75 V if TOL is connected to ground.  
CC  
After V has risen above the trip point set by TOL,  
RESET and RESET remain active for a minimum time  
CC  
RESET and RESET outputs  
RESET is an active HIGH signal developed by a CMOS  
push−pull output stage and is the logical opposite to RESET.  
RESET is an active LOW signal. It is developed with an  
open drain driver. A pull up resistor of typical value 10 kW  
to 50 kW is required to connect with the output.  
period of 250 ms. On power−down, once V falls below the  
CC  
reset threshold RESET stays LOW and is guaranteed to be  
0.4 V or less until V drops below 1.2 V. The active HIGH  
CC  
reset signal is valid down to a V level of 1.2 V also.  
CC  
TRIP Point Voltage (V)  
Min  
4.25  
4.5  
Nom  
4.37  
4.62  
Max  
4.49  
4.74  
Tolerance Select  
Tolerance  
10%  
TOL = V  
CC  
TOL = GND  
5%  
Figure 3. Timing Diagram: Power Up  
Figure 4. Timing Diagram: Power Down  
http://onsemi.com  
5
ASM1232LP, ASM1232LPS  
Application Information  
When PBRST is held LOW for the minimum time t ,  
PB  
both resets become active and remain active for a minimum  
time period of 250 ms after PBRST returns HIGH.  
The debounced input is guaranteed to recognize pulses  
greater than 20 ms. No external pull−up resistor is required,  
since PBRST is pulled HIGH by an internal 40 kW resistor.  
The PBRST can be driven from a TTL or CMOS logic line  
or shorted to ground with a mechanical switch.  
Manual Reset Operation  
Push−button switch input, PBRST, allows the user to  
override the internal trip point detection circuits and issue  
reset signals. The pushbutton input is debounced and is  
pulled HIGH through an internal 40 kW resistor.  
Figure 5. Timing Diagram: Pushbutton Reset  
Figure 6. Application Circuit: Pushbutton Reset  
http://onsemi.com  
6
ASM1232LP, ASM1232LPS  
Watchdog Timer and ST Input  
A watchdog timer stops and restarts a microprocessor that  
is “hung−up”. The mP must toggle the ST input within a set  
period (as selectable through TD input) to verify proper  
software execution. If the ST is not toggled low within the  
minimum timeout period, reset signals become active. In  
power−up after the supply voltage returns to an in−tolerance  
condition, the reset signal remains active for 250 ms  
minimum, allowing the power supply and system  
microprocessor to stabilize. ST pulses as short as 20 ns can  
be detected.  
Figure 7. Timing Diagram: Strobe Input  
Timeouts periods of approximately 150 ms, 610 ms or 1,200 ms are selected through the TD pin.  
Watchdog Time−out Period (ms)  
Min  
62.5  
250  
500  
Nom  
150  
Max  
250  
TD Voltage level  
GND  
Floating  
610  
1000  
2000  
V
CC  
1200  
The watchdog timer cannot be disabled. It must be strobed with a high−to−low transition to avoid watchdog timeout and reset.  
Figure 8. Application Circuit: Watchdog Timer  
http://onsemi.com  
7
ASM1232LP, ASM1232LPS  
PACKAGE DIMENSIONS  
Micro8t/TSSOP8 3x3  
CASE 846AA−01  
ISSUE O  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
D
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE  
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED  
0.15 (0.006) PER SIDE.  
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.  
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.  
H
E
E
MILLIMETERS  
INCHES  
NOM  
−−  
0.003  
0.013  
0.007  
0.118  
DIM  
A
A1  
b
c
D
MIN  
−−  
0.05  
0.25  
0.13  
2.90  
2.90  
NOM  
−−  
MAX  
MIN  
−−  
0.002  
0.010  
0.005  
0.114  
0.114  
MAX  
0.043  
0.006  
0.016  
0.009  
0.122  
0.122  
PIN 1 ID  
1.10  
0.15  
0.40  
0.23  
3.10  
3.10  
e
0.08  
b 8 PL  
0.33  
M
S
S
0.08 (0.003)  
T
B
A
0.18  
3.00  
E
3.00  
0.118  
e
L
0.65 BSC  
0.55  
4.90  
0.026 BSC  
0.021  
0.193  
0.40  
4.75  
0.70  
5.05  
0.016  
0.187  
0.028  
0.199  
SEATING  
PLANE  
H
−T−  
E
A
0.038 (0.0015)  
L
A1  
c
SOLDERING FOOTPRINT*  
1.04  
0.38  
8X  
8X 0.041  
0.015  
3.20  
4.24  
5.28  
0.126  
0.167 0.208  
0.65  
6X0.0256  
SCALE 8:1  
mm  
inches  
ǒ
Ǔ
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
8
ASM1232LP, ASM1232LPS  
PACKAGE DIMENSIONS  
PDIP−8, 300 mils  
CASE 646AA−01  
ISSUE A  
SYMBOL  
MIN  
NOM  
MAX  
A
5.33  
A1  
A2  
b
0.38  
2.92  
0.36  
3.30  
0.46  
1.52  
0.25  
9.27  
4.95  
0.56  
1.78  
0.36  
10.16  
b2  
c
1.14  
0.20  
9.02  
E1  
D
E
E1  
e
7.62  
6.10  
7.87  
6.35  
8.25  
7.11  
2.54 BSC  
7.87  
2.92  
10.92  
3.80  
eB  
L
PIN # 1  
IDENTIFICATION  
3.30  
D
TOP VIEW  
E
A2  
A1  
A
c
b2  
L
eB  
e
b
SIDE VIEW  
END VIEW  
Notes:  
(1) All dimensions are in millimeters.  
(2) Complies with JEDEC MS-001.  
http://onsemi.com  
9
ASM1232LP, ASM1232LPS  
PACKAGE DIMENSIONS  
SOIC 8, 150 mils  
CASE 751BD−01  
ISSUE O  
SYMBOL  
MIN  
NOM  
MAX  
1.35  
A
1.75  
A1  
b
0.10  
0.33  
0.19  
4.80  
5.80  
3.80  
0.25  
0.51  
0.25  
5.00  
6.20  
4.00  
c
E1  
E
D
E
E1  
e
1.27 BSC  
h
0.25  
0.40  
0º  
0.50  
1.27  
8º  
L
PIN # 1  
IDENTIFICATION  
θ
TOP VIEW  
D
h
A1  
θ
A
c
e
b
L
SIDE VIEW  
END VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MS-012.  
http://onsemi.com  
10  
ASM1232LP, ASM1232LPS  
PACKAGE DIMENSIONS  
SOIC−16, 150 mils  
CASE 751BG−01  
ISSUE O  
SYMBOL  
MIN  
NOM  
MAX  
1.35  
A
A1  
b
1.75  
0.25  
0.51  
0.25  
0.10  
0.33  
0.19  
c
D
E
E1  
e
9.80  
5.80  
3.80  
9.90  
6.00  
10.00  
6.20  
4.00  
E1  
E
3.90  
1.27 BSC  
h
0.25  
0.40  
0º  
0.50  
1.27  
8º  
L
θ
PIN#1 IDENTIFICATION  
TOP VIEW  
D
h
q
A
c
e
b
L
A1  
END VIEW  
SIDE VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MS-012.  
http://onsemi.com  
11  
ASM1232LP, ASM1232LPS  
Table 4. ORDERING INFORMATION  
Operating  
Temperature  
Range  
Maximum  
Supply  
Current (mA)  
Voltage  
Monitoring  
Application  
Part Number (Note 6)  
TIN−LEAD DEVICES  
ASM1232LP  
Package  
Package Marking  
8L PDIP  
8L PDIP  
0°C to +70°C  
−40°C to +85°C  
0°C to +70°C  
30  
30  
30  
30  
30  
30  
30  
30  
5 V  
5 V  
5 V  
5 V  
5 V  
5 V  
5 V  
5 V  
ASM1232LP  
ASM1232LPN  
ASM1232LPS  
ASM1232LPS−2  
ASM1232LPSN  
ASM1232LPSN−2  
ASM1232LP  
ASM1232LPN  
ASM1232LPS  
16L SOIC  
8L SOIC  
16L SOIC  
8L SOIC  
8L MSOP  
8L MSOP  
ASM1232LPS−2  
ASM1232LPSN  
ASM1232LPSN−2  
ASM1232LPU  
0°C to +70°C  
−40°C to +85°C  
−40°C to +85°C  
0°C to +70°C  
ASM1232LPUN  
LEAD FREE DEVICES  
ASM1232LPF  
−40°C to +85°C  
ASM1232LPN  
8L PDIP  
8L PDIP  
0°C to +70°C  
−40°C to +85°C  
0°C to +70°C  
30  
30  
30  
30  
30  
30  
30  
30  
5 V  
5 V  
5 V  
5 V  
5 V  
5 V  
5 V  
5 V  
ASM1232LPF  
ASM1232LPNF  
ASM1232LPS−2F  
ASM1232LPSF  
ASM1232LPSN−2F  
ASM1232LPSNF  
ASM1232LPF  
ASM1232LPNF  
ASM1232LPS−2F  
ASM1232LPSF  
ASM1232LPSN−2F  
ASM1232LPSNF  
ASM1232LPUF  
ASM1232LPUNF  
8L SOIC  
16L SOIC  
8L SOIC  
16L SOIC  
8L MSOP  
8L MSOP  
0°C to +70°C  
−40°C to +85°C  
−40°C to +85°C  
0°C to +70°C  
−40°C to +85°C  
ASM1232LPNF  
6. For parts to be packed in Tape and Reel, add “−T” at the end of the part number.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5773−3850  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
ASM1232LP/D