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S25FL116K  
16-Mbit (2-Mbyte) CMOS 3.0-Volt Flash Non-Volatile Memory  
Serial Peripheral Interface (SPI) with Multi-I/O and  
Industrial and Automotive Temperature  
S25FL116K Cover Sheet  
Data Sheet (Preliminary)  
Notice to Readers: This document states the current technical specifications regarding the Spansion  
product(s) described herein. Each product described herein may be designated as Advance Information,  
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.  
Publication Number S25FL116K_00  
Revision 06  
Issue Date November 6, 2013  
D a t a S h e e t ( P r e l i m i n a r y )  
Notice On Data Sheet Designations  
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of  
product information or intended specifications throughout the product life cycle, including development,  
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify  
that they have the latest information before finalizing their design. The following descriptions of Spansion data  
sheet designations are presented here to highlight their presence and definitions.  
Advance Information  
The Advance Information designation indicates that Spansion Inc. is developing one or more specific  
products, but has not committed any design to production. Information presented in a document with this  
designation is likely to change, and in some cases, development on the product may discontinue. Spansion  
Inc. therefore places the following conditions upon Advance Information content:  
“This document contains information on one or more products under development at Spansion Inc.  
The information is intended to help you evaluate this product. Do not design in this product without  
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed  
product without notice.”  
Preliminary  
The Preliminary designation indicates that the product development has progressed such that a commitment  
to production has taken place. This designation covers several aspects of the product life cycle, including  
product qualification, initial production, and the subsequent phases in the manufacturing process that occur  
before full production is achieved. Changes to the technical specifications presented in a Preliminary  
document should be expected while keeping these aspects of production under consideration. Spansion  
places the following conditions upon Preliminary content:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. The Preliminary status of this document indicates that product qualification has been  
completed, and that initial production has begun. Due to the phases of the manufacturing process that  
require maintaining efficiency and quality, this document may be revised by subsequent versions or  
modifications due to changes in technical specifications.”  
Combination  
Some data sheets contain a combination of products with different designations (Advance Information,  
Preliminary, or Full Production). This type of document distinguishes these products and their designations  
wherever necessary, typically on the first page, the ordering information page, and pages with the DC  
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first  
page refers the reader to the notice on this page.  
Full Production (No Designation on Document)  
When a product has been in production for a period of time such that no changes or only nominal changes  
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include  
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed  
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a  
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following  
conditions to documents in this category:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. Spansion Inc. deems the products to have been in sufficient production volume such  
that subsequent versions of this document are not expected to change. However, typographical or  
specification corrections, or modifications to the valid combinations offered may occur.”  
Questions regarding these document designations may be directed to your local sales office.  
2
S25FL116K  
S25FL116K_00_06 November 6, 2013  
S25FL116K  
16-Mbit (2-Mbyte) CMOS 3.0-Volt Flash Non-Volatile Memory  
Serial Peripheral Interface (SPI) with Multi-I/O and  
Industrial and Automotive Temperature  
Data Sheet (Preliminary)  
Features  
Serial Peripheral Interface (SPI)  
– Three 256-byte Security Registers with OTP protection  
– Low supply voltage protection of the entire memory  
– Top / Bottom relative Block Protection Range, 4 kB to all of memory  
– 8-Byte Unique ID for each device  
– SPI Clock polarity and phase modes 0 and 3  
– Command subset and footprint compatible with S25FL016K  
Read  
– Non-volatile Status Register bits control protection modes  
– Software command protection  
– Normal Read (Serial): 50 MHz clock rate  
– Fast Read (Serial): 108 MHz clock rate  
– Dual / Quad (Multi-I/O) Read 108 MHz clock rate  
– 54 MB/s maximum continuous data transfer rate  
– Efficient eXecute-In-Place (XIP)  
– Hardware input signal protection  
– Lock-Down until power cycle protection  
– OTP protection of security registers  
90 nm Floating Gate Technology  
Single Supply Voltage: 2.7V to 3.6V  
– Continuous and wrapped read modes  
– Serial Flash Discoverable Parameters (SFDP)  
Program  
Temperature Ranges  
– Industrial (–40°C to +85°C)  
– Automotive (–40°C to +105°C)  
– Serial-input Page Program (up to 256 bytes)  
– Program Suspend and Resume  
Erase  
Package Options  
– Uniform sector erase (4 kB)  
– Uniform block erase (64 kB)  
– Bulk erase  
– S25FL116K  
– 8-lead SOIC (150 mil) - SOA008  
– 8-lead SOIC (208 mil) - SOC008  
– 8-contact WSON 5x6 - WND008  
– 24-ball BGA 6 mm x 8 mm - FAB024 and FAC024  
– KGD / KGW  
– Erase Suspend and Resume  
Cycling Endurance  
– 100K Program-Erase cycles on any sector, minimum  
Data Retention  
– 20-year data retention, typical  
Security  
Publication Number S25FL116K_00  
Revision 06  
Issue Date November 6, 2013  
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-  
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document  
may be revised by subsequent versions or modifications due to changes in technical specifications.  
D a t a S h e e t ( P r e l i m i n a r y )  
1. Performance Summary  
Table 1.1 Maximum Read Rates (VCC = 2.7V to 3.6V, 105°C)  
Clock Rate  
(MHz)  
Command  
Mbytes/s  
Read  
50  
6.25  
13.5  
27  
Fast Read  
Dual Read  
Quad Read  
108  
108  
108  
54  
Table 1.2 Typical Program and Erase Rates (VCC = 2.7V to 3.6V, 105°C)  
Operation  
kbytes/s  
Page Programming (256-byte page buffer)  
4-kbyte Sector Erase  
365  
58  
64-kbyte Sector Erase  
131  
Table 1.3 Typical Current Consumption (VCC = 2.7V to 3.6V, 105°C)  
Operation  
Current (mA)  
Serial Read 50 MHz  
Serial Read 108 MHz  
Dual Read 108 MHz  
Quad Read 108 MHz  
Program  
7
12  
14  
16  
20  
Erase  
20  
Standby  
0.015  
0.002  
Deep-Power Down  
4
S25FL116K  
S25FL116K_00_06 November 6, 2013  
D a t a S h e e t ( P r e l i m i n a r y )  
Table of Contents  
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.  
2.  
Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
2.1  
2.2  
2.3  
Migration Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Hardware Interface  
3.  
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
3.9  
Input / Output Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Address and Data Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Chip Select (CS#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Serial Input (SI) / IO0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Serial Output (SO) / IO1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Write Protect (WP#) / IO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
HOLD# / IO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Core and I/O Signal Voltage Supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
3.10 Supply and Signal Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
3.11 Not Connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
3.12 Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
3.13 Do Not Use (DNU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
3.14 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
4.  
5.  
Signal Protocols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4.1  
4.2  
4.3  
4.4  
4.5  
SPI Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Interface States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Status Register Effects on the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
5.1  
5.2  
5.3  
5.4  
5.5  
5.6  
5.7  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Power On (Cold) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
6.  
Physical Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
6.1  
6.2  
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Physical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Software Interface  
7.  
Address Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
7.1  
7.2  
7.3  
7.4  
7.5  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Flash Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Security Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Device Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
8.  
9.  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
8.1  
8.2  
8.3  
SPI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
9.1  
9.2  
Configuration and Status Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Program and Erase Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
November 6, 2013 S25FL116K_00_06  
S25FL116K  
5
D a t a S h e e t ( P r e l i m i n a r y )  
9.3  
9.4  
Read Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
ID and Security Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70  
10. Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
10.1 Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
10.2 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
Ordering Information  
11. Ordering Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
11.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
12. Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
6
S25FL116K  
S25FL116K_00_06 November 6, 2013  
D a t a S h e e t ( P r e l i m i n a r y )  
Figures  
Figure 3.1  
Figure 3.2  
Figure 3.3  
Figure 3.4  
Figure 4.1  
Figure 4.2  
Figure 4.3  
Figure 4.4  
Figure 4.5  
Figure 4.6  
Figure 4.7  
Figure 4.8  
Figure 4.9  
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Bus Master and Memory Devices on the SPI Bus – Single Bit Data Path. . . . . . . . . . . . . . . 17  
Bus Master and Memory Devices on the SPI Bus – Dual Bit Data Path . . . . . . . . . . . . . . . . 17  
Bus Master and Memory Devices on the SPI Bus – Quad Bit Data Path . . . . . . . . . . . . . . . 18  
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Stand Alone Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Single Bit Wide Input Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Single Bit Wide Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Single Bit Wide I/O Command without Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Single Bit Wide I/O Command with Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Dual Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Quad Output Command without Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Dual I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 4.10 Quad I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 5.1  
Figure 5.2  
Figure 5.3  
Figure 5.4  
Figure 5.5  
Figure 5.6  
Figure 5.7  
Figure 5.8  
Figure 5.9  
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Power-Up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Power-Down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
SPI Single Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
SPI Single Bit Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 5.10 SPI MIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 5.11 Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 5.12 WP# Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Figure 9.1  
Figure 9.2  
Figure 9.3  
Figure 9.4  
Figure 9.5  
Figure 9.6  
Figure 9.7  
Figure 9.8  
Figure 9.9  
Read Status Register Command Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Write Enable (WREN 06h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Write Enable for Volatile Status Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . 57  
Write Disable (WRDI 04h) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
Write Status Registers Command Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58  
Page Program Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
64 kB Block Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Figure 9.10 Erase / Program Suspend Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Figure 9.11 Erase / Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Figure 9.12 Read Data Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Figure 9.13 Fast Read Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
Figure 9.14 Fast Read Dual Output Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
Figure 9.15 Fast Read Quad Output Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65  
Figure 9.16 Fast Read Dual I/O Command Sequence (Initial command or previous M5-4 ≠ 10). . . . . . . 66  
Figure 9.17 Fast Read Dual I/O Command Sequence (Previous command set M5-4 = 10) . . . . . . . . . . 66  
Figure 9.18 Fast Read Quad I/O Command Sequence (Initial command or previous M5-4 ≠10) . . . . . . 67  
Figure 9.19 Fast Read Quad I/O Command Sequence (Previous command set M5-4 = 10). . . . . . . . . . 67  
Figure 9.20 Set Burst with Wrap Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
Figure 9.21 Continuous Read Mode Reset for Fast Read Dual or Quad I/O . . . . . . . . . . . . . . . . . . . . . . 69  
Figure 9.22 Deep Power-Down Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70  
Figure 9.23 Release from Deep-Power-Down Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
Figure 9.24 Read Electronic Signature (RES ABh) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . 71  
Figure 9.25 READ_ID (90h) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
Figure 9.26 Read JEDEC ID Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
Figure 9.27 Read SFDP Register Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
Figure 9.28 Erase Security Registers Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
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Figure 9.29 Program Security Registers Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
Figure 9.30 Read Security Registers Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
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Tables  
Table 1.1  
Table 1.2  
Table 1.3  
Table 2.1  
Table 3.1  
Table 4.1  
Table 5.1  
Table 5.2  
Table 5.3  
Table 5.4  
Table 5.5  
Table 5.6  
Table 5.7  
Table 5.8  
Table 6.1  
Table 6.2  
Table 6.3  
Table 7.1  
Table 7.2  
Table 7.3  
Table 7.4  
Table 7.5  
Table 7.6  
Table 7.7  
Table 7.8  
Table 7.9  
Table 7.10  
Table 7.11  
Table 9.1  
Table 9.2  
Table 9.3  
Table 9.4  
Table 10.1  
Table 11.1  
Maximum Read Rates (VCC = 2.7V to 3.6V, 105°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Typical Program and Erase Rates (VCC = 2.7V to 3.6V, 105°C) . . . . . . . . . . . . . . . . . . . . . . . 4  
Typical Current Consumption (VCC = 2.7V to 3.6V, 105°C). . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
FL Generations Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Interface States Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Latchup Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Power-Up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Industrial Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
8-Connector Package, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
24-Ball BGA, 5x5 Ball Footprint (FAB024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
24-Ball BGA, 4x6 Ball Footprint (FAC024), Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
S25FL116K Main Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Security Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Serial Flash Discoverable Parameter Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Status Register-1 (SR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Status Register-2 (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Status Register-3 (SR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
FL116K Block Protection (CMP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
FL116K Block Protection (CMP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
Status Register Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Latency Cycles Versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Device Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
Command Set (Configuration, Status, Erase, Program Commands(1)) . . . . . . . . . . . . . . . . 54  
Command Set (Read Commands). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Command Set (ID, Security Commands). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Commands Accepted During Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Erase Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
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2. General Description  
The S25FL116K of the FL1-K family non-volatile flash memory devices connect to a host system via a Serial  
Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SIngle I/O or SIO) is supported as  
well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial protocols. This multiple width  
interface is called SPI Multi-I/O or MIO.  
The SPI-MIO protocols use only 4 to 6 signals:  
Chip Select (CS#)  
Serial Clock (CLK)  
Serial Data  
– IO0 (SI)  
– IO1 (SO)  
– IO2 (WP#)  
– IO3 (HOLD#)  
The SIO protocol uses Serial Input (SI) and Serial Output (SO) for data transfer. The DIO protocols use IO0  
and IO1 to input or output two bits of data in each clock cycle.  
The Write Protect (WP#) input signal option allows hardware control over data protection. Software controlled  
commands can also manage data protection.  
The HOLD# input signal option allows commands to be suspended and resumed on any clock cycle.  
The QIO protocols use all of the data signals (IO0 to IO3) to transfer 4 bits in each clock cycle. When the QIO  
protocols are enabled the WP# and HOLD# inputs and features are disabled.  
Clock frequency of up to 108 MHz is supported, allowing data transfer rates up to:  
Single bit data path = 13.5 Mbytes/s  
Dual bit data path = 27 Mbytes/s  
Quad bit data path = 54 Mbytes/s  
Executing code directly from flash memory is often called eXecute-In-Place or XIP. By using S25FL116K  
devices at the higher clock rates supported, with QIO commands, the command read transfer rate can match  
or exceed traditional x8 or x16 parallel interface, asynchronous, NOR flash memories, while reducing signal  
count dramatically. The Continuous Read Mode allows for random memory access with as few as 8-clocks of  
overhead for each access, providing efficient XIP operation. The Wrapped Read mode provides efficient  
instruction or data cache refill via a fast read of the critical byte that causes a cache miss, followed by reading  
all other bytes in the same cache line in a single read command.  
The S25FL116K:  
Support JEDEC standard manufacturer and device type identification.  
Program pages of 256 bytes each. One to 256 bytes can be programmed in each Page Program operation.  
Pages can be erased in groups of 16 (4-kB aligned sector erase), groups of 256 (64-kB aligned block  
erase), or the entire chip (chip erase).  
The S25FL116K operates on a single 2.7V to 3.6V power supply and all devices are offered in space-  
saving packages.  
Provides an ideal storage solution for systems with limited space, signal connections, and power. These  
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for  
code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.  
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2.1  
2.1.1  
Migration Notes  
Features Comparison  
The S25FL1-K (S25FL116K, S25FL132K, and S25FL164K) is command set and footprint compatible with  
prior generation FL-K and FL-P families.  
Table 2.1 FL Generations Comparison  
Parameter  
Technology Node  
S25FL1-K  
90 nm  
S25FL-K  
90 nm  
S25FL-P  
90 nm  
Architecture  
Floating Gate  
In Production  
16 Mbit - 64 Mbit  
x1, x2, x4  
Floating Gate  
In Production  
4 Mbit - 128 Mbit  
x1, x2, x4  
MirrorBit®  
Release Date  
In Production  
32 Mbit - 256 Mbit  
x1, x2, x4  
Density  
Bus Width  
Supply Voltage  
2.7V - 3.6V  
2.7V - 3.6V  
2.7V - 3.6V  
Normal Read Speed  
Fast Read Speed  
Dual Read Speed  
Quad Read Speed  
Program Buffer Size  
Page Programming Time (typ.)  
Program Suspend / Resume  
Erase Sector Size  
Parameter Sector Size  
Sector Erase Time (typ.)  
Erase Suspend / Resume  
OTP Size  
6 MB/s (50 MHz)  
13.5 MB/s (108 MHz)  
27 MB/s (108 MHz)  
54 MB/s (108 MHz)  
256B  
6 MB/s (50 MHz)  
13 MB/s (104 MHz)  
26 MB/s (104 MHz)  
52 MB/s (104 MHz)  
256B  
5 MB/s (40 MHz)  
13 MB/s (104 MHz)  
20 MB/s (80 MHz)  
40 MB/s (80 MHz)  
256B  
700 µs (256B)  
Yes  
700 µs (256B)  
Yes  
1500 µs (256B)  
No  
4 kB / 64 kB  
4 kB / 32 kB / 64 kB  
N/A  
64 kB / 256 kB  
4 kB  
N/A  
70 ms (4 kB), 350 ms (64 kB)  
Yes  
30 ms (4 kB), 150 ms (64 kB)  
Yes  
500 ms (64 kB)  
No  
768B (3 x 256B)  
–40°C to +85°C / +105°C  
768B (3 x 256B)  
–40°C to +85°C  
506B  
Operating Temperature  
–40°C to +85°C / +105°C  
Notes:  
1. S25FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.  
2. S25FL1-K family devices can erase 4-kB sectors in groups of 64 kB.  
3. S25FL-P has either 64-kB or 256-kB uniform sectors depending on an ordering option.  
4. Refer to individual data sheets for further details.  
2.1.2  
Known Feature Differences from Prior Generations  
Secure Silicon Region (OTP)  
2.1.2.1  
The size and format (address map) of the One Time Program area is the same for the S25FL1-K and the  
S25FL-K but different for the S25FL-P.  
2.1.2.2  
Commands Not Supported  
The following S25FL-K and S25FL-P commands are not supported:  
Quad Page PGM (32h)  
Half-Block Erase 32K (52h)  
Word read Quad I/O (E7)  
Octal Word Read Quad I/O (E3h)  
MFID dual I/O (92h)  
MFID quad I/O (94h)  
Read Unique ID (4Bh)  
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2.1.2.3  
New Features  
The S25FL116K introduces new features to low density SPI category memories:  
Variable read latency (number of dummy cycles) for faster initial access time or higher clock rate read  
commands  
Automotive temperature range  
Volatile configuration option in addition to legacy non-volatile configuration  
2.2  
Glossary  
Command = All information transferred between the host system and memory during one period while  
CS# is low. This includes the instruction (sometimes called an operation code or opcode) and any required  
address, mode bits, latency cycles, or data.  
Flash = The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases  
large blocks of memory bits in parallel, making the erase operation much faster than early EEPROM.  
High = A signal voltage level ≥ VIH or a logic level representing a binary one (1).  
Instruction = The 8-bit code indicating the function to be performed by a command (sometimes called an  
operation code or opcode). The instruction is always the first 8 bits transferred from host system to the  
memory in any command.  
Low = A signal voltage level ≤ VIL or a logic level representing a binary zero (0).  
LSB = Least Significant Bit = Generally the right most bit, with the lowest order of magnitude value, within  
a group of bits of a register or data value.  
MSB = Most Significant Bit = Generally the left most bit, with the highest order of magnitude value, within a  
group of bits of a register or data value.  
Non-Volatile = No power is needed to maintain data stored in the memory.  
OPN = Ordering Part Number = The alphanumeric string specifying the memory device type, density,  
package, factory non-volatile configuration, etc. used to select the desired device.  
Page = 256-byte aligned and length group of data.  
PCB = Printed Circuit Board.  
Register Bit References = Are in the format: Register_name[bit_number] or  
Register_name[bit_range_MSB: bit_range_LSB].  
Sector = Erase unit size; all sectors are physically 4-kbytes aligned and length. Depending on the erase  
command used, groups of physical sectors may be erased as a larger logical sector of 64 kbytes.  
Write = An operation that changes data within volatile or non-volatile registers bits or non-volatile flash  
memory. When changing non-volatile data, an erase and reprogramming of any unchanged non-volatile  
data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in  
the same way that volatile data is modified – as a single operation. The non-volatile data appears to the  
host system to be updated by the single write command, without the need for separate commands for  
erase and reprogram of adjacent, but unaffected data.  
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2.3  
2.3.1  
Other Resources  
Links to Software  
http://www.spansion.com/Support/Pages/Support.aspx  
2.3.2  
2.3.3  
Links to Application Notes  
http://www.spansion.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx  
Specification Bulletins  
Specification bulletins provide information on temporary differences in feature description or parametric  
variance since the publication of the last full data sheet. Contact your local sales office for details. Obtain the  
latest list of company locations and contact information at:  
http://www.spansion.com/About/Pages/Locations.aspx  
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Hardware Interface  
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)  
Many memory devices connect to their host system with separate parallel control, address, and data signals  
that require a large number of signal connections and larger package size. The large number of connections  
increase power consumption due to so many signals switching and the larger package increases cost.  
The S25FL116K reduces the number of signals for connection to the host system by serially transferring all  
control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package,  
reduces signal switching power, and either reduces the host connection count or frees host connectors for  
use in providing other features.  
The S25FL116K uses the industry standard single bit Serial Peripheral Interface (SPI) and also supports  
commands for two bit (Dual) and four bit (Quad) wide serial transfers. This multiple width interface is called  
SPI Multi-I/O or SPI-MIO.  
3. Signal Descriptions  
3.1  
Input / Output Summary  
Table 3.1 Signal List  
Signal Name  
SCK  
Type  
Input  
Input  
I/O  
Description  
Serial Clock.  
Chip Select.  
CS#  
SI (IO0)  
SO (IO1)  
Serial Input for single bit data commands. IO0 for Dual or Quad commands.  
Serial Output for single bit data commands. IO1 for Dual or Quad commands.  
I/O  
Write Protect in single bit or Dual data commands. IO2 in Quad mode. The signal has an  
internal pull-up resistor and may be left unconnected in the host system if not used for  
Quad commands.  
WP# (IO2)  
I/O  
I/O  
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode.  
The signal has an internal pull-up resistor and may be left unconnected in the host  
system if not used for Quad commands.  
HOLD# (IO3)  
VCC  
VSS  
Supply  
Supply  
Core and I/O Power Supply.  
Ground.  
Not Connected. No device internal signal is connected to the package connector nor is  
there any future plan to use the connector for a signal. The connection may safely be  
used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal  
NC  
Unused  
connected to an NC must not have voltage levels higher than VCC  
.
Reserved for Future Use. No device internal signal is currently connected to the  
package connector but there is potential future use of the connector for a signal. It is  
recommended to not use RFU connectors for PCB routing channels so that the PCB may  
take advantage of future enhanced features in compatible footprint devices.  
RFU  
Reserved  
Do Not Use. A device internal signal may be connected to the package connector. The  
connection may be used by Spansion® for test or other purposes and is not intended for  
connection to any host system signal. Any DNU signal related function will be inactive  
when the signal is at VIL. The signal has an internal pull-down resistor and may be left  
unconnected in the host system or may be tied to VSS. Do not use these connections for  
PCB signal routing channels. Do not connect any host system signal to this connection.  
DNU  
Reserved  
Note:  
1. A signal name ending with the # symbol is active when low.  
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3.2  
Address and Data Configuration  
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only  
on the SI signal. Data may be sent back to the host serially on the Serial Output (SO) signal.  
Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will  
be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,  
and IO3.  
Dual or Quad Input / Output (I/O) commands send information from the host to the memory as bit pairs on IO0  
and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs  
on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.  
3.3  
3.4  
Serial Clock (SCK)  
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data  
input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK.  
Chip Select (CS#)  
The chip select signal indicates when a command for the device is in process and the other signals are  
relevant for the memory device. When the CS# signal is at the logic high state, the device is not selected and  
all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or  
Write Status Registers embedded operation is in progress, the device will be in the Standby Power mode.  
Driving the CS# input to logic low state enables the device, placing it in the Active Power mode. After Power-  
up, a falling edge on CS# is required prior to the start of any command.  
3.5  
3.6  
3.7  
Serial Input (SI) / IO0  
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data  
to be programmed. Values are latched on the rising edge of serial SCK clock signal.  
SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses,  
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out  
data (on the falling edge of SCK).  
Serial Output (SO) / IO1  
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of  
the serial SCK clock signal.  
SO becomes IO1, an input and output during Dual and Quad commands for receiving instructions,  
addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as  
shifting out data (on the falling edge of SCK).  
Write Protect (WP#) / IO2  
When WP# is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status  
Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status  
Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the  
memory area that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers, are also  
hardware protected against data modification while WP# remains Low.  
The WP# function is not available when the Quad mode is enabled (QE) in Status Register-2 (SR2[1]=1). The  
WP# function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to  
be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the  
falling edge of SCK).  
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the  
host system if not used for Quad mode.  
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3.8  
HOLD# / IO3  
The HOLD# signal is used to pause any serial communications with the device without deselecting the device  
or stopping the serial clock.  
To enter the Hold condition, the device must be selected by driving the CS# input to the logic low state. It is  
required that the user keep the CS# input low state during the entire duration of the Hold condition. This is to  
ensure that the state of the interface logic remains unchanged from the moment of entering the Hold  
condition.  
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with  
SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic  
low state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the HOLD#  
signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in  
progress.  
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care.  
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the  
SCK signal being at the logic low state. If the rising edge does not coincide with the SCK signal being at the  
logic low state, the Hold condition ends whenever the SCK signal reaches the logic low state.  
Figure 3.1 Hold Condition  
CS#  
SCLK  
HOLD#  
Hold Condition  
Standard Use  
Hold Condition  
Non-standard Use  
SI_or_IO_(during_input)  
SO_or_IO_(internal)  
SO_or_IO_(external)  
Valid Input  
Don’t Care  
B
Valid Input  
Don’t Care  
D
Valid Input  
D
A
A
C
E
E
B
B
C
3.9  
Core and I/O Signal Voltage Supply (V )  
CC  
VCC is the voltage source for all device internal logic and input / output signals. It is the single voltage used for  
all device functions including read, program, and erase.  
3.10 Supply and Signal Ground (V )  
SS  
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output  
drivers.  
3.11 Not Connected (NC)  
No device internal signal is connected to the package connector nor is there any future plan to use the  
connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit  
Board (PCB).  
3.12 Reserved for Future Use (RFU)  
No device internal signal is currently connected to the package connector but is there potential future use for  
the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the  
PCB may take advantage of future enhanced features in compatible footprint devices.  
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3.13 Do Not Use (DNU)  
A device internal signal may be connected to the package connector. The connection may be used by  
Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU  
signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor  
and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB  
signal routing channels. Do not connect any host system signal to these connections.  
3.14 Block Diagrams  
Figure 3.2 Bus Master and Memory Devices on the SPI Bus – Single Bit Data Path  
HOLD#  
HOLD#  
WP#  
SO  
SI  
WP#  
SI  
SO  
SCK  
SCK  
CS2#  
CS2#  
CS1#  
CS1#  
SPI  
SPI  
SPI  
Flash  
Flash  
Bus Master  
Figure 3.3 Bus Master and Memory Devices on the SPI Bus – Dual Bit Data Path  
HOLD#  
HOLD#  
WP#  
IO1  
IO0  
SCK  
WP#  
IO1  
IO0  
SCK  
CS2#  
CS2#  
CS1#  
CS1#  
SPI  
Flash  
SPI  
Flash  
SPI  
Bus Master  
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Figure 3.4 Bus Master and Memory Devices on the SPI Bus – Quad Bit Data Path  
IO3  
IO2  
IO3  
IO2  
IO1  
IO1  
IO0  
IO0  
SCK  
SCK  
CS2#  
CS2#  
CS1#  
CS1#  
SPI  
Flash  
SPI  
Flash  
SPI  
Bus Master  
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4. Signal Protocols  
4.1  
SPI Clock Modes  
The S25FL116K can be driven by an embedded microcontroller (bus master) in either of the two following  
clocking modes.  
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0  
Mode 3 with CPOL = 1 and, CPHA = 1  
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and  
the output data is always available from the falling edge of the SCK clock signal.  
The difference between the two modes is the clock polarity when the bus master is in standby mode and not  
transferring any data.  
SCK will stay at logic low state with CPOL = 0, CPHA = 0  
SCK will stay at logic high state with CPOL = 1, CPHA = 1  
Figure 4.1 SPI Modes Supported  
CPOL=0_CPHA=0_SCLK  
CPOL=1_CPHA=1_SCLK  
CS#  
SI  
MSB  
SO  
MSB  
Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by  
showing SCLK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode  
0 with SCLK low at the fall of CS#. In such a case, mode 3 timing simply means clock is high at the fall of CS#  
so no SCLK rising edge set up or hold time to the falling edge of CS# is needed for mode 3.  
SCLK cycles are measured (counted) from one falling edge of SCLK to the next falling edge of SCLK. In  
mode 0 the beginning of the first SCLK cycle in a command is measured from the falling edge of CS# to the  
first falling edge of SCLK because SCLK is already low at the beginning of a command.  
4.2  
Command Protocol  
All communication between the host system and S25FL116K is in the form of units called commands.  
All commands begin with an instruction that selects the type of information transfer or device operation to be  
performed. Commands may also have an address, instruction modifier (mode), latency period, data transfer  
to the memory, or data transfer from the memory. All instruction, address, and data information is transferred  
serially between the host system and memory device.  
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.  
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back  
to the host serially on the SO signal.  
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be  
returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,  
and IO3.  
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and  
IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on  
IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.  
Commands are structured as follows:  
Each command begins with CS# going low and ends with CS# returning high. The memory device is  
selected by the host driving the Chip Select (CS#) signal low throughout a command.  
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The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.  
Each command begins with an eight bit (byte) instruction. The instruction is always presented only as a  
single bit serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on  
each SCK rising edge. The instruction selects the type of information transfer or device operation to be  
performed.  
The instruction may be stand alone or may be followed by address bits to select a location within one of  
several address spaces in the device. The instruction determines the address space used. The address is  
a 24-bit, byte boundary, address. The address transfers occur on SCK rising edge.  
The width of all transfers following the instruction are determined by the instruction sent. Following  
transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done  
in 2-bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per  
(quad) transfer on the IO0-IO3 signals. Within the dual or quad groups the least significant bit is on IO0.  
More significant bits are placed in significance order on each higher numbered IO signal. SIngle bits or  
parallel bit groups are transferred in most to least significant bit order.  
Some instructions send an instruction modifier called mode bits, following the address, to indicate that the  
next command will be of the same type with an implied, rather than an explicit, instruction. The next  
command thus does not provide an instruction byte, only a new address and mode bits. This reduces the  
time needed to send each command when the same command type is repeated in a sequence of  
commands. The mode bit transfers occur on SCK rising edge.  
The address or mode bits may be followed by write data to be stored in the memory device or by a read  
latency period before read data is returned to the host.  
Write data bit transfers occur on SCK rising edge.  
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK  
cycles (also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are  
driven from the outputs on SCK falling edge at the end of the last read latency cycle. The first read data bits  
are considered transferred to the host on the following SCLK rising edge. Each following transfer occurs on  
the next SCK rising edge.  
If the command returns read data to the host, the device continues sending data transfers until the host  
takes the CS# signal high. The CS# signal can be driven high after any transfer in the read data sequence.  
This will terminate the command.  
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal  
must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is  
transferred. That is, the CS# signal must be driven high when the number of clock cycles after CS# signal  
was driven low is an exact multiple of eight cycles. If the CS# signal does not go high exactly at the eight  
SCLK cycle boundary of the instruction or write data, the command is rejected and not executed.  
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first.  
The data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the  
lowest address byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e.  
the byte address increments.  
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded  
operations) are ignored. The embedded operation will continue to execute without any affect. A very limited  
set of commands are accepted during an embedded operation. These are discussed in the individual  
command descriptions.  
Depending on the command, the time for execution varies. A command to read status information from an  
executing command is available to determine when the command completes execution and whether the  
command was successful.  
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4.2.1  
Command Sequence Examples  
Figure 4.2 Stand Alone Instruction Command  
CS#  
SCLK  
SI  
7
6
5
4
3
2
1
0
SO  
Phase  
Instruction  
Figure 4.3 Single Bit Wide Input Command  
CS#  
SCLK  
SI  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO  
Phase  
Instruction  
Input Data  
Figure 4.4 Single Bit Wide Output Command  
CS#  
SCLK  
SI  
7
6
5
4
3
2
1
0
SO  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Data1  
Data2  
Figure 4.5 Single Bit Wide I/O Command without Latency  
CS#  
SCLK  
SI  
7
6
5
4
3
2
1
0
23  
1
0
SO  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Data1  
Data2  
Figure 4.6 Single Bit Wide I/O Command with Latency  
CS#  
SCLK  
SI  
7
6
5
4
3
2
1
0
23  
1
0
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Dummy Cycles  
Data1  
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Figure 4.7 Dual Output Command  
CS#  
SCLK  
IO0  
IO1  
7
6
5
4
3
2
1
0 23 22 21 0  
Address  
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
Phase  
Instruction  
Dummy  
Data1  
Data2  
Figure 4.8 Quad Output Command without Latency  
CS#  
SCLK  
IO0  
7
6
5
4
3
2
1
0
23  
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
4
5
6
7
0
4
5
IO1  
1
2
3
1
2
3
IO2  
6
IO3  
7
Phase  
Instruction  
Address  
Data1  
Data2  
Data3  
Data4  
Data5  
...  
Figure 4.9 Dual I/O Command  
CS#  
SCLK  
IO0  
7
6
5
4
3
2
1
0
22  
23  
2
3
0
1
6
7
4
5
2
0
1
6
7
4
5
2
3
0
IO1  
3
1
Phase  
Instruction  
Address  
Dummy  
Data1  
Data2  
Figure 4.10 Quad I/O Command  
CS#  
SCLK  
IO0  
7
6
5
4
3
2
1
0
20  
21  
22  
23  
4
5
6
7
0
1
2
3
4
5
6
7
4
0
1
2
3
4
0
4
0
1
2
3
4
0
1
2
3
IO1  
5
6
7
5
6
7
1
2
3
5
6
7
5
6
7
IO2  
IO3  
Phase  
Instruction  
Address Mode  
Dummy  
D1  
D2  
D3  
D4  
Additional sequence diagrams, specific to each command, are provided in Commands on page 54.  
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4.3  
Interface States  
This section describes the input and output signal levels as related to the SPI interface behavior.  
Table 4.1 Interface States Summary  
HOLD# /  
IO3  
WP# /  
IO2  
SO /  
IO1  
Interface State  
Low Power  
Hardware Data Protection  
Power-On (Cold) Reset  
Interface Standby  
Instruction Cycle  
V
SCLK  
CS#  
SI / IO0  
CC  
< V  
X
X
X
X
Z
X
WI  
≥ V (min)  
X
X
HH  
X
X
X
X
X
Z
Z
Z
X
X
X
CC  
≥ V (min)  
CC  
≥ V (min)  
HT  
HL  
HL  
HH  
HL  
HV  
X
HV  
X
CC  
Hold Cycle  
≥ V (min)  
HV or HT  
CC  
Single Input Cycle  
Host to Memory Transfer  
≥ V (min)  
HT  
HT  
HT  
HL  
HL  
HL  
HH  
HH  
HH  
X
X
X
Z
Z
HV  
X
CC  
Single Latency (Dummy) Cycle  
≥ V (min)  
CC  
Single Output Cycle  
Memory to Host Transfer  
≥ V (min)  
MV  
X
CC  
Dual Input Cycle  
Host to Memory Transfer  
≥ V (min)  
HT  
HT  
HT  
HL  
HL  
HL  
HH  
HH  
HH  
X
X
X
HV  
X
HV  
X
CC  
Dual Latency (Dummy) Cycle  
≥ V (min)  
CC  
Dual Output Cycle  
Memory to Host Transfer  
≥ V (min)  
MV  
MV  
CC  
Quad Input Cycle  
Host to Memory Transfer  
≥ V (min)  
HT  
HT  
HT  
HL  
HL  
HL  
HV  
X
HV  
X
HV  
X
HV  
X
CC  
Quad Latency (Dummy) Cycle  
≥ V (min)  
CC  
Quad Output Cycle  
Memory to Host Transfer  
≥ V (min)  
MV  
MV  
MV  
MV  
CC  
Legend:  
Z
= no driver - floating signal  
HL = Host driving V  
HH = Host driving V  
IL  
IH  
HV = either HL or HH  
= HL or HH or Z  
HT = toggling between HL and HH  
X
ML = Memory driving V  
MH = Memory driving V  
MV = either ML or MH  
IL  
IH  
4.3.1  
Low Power Hardware Data Protection  
When VCC is less than VWI the memory device will ignore commands to ensure that program and erase  
operations can not start when the core supply voltage is out of the operating range.  
4.3.2  
Power-On (Cold) Reset  
When the core voltage supply remains at or below the VWI voltage for ≥ tPD time, then rises to ≥ VCC (Minimum)  
the device will begin its Power-On-Reset (POR) process. POR continues until the end of tPUW. During tPUW  
the device does not react to write commands. Following the end of tPUW the device transitions to the Interface  
Standby state and can accept write commands. For additional information on POR see Power On (Cold)  
Reset on page 31.  
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4.3.3  
4.3.4  
Interface Standby  
When CS# is high the SPI interface is in standby state. Inputs are ignored. The interface waits for the  
beginning of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a  
new command.  
While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is  
in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the  
algorithm when the entire device returns to standby current draw.  
Instruction Cycle  
When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device  
captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the  
device captures the next lower significance bit of the 8-bit instruction. The host keeps CS# low, HOLD# high,  
and drives Write Protect (WP#) signal as needed for the instruction. However, WP# is only relevant during  
instruction cycles of a Write Status Registers command and is otherwise ignored.  
Each instruction selects the address space that is operated on and the transfer format used during the  
remainder of the command. The transfer format may be Single, Dual output, Quad output, Dual I/O, or Quad  
I/O. The expected next interface state depends on the instruction received.  
Some commands are stand alone, needing no address or data transfer to or from the memory. The host  
returns CS# high after the rising edge of SCK for the eighth bit of the instruction in such commands. The next  
interface state in this case is Interface Standby.  
4.3.5  
4.3.6  
4.3.7  
Hold  
When Quad mode is not enabled (SR2[1]=0) the HOLD# / IO3 signal is used as the HOLD# input. The host  
keeps HOLD# low, SCLK may be at a valid level or continue toggling, and CS# is low. When HOLD# is low a  
command is paused, as though SCK were held low. SI / IO0 and SO / IO1 ignore the input level when acting  
as inputs and are high impedance when acting as outputs during hold state. Whether these signals are input  
or output depends on the command and the point in the command sequence when HOLD# is asserted low.  
When HOLD# returns high the next state is the same state the interface was in just before HOLD# was  
asserted low.  
Single Input Cycle – Host to Memory Transfer  
Several commands transfer information after the instruction on the single serial input (SI) signal from host to  
the memory device. The dual output, and quad output commands send address to the memory using only SI  
but return read data using the I/O signals. The host keeps CS# low, HOLD# high, and drives SI as needed for  
the command. The memory does not drive the Serial Output (SO) signal.  
The expected next interface state depends on the instruction. Some instructions continue sending address or  
data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly  
to Single, Dual, or Quad Output.  
Single Latency (Dummy) Cycle  
Read commands may have zero to several latency cycles during which read data is read from the main flash  
memory array before transfer to the host. The number of latency cycles are determined by the instruction.  
During the latency cycles, the host keeps CS# low, and HOLD# high. The Write Protect (WP#) signal is  
ignored. The host may drive the SI signal during these cycles or the host may leave SI floating. The memory  
does not use any data driven on SI / I/O0 or other I/O signals during the latency cycles. In dual or quad read  
commands, the host must stop driving the I/O signals on the falling edge at the end of the last latency cycle. It  
is recommended that the host stop driving I/O signals during latency cycles so that there is sufficient time for  
the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents  
driver conflict between host and memory when the signal direction changes. The memory does not drive the  
Serial Output (SO) or I/O signals during the latency cycles.  
The next interface state depends on the command structure i.e. the number of latency cycles, and whether  
the read is single, dual, or quad width.  
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4.3.8  
4.3.9  
4.3.10  
Single Output Cycle – Memory to Host Transfer  
Several commands transfer information back to the host on the single Serial Output (SO) signal. The host  
keeps CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory ignores the Serial  
Input (SI) signal. The memory drives SO with data.  
The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the  
command.  
Dual Input Cycle – Host to Memory Transfer  
The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host  
keeps CS# low, HOLD# high. The Write Protect (WP#) signal is ignored. The host drives address on SI / IO0  
and SO / IO1.  
The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are  
latency cycles needed or Dual Output Cycle if no latency is required.  
Dual Latency (Dummy) Cycle  
Read commands may have zero to several latency cycles during which read data is read from the main flash  
memory array before transfer to the host. The number of latency cycles are determined by the instruction.  
During the latency cycles, the host keeps CS# low, and HOLD# high. The Write Protect (WP#) signal is  
ignored. The host may drive the SI / IO0 and SO / IO1 signals during these cycles or the host may leave SI /  
IO0 and SO / IO1 floating. The memory does not use any data driven on SI / IO0 and SO / IO1 during the  
latency cycles. The host must stop driving SI / IO0 and SO / IO1 on the falling edge at the end of the last  
latency cycle. It is recommended that the host stop driving them during all latency cycles so that there is  
sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency  
cycles. This prevents driver conflict between host and memory when the signal direction changes. The  
memory does not drive the SI / IO0 and SO / IO1 signals during the latency cycles.  
The next interface state following the last latency cycle is a Dual Output Cycle.  
4.3.11  
Dual Output Cycle – Memory to Host Transfer  
The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps CS#  
low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory drives data on the SI / IO0 and  
SO / IO1 signals during the dual output cycles.  
The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the  
command.  
4.3.12  
4.3.13  
Quad Input Cycle – Host to Memory Transfer  
The Read Quad I/O command transfers four address, mode, or data bits to the memory in each cycle. The  
host keeps CS# low, and drives the IO signals.  
For Read Quad I/O the next interface state following the delivery of address and mode bits is a Quad Latency  
Cycle if there are latency cycles needed or Quad Output Cycle if no latency is required.  
Quad Latency (Dummy) Cycle  
Read commands may have zero to several latency cycles during which read data is read from the main flash  
memory array before transfer to the host. The number of latency cycles are determined by the Latency  
Control in the Status Register-3 (SR3[3:0]). During the latency cycles, the host keeps CS# low. The host may  
drive the IO signals during these cycles or the host may leave the IO floating. The memory does not use any  
data driven on IO during the latency cycles. The host must stop driving the IO signals on the falling edge at  
the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so  
that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the  
latency cycles. This prevents driver conflict between host and memory when the signal direction changes.  
The memory does not drive the IO signals during the latency cycles.  
The next interface state following the last latency cycle is a Quad Output Cycle.  
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4.3.14  
Quad Output Cycle – Memory to Host Transfer  
The Read Quad Output and Read Quad I/O return data to the host four bits in each cycle. The host keeps  
CS# low. The memory drives data on IO0-IO3 signals during the Quad output cycles.  
The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the  
command.  
4.4  
Status Register Effects on the Interface  
The Status Register-2, bit 1 (SR2[1]), selects whether Quad mode is enabled to ignore HOLD# and WP# and  
allow Read Quad Output, and Read Quad I/O commands.  
4.5  
Data Protection  
Some basic protection against unintended changes to stored data are provided and controlled purely by the  
hardware design. These are described below. Other software managed protection methods are discussed in  
the software section of this document.  
4.5.1  
Low Power  
When VCC is less than VWI the memory device will ignore commands to ensure that program and erase  
operations can not start when the core supply voltage is out of the operating range.  
4.5.2  
4.5.3  
4.5.4  
Power-Up  
Program and erase operations continue to be prevented during the Power-up to Write delay (tPUW) because  
no write command is accepted until after tPUW  
.
Deep-Power-Down (DPD)  
In DPD mode the device responds only to the Resume from DPD command (RES ABh). All other commands  
are ignored during DPD mode, thereby protecting the memory from program and erase operations.  
Clock Pulse Count  
The device verifies that all program, erase, and Write Status Registers commands consist of a clock pulse  
count that is a multiple of eight before executing them. A command not having a multiple of 8 clock pulse  
count is ignored and no error status is set for the command.  
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5. Electrical Characteristics  
5.1  
Absolute Maximum Ratings  
Table 5.1 Absolute Maximum Ratings  
Parameters (1)  
Symbol  
Conditions  
Range  
–0.6 to +4.0  
–0.6 to +4.0  
–2.0 to 6.0  
–65 to +150  
(2)  
Unit  
V
Supply Voltage  
V
CC  
Voltage Applied to Any Pin  
Transient Voltage on any Pin  
Storage Temperature  
Lead Temperature  
V
Relative to Ground  
V
IO  
V
< 20 ns Transient Relative to Ground  
V
IOT  
T
°C  
°C  
V
STG  
T
LEAD  
Electrostatic Discharge Voltage  
V
Human Body Model (3)  
–2000 to +2000  
ESD  
Notes:  
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed.  
Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent  
damage.  
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on  
restrictions on hazardous substances (RoHS) 2002/95/EU.  
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).  
5.1.1  
Input Signal Overshoot  
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage  
transitions, inputs or I/Os may overshoot VSS to negative VIOT or overshoot to positive VIOT, for periods up to  
20 ns.  
Figure 5.1 Maximum Negative Overshoot Waveform  
< 20 ns  
< 20 ns  
V
IL  
V
IOT  
< 20 ns  
Figure 5.2 Maximum Positive Overshoot Waveform  
< 20 ns  
VIOT  
VIH  
< 20 ns  
< 20 ns  
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5.1.2  
Latchup Characteristics  
Table 5.2 Latchup Specification  
Description  
Min  
–1.0  
–1.0  
–100  
Max  
Unit  
V
Input voltage with respect to V on all input only connections  
SS  
V
V
+ 1.0  
CC  
CC  
Input voltage with respect to V on all I/O connections  
SS  
+ 1.0  
V
V
Current  
+100  
mA  
CC  
Note:  
1. Excludes power supply V . Test conditions: V = 3.0 V, one connection at a time tested, connections not being tested are at V  
.
CC  
CC  
SS  
5.2  
Operating Ranges  
Operating ranges define those limits between which functionality of the device is guaranteed.  
Table 5.3 Operating Ranges  
Spec  
Parameter  
Symbol  
Conditions  
Unit  
Min  
–40  
–40  
2.7  
Max  
+85  
+105  
3.6  
Industrial  
Automotive  
°C  
°C  
V
Ambient Temperature  
TA  
Supply Voltage  
Full Range, Automotive Temp  
VCC  
Note:  
1.  
V
voltage during read can operate across the min and max range but should not exceed 10ꢀ of the voltage used during  
CC  
programming or erase of the data being read.  
5.3  
DC Electrical Characteristics  
Table 5.4 DC Electrical Characteristics  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
2
Unit  
µA  
Input Leakage  
I/O Leakage  
I
LI  
I
2
µA  
LO  
Standby Current  
I
CS# = V , V = GND or V  
15  
2
25  
5
µA  
CC1  
CC2  
CC IN  
CC  
Power-down Current  
I
CS# = V , V = GND or V  
µA  
CC IN  
CC  
SCK = 0.1 V / 0.9 V  
CC  
SO = Open  
CC  
CC  
CC  
CC  
Current: Read Single / Dual / Quad 1 MHz (2)  
I
I
I
I
4/5/6  
6/7/8  
6/7.5/9  
mA  
mA  
mA  
mA  
CC3  
CC3  
CC3  
CC3  
SCK = 0.1 V / 0.9 V  
CC  
SO = Open  
Current: Read Single / Dual / Quad 33 MHz (2)  
Current: Read Single / Dual / Quad 50 MHz (2)  
9/10.5/12  
SCK = 0.1 V / 0.9 V  
CC  
SO = Open  
7/8/9  
10/12/13.5  
18/22/25  
Current: Read Single / Dual / Quad 108 MHz  
(2)  
SCK = 0.1 V / 0.9 V  
CC  
SO = Open  
12/14/16  
Current: Write Status Registers  
Current Page Program  
Current Sector / Block Erase  
Current Chip Erase  
I
I
I
I
CS# = V  
CS# = V  
CS# = V  
CS# = V  
8
12  
25  
25  
25  
mA  
mA  
mA  
mA  
V
CC4  
CC5  
CC6  
CC7  
CC  
CC  
CC  
CC  
20  
20  
20  
Input Low Voltage  
V
-0.5  
V
x 0.2  
+ 0.4  
IL  
CC  
Input High Voltage  
V
V
V
x 0.7  
V
CC  
V
IH  
CC  
I
I
I
= 100 µA  
= 1.6 mA  
= –100 µA  
V
V
0.2  
0.4  
V
OL  
OL  
OH  
SS  
Output Low Voltage  
V
OL  
SS  
Output High Voltage  
V
– 0.2  
V
CC  
V
OH  
CC  
Notes:  
1. Tested on sample basis and specified through design and characterization data. T = 25°C, V = 3V.  
A
CC  
2. Checker Board Pattern.  
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5.3.1  
Active Power and Standby Power Modes  
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the  
device is disabled, but may still be in an Active Power mode until all program, erase, and write operations  
have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB  
.
5.4  
AC Measurement Conditions  
Figure 5.3 Test Setup  
Device  
Under  
Test  
CL  
Table 5.5 AC Measurement Conditions  
Symbol  
Parameter  
Min  
Max  
30  
Unit  
pF  
ns  
V
C
Load Capacitance  
Input Rise and Fall Times  
Input Pulse Voltage  
L
TR, TF  
2.4  
0.2 x V to 0.8 V  
CC  
CC  
Input Timing Ref Voltage  
0.5 V  
0.5 V  
V
CC  
CC  
Output Timing Ref  
Voltage  
V
Notes:  
1. Output High-Z is defined as the point where data is no longer driven.  
2. Input slew rate: 1.5 V/ns.  
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).  
Figure 5.4 Input, Output, and Timing Reference Levels  
Input Levels  
+ 0.4V  
Output Levels  
V
V
CC  
CC  
CC  
0.7 x V  
0.5 x V  
0.3 x V  
CC  
CC  
CC  
V
- 0.2V  
Timing Reference Level  
0.2V to 0.4V  
- 0.5V  
V
SS  
5.4.1  
Capacitance Characteristics  
Table 5.6 Capacitance  
Parameter  
Input Capacitance (applies to SCK, CS#)  
Output Capacitance (applies to All I/O)  
Test Conditions  
1 MHz  
Min  
Max  
8
Unit  
pF  
C
IN  
C
1 MHz  
8
pF  
OUT  
Notes:  
1. Sampled, not 100ꢀ tested.  
2. Test conditions T = 25°C, f = 1.0 MHz.  
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Table 5.7 Power-Up Timing and Voltage Levels  
5.5  
Power-Up Timing  
Spec  
Parameter  
Symbol  
Min  
Unit  
Max  
VCC (min) to CS# Low  
tVSL  
tPUW  
VWI  
tPD  
10  
1
µs  
ms  
V
Time Delay Before Write Command  
Write Inhibit Threshold Voltage  
VDD(low) Time  
10  
1.0  
10.0  
2.0  
µs  
Note:  
1. These parameters are characterized only.  
Figure 5.5 Power-Up Timing and Voltage Levels  
V
CC  
V
(max)  
CC  
Program, Erase, and Write instructions are ignored  
CS# must track V  
CC  
V
(min)  
CC  
t
VSL  
Read instructions  
allowed  
Device is fully  
accessible  
Reset  
State  
V
WI  
t
PUW  
Time  
Figure 5.6 Power-Down and Voltage Drop  
V
CC  
V
(max)  
CC  
No Device Access Allowed  
V
(min)  
CC  
t
Device Read  
Allowed  
VSL  
V
WI  
t
PD  
Time  
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5.6  
5.7  
Power On (Cold) Reset  
The device executes a Power-On-Reset (POR) process until a time delay of tPUW has elapsed after the  
moment that VCC rises above the VWI threshold. See Figure 5.5 on page 30, Figure 5.6 on page 30, and  
Table 5.7 on page 30. The device must not be selected (CS# to go high with VCC) until after (tVSL), i.e. no  
commands may be sent to the device until the end of tVSL  
.
AC Electrical Characteristics  
Table 5.8 Industrial Temperature Ranges (Sheet 1 of 2)  
Spec  
Typ  
Description  
Symbol  
Alt  
Unit  
Min  
Max  
Clock frequency for all SPI commands except for Read  
Data command (03h) and Fast Read command (0Bh)  
F
f
D.C.  
108  
MHz  
R
C
2.7V-3.6V V  
CC  
Clock frequency for Read Data command (03h)  
f
D.C.  
D.C.  
50  
MHz  
MHz  
R
Clock frequency for all Fast Read commands SIO and  
MIO  
f
108  
FR  
Clock Period  
P
9.25  
3.3  
4.3  
6
ns  
ns  
SCK  
Clock High, Low Time for f  
t
t
, t  
(1)  
(1)  
t
t
t
, t  
FR  
CLH CLL  
CH CL  
Clock High, Low Time for F  
, t  
, t  
CH CL  
ns  
R
CLH CLL  
Clock High, Low Time for f  
Clock Rise Time  
t
, t  
(1)  
, t  
CH CL  
ns  
R
CRLH CRLL  
t
t
(2)  
(2)  
t
0.1  
0.1  
5
V/ns  
V/ns  
ns  
CLCH  
CHCL  
CRT  
Clock Fall Time  
t
CFT  
CS# Active Setup Time relative to CLK  
CS# Not Active Hold Time relative to CLK  
Data In Setup Time  
t
t
t
CSS  
SLCH  
t
5
ns  
CHSL  
DVCH  
CHDX  
CHSH  
SHCH  
CSH  
t
t
2
ns  
SU  
HD  
Data In Hold Time  
t
t
t
t
5
ns  
CS# Active Hold Time relative to CLK  
CS# Not Active Setup Time relative to CLK  
CS# Deselect Time (for Array Read -> Array Read)  
t
5
ns  
CSS  
t
5
ns  
CSH  
CS1  
t
t
7
ns  
SHSL1  
40  
CS# Deselect Time (for Erase or Program -> Read  
Status Registers)  
Volatile Status Register Write Time  
t
t
ns  
SHSL2  
CS2  
CS3  
40  
CS# Deselect Time (for Erase or Program -> Suspend  
command)  
t
t
130  
ns  
SHSL3  
Output Disable Time  
t
(2)  
t
7
7
6
ns  
ns  
ns  
SHQZ  
DIS  
Clock Low to Output Valid, 30 pF, 2.7V - 3.6V  
Clock Low to Output Valid, 15 pF, 2.7V - 3.6V  
t
t
t
CLQV1  
V1  
V1  
t
t
CLQV1  
CLQV2  
Clock Low to Output Valid (for Read ID commands)  
2.7V - 3.6V  
t
8.5  
ns  
V2  
Output Hold Time  
t
t
t
2
5
5
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
CLQX  
HO  
HOLD# Active Setup Time relative to CLK  
HOLD# Active Hold Time relative to CLK  
HOLD# Not Active Setup Time relative to CLK  
HOLD# Not Active Hold Time relative to CLK  
HOLD# to Output Low-Z  
HLCH  
t
CHHH  
HHCH  
t
t
CHHL  
t
(2)  
(2)  
(3)  
(3)  
t
7
HHQX  
LZ  
HOLD# to Output High-Z  
t
t
12  
HLQZ  
WHSL  
SHWL  
HZ  
Write Protect Setup Time Before CS# Low  
Write Protect Hold Time After CS# High  
CS# High to Power-down Mode  
t
t
t
20  
WPS  
WPH  
t
100  
t
(2)  
3
3
DP  
CS# High to Standby Mode without Electronic Signature  
Read  
t
(2)  
(2)  
µs  
µs  
RES1  
CS# High to Standby Mode with Electronic Signature  
Read  
t
1.8  
RES2  
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Table 5.8 Industrial Temperature Ranges (Sheet 2 of 2)  
Spec  
Typ  
Description  
Write Status Registers Time  
Symbol  
Alt  
Unit  
Min  
Max  
300  
50  
t
50  
15  
ms  
µs  
µs  
ms  
ms  
ms  
s
W
Byte Program Time (First Byte) (4)(5)  
Additional Byte Program Time (After First Byte) (4)(5)  
Page Program Time (5)  
t
t
BP1  
BP2  
2.5  
0.7  
70  
12  
t
t
3
PP  
Sector Erase Time (4 kB) (5)  
450  
2000  
64  
SE  
Block Erase Time (64 kB) (5)  
t
500  
11.2  
BE2  
Chip Erase Time 16 Mb (5)  
t
CE  
Notes:  
1. Clock high + Clock low must be less than or equal to 1/f .  
C
2. Value guaranteed by design and / or characterization, not 100ꢀ tested in production.  
3. Only applicable as a constraint for a Write Status Registers command when Status Register Protect 0 (SRP0) bit is set to 1. Or WPSEL  
bit = 1.  
4. For multiple bytes after first byte within a page, t  
bytes programmed.  
= t  
+ t  
* N (typical) and t  
= t  
+ t * N (max), where N = number of  
BP2  
BPN  
BP1  
BP2  
BPN  
BP1  
5. All program and erase times are tested using a random data pattern.  
5.7.1  
Clock Timing  
Figure 5.7 Clock Timing  
P
SCK  
t
CH  
V
(min)  
IH  
V
CC / 2  
V
(max)  
IL  
t
t
CFT  
CRT  
t
CL  
5.7.2  
Input / Output Timing  
Figure 5.8 SPI Single Bit Input Timing  
tCS  
CS#  
tCSH  
tCSH  
tCSS  
tCSS  
SCK  
tSU  
tHD  
MSB IN  
SI  
LSB IN  
SO  
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Figure 5.9 SPI Single Bit Output Timing  
tCS  
CS#  
SCK  
SI  
tLZ  
tHO  
tV  
tDIS  
SO  
MSB OUT  
LSB OUT  
Figure 5.10 SPI MIO Timing  
tCS  
CS#  
tCSH  
tCSS  
tCSS  
tCSH  
SCLK  
IO  
tSU  
tHD  
MSB IN  
tLZ  
tHO  
tV  
LSB OUT  
tDIS  
LSB IN  
MSB OUT  
Figure 5.11 Hold Timing  
CS#  
SCLK  
tHLCH  
tCHHL  
tHHCH  
tHLCH  
tHHCH  
tCHHH  
tCHHL  
tCHHH  
HOLD#  
Hold Condition  
Standard Use  
Hold Condition  
Non-standard Use  
SI_or_IO_(during_input)  
tHZ  
tLZ  
B
tHZ  
tLZ  
SO_or_IO_(during_output)  
A
B
C
D
E
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Figure 5.12 WP# Input Timing  
CS#  
tWPS  
7
tWPH  
WP#  
SCLK  
SI  
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO  
Phase  
Write Status Registers Instruction  
Input Data  
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6. Physical Interface  
6.1  
6.1.1  
Connection Diagrams  
SOIC 8 / WSON 8  
Table 6.1 8-Connector Package, Top View  
Signal  
Lead  
Package Body  
Lead  
Signal  
CS#  
1
2
3
4
8
7
6
5
VCC  
SO / IO1  
HOLD# / IO3  
SCLK  
SOIC 8  
WSON 8  
WP# / IO2  
VSS  
SI / IO0  
6.1.2  
FAB024 24-Ball BGA  
Table 6.2 24-Ball BGA, 5x5 Ball Footprint (FAB024), Top View  
Ball Index  
1
(no ball)  
DNU  
DNU  
DNU  
NC  
2
NC  
3
NC  
4
RFU  
5
A
B
C
D
E
NC  
NC  
NC  
NC  
NC  
SCLK  
CS#  
VSS  
RFU  
SI / IO0  
NC  
VCC  
WP# / IO2  
HOLD# / IO3  
RFU  
SO / IO1  
NC  
6.1.3  
FAC024 24-Ball BGA Package  
Table 6.3 24-Ball BGA, 4x6 Ball Footprint (FAC024), Top View  
Ball Index  
1
2
NC  
3
NC  
4
A
B
C
D
E
F
NC  
RFU  
VCC  
DNU  
DNU  
DNU  
NC  
SCK  
CS#  
SO / IO1  
NC  
VSS  
RFU  
SI / IO0  
NC  
WP# / IO2  
HOLD# / IO3  
RFU  
NC  
NC  
NC  
NC  
Note:  
1. Signal connections are in the same relative positions as FAB024 BGA, allowing a single PCB footprint to use either package.  
6.1.4  
Special Handling Instructions for FBGA Packages  
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The  
package and / or data integrity may be compromised if the package body is exposed to temperatures above  
150°C for prolonged periods of time.  
November 6, 2013 S25FL116K_00_06  
S25FL116K  
35  
D a t a S h e e t ( P r e l i m i n a r y )  
6.2  
6.2.1  
Physical Diagrams  
SOA008 — 8-lead Plastic Small Outline Package (150-mils Body Width)  
NOTES:  
1.  
2.  
3.  
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.  
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.  
DIMENSION D DOES NOT INCLUDE MOLD FLASH,  
PROTRUSIONS OR GATE BURRS. MOLD FLASH,  
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm  
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION  
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1  
DIMENSIONS ARE DETERMINED AT DATUM H.  
4.  
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE  
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE  
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF  
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD  
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP  
AND BOTTOM OF THE PLASTIC BODY.  
5.  
6.  
DATUMS A AND B TO BE DETERMINED AT DATUM H.  
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR  
THE SPECIFIED PACKAGE LENGTH.  
7.  
8.  
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD  
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.  
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.  
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL  
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL  
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE  
LOWER RADIUS OF THE LEAD FOOT.  
9.  
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,  
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX  
AREA INDICATED.  
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED  
FROM THE SEATING PLANE.  
g1019 \ 16-038.3f \ 10.06.11  
36  
S25FL116K  
S25FL116K_00_06 November 6, 2013  
D a t a S h e e t ( P r e l i m i n a r y )  
6.2.2  
SOC008 — 8-lead Plastic Small Outline Package (208-mils Body Width)  
NOTES:  
1.  
2.  
3.  
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.  
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.  
PACKAGE SOC 008 (inches)  
SOC 008 (mm)  
JEDEC  
DIMENSION D DOES NOT INCLUDE MOLD FLASH,  
PROTRUSIONS OR GATE BURRS. MOLD FLASH,  
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm  
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION  
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1  
DIMENSIONS ARE DETERMINED AT DATUM H.  
SYMBOL  
MIN  
MAX  
0.085  
0.0098  
0.075  
0.019  
0.018  
MIN  
MAX  
2.159  
0.249  
1.91  
A
A1  
A2  
b
0.069  
0.002  
0.067  
0.014  
0.013  
1.753  
0.051  
1.70  
0.356  
0.330  
0.191  
0.152  
0.483  
0.457  
0.241  
0.203  
4.  
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE  
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE  
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF  
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD  
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP  
AND BOTTOM OF THE PLASTIC BODY.  
b1  
c
0.0075 0.0095  
0.006 0.008  
0.208 BSC  
c1  
D
5.283 BSC  
5.  
6.  
DATUMS A AND B TO BE DETERMINED AT DATUM H.  
E
0.315 BSC  
0.208 BSC  
.050 BSC  
8.001 BSC  
5.283 BSC  
1.27 BSC  
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR  
THE SPECIFIED PACKAGE LENGTH.  
E1  
e
7.  
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD  
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.  
L
0.020  
0.030  
0.508  
0.762  
8.  
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.  
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL  
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL  
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE  
LOWER RADIUS OF THE LEAD FOOT.  
L1  
L2  
N
.049 REF  
1.25 REF  
0.25 BSC  
8
.010 BSC  
8
θ
0˚  
5˚  
8˚  
15˚  
0˚  
0˚  
5˚  
8˚  
9.  
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,  
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX  
AREA INDICATED.  
θ1  
θ2  
15˚  
0˚  
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED  
FROM THE SEATING PLANE.  
3602 \ 16-038.03 \ 9.1.6  
November 6, 2013 S25FL116K_00_06  
S25FL116K  
37  
D a t a S h e e t ( P r e l i m i n a r y )  
6.2.3  
WND008 — 8-contact WSON 5x6  
NOTES:  
PACKAGE  
WND008  
1. DIMENSIONING AND TOLERANCING CONFORMS TO  
ASME Y14.5M - 1994.  
SYMBOL  
MIN  
NOM  
1.27 BSC.  
8
MAX  
NOTES  
e
N
2. ALL DIMENSIONS ARE IN MILLMETERS.  
3. N IS THE TOTAL NUMBER OF TERMINALS.  
3
5
ND  
L
4
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS  
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL  
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE  
OTHER END OF THE TERMINAL, THE DIMENSION “b”  
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.  
0.55  
0.35  
3.90  
3.30  
0.60  
0.65  
0.45  
4.10  
3.50  
b
0.40  
4
D2  
E2  
D
4.00  
3.40  
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.  
5.00 BSC  
6.00 BSC  
0.75  
6. MAX. PACKAGE WARPAGE IS 0.05mm.  
E
7. MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.  
A
0.70  
0.00  
0.80  
0.05  
8
9
PIN #1 ID ON TOP WILL BE LASER MARKED.  
A1  
K
0.02  
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED  
HEAT SINK SLUG AS WELL AS THE TERMINALS.  
0.20 MIN.  
g1071 \ 16-038.30 \ 02.22.12  
38  
S25FL116K  
S25FL116K_00_06 November 6, 2013  
D a t a S h e e t ( P r e l i m i n a r y )  
6.2.4  
FAB024 — 24-ball Ball Grid Array (8 x 6 mm) Package  
November 6, 2013 S25FL116K_00_06  
S25FL116K  
39  
D a t a S h e e t ( P r e l i m i n a r y )  
6.2.5  
FAC024 — 24-ball Ball Grid Array (8 x 6 mm) Package  
NOTES:  
PACKAGE  
JEDEC  
FAC024  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
D x E  
8.00 mm x 6.00 mm NOM  
PACKAGE  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
3. BALL POSITION DESIGNATION PER JEP95, SECTION  
4.3, SPP-010.  
SYMBOL  
MIN  
NOM  
---  
MAX  
NOTE  
A
A1  
A2  
D
---  
1.20  
---  
PROFILE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
0.25  
0.70  
---  
BALL HEIGHT  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
---  
0.90  
BODY THICKNESS  
BODY SIZE  
8.00 BSC.  
6.00 BSC.  
5.00 BSC.  
3.00 BSC.  
6
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
E
BODY SIZE  
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
MD  
ME  
N
4
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE  
CROWNS OF THE SOLDER BALLS.  
24  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
Øb  
e
0.35  
0.40  
0.45  
BALL DIAMETER  
1.00 BSC.  
0.5/0.5  
BALL PITCHL  
SD/ SE  
SOLDER BALL PLACEMENT  
DEPOPULATED SOLDER BALLS  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
J
PACKAGE OUTLINE TYPE  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.  
3642 F16-038.9 \ 09.10.09  
40  
S25FL116K  
S25FL116K_00_06 November 6, 2013  
D a t a S h e e t ( P r e l i m i n a r y )  
Software Interface  
This section discusses the features and behaviors most relevant to host system software that interacts with  
S25FL116K memory devices.  
7. Address Space Maps  
7.1  
Overview  
Many commands operate on the main flash memory array. Some commands operate on address spaces  
separate from the main flash array. Each separate address space uses the full 24-bit address but may only  
define a small portion of the available address space.  
7.2  
Flash Memory Array  
The main flash array is divided into erase units called sectors. The sectors are uniform 4 kbytes in size.  
Table 7.1 S25FL116K Main Memory Address Map  
Address Range  
Sector Size (kbyte)  
Sector Count  
Sector Range  
Notes  
(Byte Address)  
000000h-000FFFh  
:
SA0  
:
Sector Starting Address  
—
4
512  
Sector Ending Address  
SA511  
1FF000h-1FFFFFh  
Note:  
This is condensed table that use a couple of sectors as references. There are address ranges that are not explicitly listed. All 4-kB sectors  
have the pattern XXX000h-XXXFFFh.  
7.3  
Security Registers  
The S25FL116K provides four 256-byte Security Registers. Each register can be used to store information  
that can be permanently protected by programming One Time Programmable (OTP) lock bits in Status  
Register-2.  
Register 0 is used by Spansion to store and protect the Serial Flash Discoverable Parameters (SFDP)  
information that is also accessed by the Read SFDP command.  
The three additional Security Registers can be erased, programmed, and protected individually. These  
registers may be used by system manufacturers to store and permanently protect security or other important  
information separate from the main memory array.  
Table 7.2 Security Register Addresses  
Security Register  
Address  
0
000000h - 0000FF  
(SFDP)  
1
2
3
001000h - 0010FF  
002000h - 0020FF  
003000h - 0030FF  
7.3.1  
Security Register 0 - Serial Flash Discoverable Parameters (SFDP)  
The S25FL116K features a 256-Byte Serial Flash Discoverable Parameter (SFDP) space, located in Security  
Register-0, that contains information about the device operational capabilities such as available commands,  
timing and other features. The SFDP parameters are stored in one or more Parameter Identification (PID)  
tables. Currently only one PID table is specified but more may be added in the future. The Read SFDP  
Register command reads the contents of Security Register-0 and is compatible with the JEDEC JESD216  
SFDP standard.  
November 6, 2013 S25FL116K_00_06  
S25FL116K  
41  
D a t a S h e e t ( P r e l i m i n a r y )  
Table 7.3 Serial Flash Discoverable Parameter Definition Table (Sheet 1 of 2)  
Byte  
DWORD  
Data  
Description  
Comment  
Address  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
10h  
11h  
12h  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
1Fh  
53h  
46h  
44h  
50h  
00h  
01h  
02h  
FFh  
00h  
00h  
01h  
09h  
80h  
00h  
00h  
FFh  
SFDP Signature  
SFDP Signature  
SFDP Signature  
SFDP Signature  
SFDP Header 1  
SFDP Signature = 50444653h  
SFDP Minor Revisions  
SFDP revision 1.0  
SFDP Major Revisions  
SFDP Header 2  
Number of Parameter Headers (NPH)  
Reserved  
3 Parameter Headers  
PID(0): Parameter ID (1)  
Mandatory JEDEC Parameter = 00h  
PID(0): JEDEC Parameter Minor Revisions  
PID(0): JEDEC Parameter Major Revisions  
PID(0): JEDEC Parameter Length  
PID(0): Address of Parameter Table (A7-A0)  
PID(0): Address of Parameter Table (A15-A8)  
PID(0): Address of Parameter Table (A23-A16)  
Reserved  
Parameter  
Header 1  
JEDEC Parameter Version 1.0  
as published in JESD216 April 2011  
9 Dwords  
PID(0) Table Address = 000080h  
Parameter  
Header 2  
EFh PID(1): Parameter ID  
PID(1): Parameter Minor Revisions  
Legacy Parameter ID = EFh  
00h  
01h  
04h  
80h  
00h  
00h  
FFh  
01h  
00h  
01h  
00h  
A4h  
00h  
00h  
FFh  
Parameter  
Header 3  
Serial Flash Basics Version 1.0  
PID(1): Parameter Major Revisions  
PID(1): Parameter Length  
4 Dwords  
PID(1): Address of Parameter Table (A7-A0)  
PID(1): Address of Parameter Table (A15-A8)  
PID(1): Address of Parameter Table (A23-A16)  
Reserved  
PID(1) Table Address = 000080h  
Same data as first 4 words of JEDEC  
Parameter  
Parameter  
Header 4  
PID(2): Parameter ID  
Spansion Manufacturer ID = 01h  
PID(2): Serial Flash Properties Minor Revisions  
PID(2): Serial Flash Properties Major Revisions  
PID(2): Parameter Length  
Parameter  
Header 5  
Spansion Serial Flash Properties  
Revision 1.0  
00h = Not implemented  
PID(2): Address of Parameter Table (A7-A0)  
PID(2): Address of Parameter Table (A15-A8)  
PID(2): Address of Parameter Table (A23-A16)  
Reserved  
PID(2) Table Address = 0000A4h  
Parameter  
Header 6  
20h to  
7Fh  
Reserved  
FFh  
Reserved  
Bits 7:5 = unused = 111b  
Bits 4:3 = Target flash has nonvolatile status bit and  
does not require status register to be written on every  
power on to allow writes and erases = 00b  
Bit 2 = Program Buffer > 64 bytes = 1  
Bits 1:0 = Uniform 4-kB erase = 01b  
Start of SFDP JEDEC parameter  
80h  
81h  
E5h  
20h  
4 kbyte Erase Opcode  
JEDEC Flash  
Parameters 1  
Bit[7]  
Bit[6]  
Bit[5]  
Bit[4]  
Bit[3]  
=
=
=
=
=
1
1
1
1
0
Reserved  
Supports Quad Out Read (1-1-4)  
Supports Quad I/O Read (1-4-4)  
Supports Dual I/O Read (1-2-2)  
Dual Transfer Rate not Supported  
82h  
83h  
F1h  
FFh  
Read Command Support  
Bit[2:1] = 00 3-byte / 24-bit Addressing  
Bit[0] Supports Single Input Dual Output  
=
1
Reserved  
42  
S25FL116K  
S25FL116K_00_06 November 6, 2013  
D a t a S h e e t ( P r e l i m i n a r y )  
Table 7.3 Serial Flash Discoverable Parameter Definition Table (Sheet 2 of 2)  
Byte  
Address  
DWORD  
Data  
Description  
Comment  
84h  
FFh  
FFh  
FFh  
85h  
16 Megabits = 00FFFFFFh  
32 Megabits = 01FFFFFFh  
64 Megabits = 02FFFFFFh  
JEDEC Flash  
Parameters 2  
86h  
Flash Size in Bits  
00h /  
01h /  
02h  
87h  
Bit[7:5] = 010  
Bit[4:0] = 00100 4 Dummy cycles are needed  
2 cycles of Mode Bits are needed  
88h  
89h  
8Ah  
8Bh  
8Ch  
8Dh  
8Eh  
44h  
Fast Read Quad I/O Default Setting  
Fast Read Quad Output Default Setting  
Fast Read Dual Output Default Setting  
Fast Read Dual I/O Default Setting  
EBh (1-4-4) Quad I/O Fast Read Opcode  
JEDEC Flash  
Parameters 3  
Bit[7:5] = 000  
Bit[4:0] = 01000 8 Dummy cycles are needed  
No Mode cycles are needed  
08h  
6Bh  
08h  
3Bh  
80h  
(1-1-4) Quad Output Fast Read Opcode  
Bit[7:5] = 000  
Bit[4:0] = 01000 8 Dummy cycles are needed  
No Mode cycles are needed  
(1-1-2) Dual Output Fast Read Opcode  
JEDEC Flash  
Parameters 4  
Bit[7:5] = 100  
Bit[4:0] = 00000 No Dummy cycles are needed  
4 Mode cycles are needed  
8Fh  
90h  
91h  
92h  
93h  
94h  
95h  
BBh (1-2-2) Dual I/O Fast Read Opcode  
EEh  
Bit[31:5]= 1  
Reserved  
FFh  
FFh  
FFh  
FFh  
FFh  
JEDEC Flash  
Parameters 5  
Bit[4]  
Bit[3:1] =  
Bit[0]  
=
0
1
0
(4-4-4) Quad All Read Not Supported  
Reserved  
(2-2-2) Dual All Read Not Supported  
Uniform Width Protocol Support  
=
Reserved  
Reserved  
JEDEC Flash  
Parameters 6  
Dual All Read Parameters  
Reserved  
Bit[7:5] = 111  
Bit[4:0] = 11111 Dummy cycles needed  
Mode cycles needed  
96h  
FFh  
97h  
98h  
99h  
FFh  
FFh  
FFh  
(2-2-2) Dual All Read Command not supported = FFh  
Reserved  
Reserved  
JEDEC Flash  
Parameters 7  
Quad All Read Parameters  
Reserved  
Bit[7:5] = 111  
Mode cycles needed  
9Ah  
FFh  
FFh  
Bit[4:0] = 11111 Dummy cycles needed  
9Bh  
9Ch  
9Dh  
9Eh  
9Fh  
A0h  
A1h  
A2h  
A3h  
(4-4-4) Quad All Read Command not supported = FFh  
0Ch Sector type 1 size 2N Bytes = 4 kB = 0Ch  
20h  
10h  
Sector type 1 instruction  
JEDEC Flash  
Parameters 8  
Sector type 2 size 2N Bytes = 64 kB = 10h  
D8h Sector type 2 instruction  
Sector / Block  
Architecture  
00h  
FFh  
00h  
FFh  
Sector type 3 size 2N Bytes = not supported = 00h  
Sector type 3 instruction = not supported = FFh  
Sector type 4 size 2N Bytes = not supported = 00h  
Sector type 4 instruction = not supported = FFh  
JEDEC Flash  
Parameters 9  
A4h to  
F7h  
FFh  
FFh  
Reserved  
Unique ID  
F8h to  
FFh  
Unique ID  
Note:  
1. PID(x) = Parameter Identification Table (x).  
November 6, 2013 S25FL116K_00_06  
S25FL116K  
43  
D a t a S h e e t ( P r e l i m i n a r y )  
7.4  
Status Registers  
Status Register-1 (SR1) and Status Register-2 (SR2) can be used to provide status on the availability of the  
flash memory array, if the device is write enabled or disabled, the state of write protection, Quad SPI setting,  
and Security Register lock status, and Erase / Program Suspend status.  
SR1 and SR2 contain non-volatile bits in locations SR1[7:2] and SR2[6:0] that control sector protection, OTP  
Register Protection, Status Register Protection, and Quad mode. Bit locations SR2[7], SR1[1], and SR1[0]  
are read only volatile bits for write enable, and busy status; these are updated by the memory control logic.  
The SR1[1] write enable bit is set only by the Write Enable (06h) command and cleared by the memory  
control logic when an embedded operation is completed.  
Write access to the non-volatile Status Register bits is controlled by the state of the non-volatile Status  
Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable command (06h) preceding a Write  
Status Registers command, and while Quad mode is not enabled, the WP# pin.  
A volatile version of bits SR2[6], SR2[1], and SR1[7:2] that control sector protection and Quad Mode are used  
to control the behavior of these features after power up. During power up these volatile bits are loaded from  
the non-volatile version of the Status Register bits. The Write Enable for Volatile Status Register (50h)  
command can be used to write these volatile bits when the command is followed by a Write Status Registers  
(01h) command. This gives more flexibility to change the system configuration and memory protection  
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the  
Status Register non-volatile bits.  
Write access to the volatile SR1 and SR2 Status Register bits is controlled by the state of the non-volatile  
Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable for Volatile Status Register  
command (50h) preceding a Write Status Registers command, and while Quad mode is not enabled, the  
WP# pin.  
Status Register-3 (SR3) is used to configure and provide status on the variable read latency, and Quad IO  
wrapped read features.  
Write access to the volatile SR3 Status Register bits is controlled by Write Enable for Volatile Status Register  
command (50h) preceding a Write Status Register command. The SRP bits do not protect SR3.  
Table 7.4 Status Register-1 (SR1)  
Field  
Name  
Bits  
Function  
Type  
Default State  
Description  
0 = WP# input has no effect or Power Supply Lock Down  
mode  
Status  
Register  
Protect 0  
7
SRP0  
0
1 = WP# input can protect the Status Register or OTP  
Lock Down  
See Table 7.9 on page 49.  
0 = BP2-BP0 protect 64-kB blocks  
Sector / Block  
Protect  
6
5
SEC  
TB  
0
0
1 = BP2-BP0 protect 4-kB sectors  
See Table 7.7 and Table 7.8 for protection ranges.  
Non-volatile and  
volatile versions  
0 = BP2-BP0 protect from the Top down  
Top / Bottom  
Protect  
1 = BP2-BP0 protect from the Bottom up  
See Table 7.7 and Table 7.8 for protection ranges  
4
3
2
BP2  
BP1  
BP0  
0
0
0
000b = No protection  
See Table 7.7 and Table 7.8 for protection ranges.  
Block Protect  
Bits  
0 = Not Write Enabled, no embedded operation can start  
1 = Write Enabled, embedded operation can start  
Write Enable  
Latch  
1
0
WEL  
Volatile, Read only  
Volatile, Read only  
0
0
Embedded  
Operation  
Status  
0 = Not Busy, no embedded operation in progress  
1 = Busy, embedded operation in progress  
BUSY  
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Table 7.5 Status Register-2 (SR2)  
Field  
Name  
Bits  
Function  
Type  
Default State  
Description  
0 = Erase / Program not suspended  
1 = Erase / Program suspended  
Suspend  
Status  
7
SUS  
CMP  
Volatile, Read Only  
0
0 = Normal Protection Map  
Complement  
Protect  
Non-volatile and  
volatile versions  
6
0
1 = Inverted Protection Map  
See Table 7.7 and Table 7.8 for protection ranges.  
5
4
3
LB3  
LB2  
LB1  
0
0
0
OTP Lock Bits 3:0 for Security Registers 3:0  
0 = Security Register not protected  
Security  
Register  
Lock Bits  
1 = Security Register protected  
OTP  
Security register 0 contains the Serial Flash  
Discoverable Parameters and is always programmed  
and locked by Spansion.  
2
LB0 (1)  
1
0 = Quad Mode Not Enabled, the WP# pin and HOLD#  
are enabled  
1
QE  
Quad Enable  
0
1 = Quad Mode Enabled, the IO2 and IO3 pins are  
enabled, and WP# and HOLD# functions are disabled  
Non-volatile and  
volatile versions  
0 = SRP1 selects whether WP# input has effect on  
protection of the status register  
Status  
Register  
Protect 1  
0
SRP1  
0
1 = SRP1 selects Power Supply Lock Down or OTP Lock  
Down mode  
See Table 7.9 on page 49.  
Note:  
1. LB0 value should be considered don't care for read. This bit is set to 1.  
Table 7.6 Status Register-3 (SR3)  
Field  
Name  
Bits  
Function  
Type  
Default State  
Description  
7
6
RFU  
W6  
Reserved  
0
1
Reserved for Future Use  
00 = 8-byte wrap. Data read starts at the initial address  
and wraps within an aligned 8-byte boundary  
01 = 16-byte wrap. Data read starts at the initial address  
and wraps within an aligned 16-byte boundary.  
10 = 32-byte wrap. Data read starts at the initial address  
and wraps within an aligned 32-byte boundary.  
11 = 64-byte wrap. Data read starts at the initial address  
and wraps within an aligned 64-byte boundary.  
Burst Wrap  
Length  
5
W5  
W4  
1
Volatile  
0 = Wrap Enabled  
1 = Wrap Disabled  
Burst Wrap  
Enable  
4
1
3
2
1
0
0
0
0
0
Defines the number of read latency cycles in Fast Read,  
Dual Out, Quad Out, Dual IO, and Quad IO commands.  
Binary values for 1 to 15 latency cycles. A value of zero  
disables the variable latency mode.  
Latency  
Control  
(LC)  
Variable Read  
Latency  
Control  
7.4.1  
BUSY  
BUSY is a read only bit in the Status Register (SR1[0]) that is set to a 1 state when the device is executing a  
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Registers or Erase / Program Security  
Register command. During this time the device will ignore further commands except for the Read Status  
Register and Erase / Program Suspend command (see tW, tPP, tSE, tBE, and tCE in Section 5.7, AC Electrical  
Characteristics on page 31). When the program, erase or the write status / security register command has  
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further commands.  
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7.4.2  
Write Enable Latch (WEL)  
Write Enable Latch (WEL) is a read only bit in the Status Register (SR1[1]) that is set to 1 after executing a  
Write Enable Command. The WEL status bit is cleared to 0 when the device is write disabled. A write disable  
state occurs upon power-up or after any of the following commands: Write Disable, Page Program, Sector  
Erase, Block Erase, Chip Erase, Write Status Registers, Erase Security Register and Program Security  
Register. The WEL status bit is cleared to 0 even when a program or erase operation is prevented by the  
block protection bits. The WEL status bit is also cleared to 0 when a program or erase operation is  
suspended. The WEL status bit is set to 1 when a program or erase operation is resumed.  
7.4.3  
7.4.4  
Block Protect Bits (BP2, BP1, BP0)  
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that  
provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers  
Command (see tW in Section 5.7, AC Electrical Characteristics on page 31). All, none or a portion of the  
memory array can be protected from Program and Erase commands (see Section 7.4.7, Block Protection  
Maps on page 47). The factory default setting for the Block Protection Bits is 0 (none of the array is  
protected.)  
Top / Bottom Block Protect (TB)  
The non-volatile Top / Bottom bit (TB SR1[5]) controls if the Block Protect Bits (BP2, BP1, BP0) protect from  
the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 7.4.7, Block Protection Maps  
on page 47. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers  
Command depending on the state of the SRP0, SRP1 and WEL bits.  
7.4.5  
7.4.6  
Sector / Block Protect (SEC)  
The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0)  
protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the  
array as shown in Section 7.4.7, Block Protection Maps on page 47. The default setting is SEC=0.  
Complement Protect (CMP)  
The Complement Protect bit (CMP SR2[6]) is a non-volatile read / write bit in the Status Register (SR2[6]). It  
is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection.  
Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For  
instance, when CMP=0, a top 4-kB sector can be protected while the rest of the array is not; when CMP=1,  
the top 4-kB sector will become unprotected while the rest of the array become read-only. Please refer to  
Section 7.4.7, Block Protection Maps on page 47 for details. The default setting is CMP=0.  
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7.4.7  
Block Protection Maps  
Table 7.7 FL116K Block Protection (CMP = 0)  
Status Register (1)  
S25FL116K (16 Mbit) Block Protection (CMP=0) (2)  
Protected  
SEC  
TB  
BP2  
BP1  
BP0  
Protected Block(s)  
Protected Addresses  
Protected Portion  
Density  
None  
64 kB  
128 kB  
256 kB  
512 kB  
1 MB  
X
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
X
1
0
1
X
1
0
1
X
None  
None  
None  
31  
1F0000h – 1FFFFFh  
1E0000h – 1FFFFFh  
1C0000h – 1FFFFFh  
180000h – 1FFFFFh  
100000h – 1FFFFFh  
000000h – 00FFFFh  
000000h – 01FFFFh  
000000h – 03FFFFh  
000000h – 07FFFFh  
000000h – 0FFFFFh  
000000h – 1FFFFFh  
1FF000h – 1FFFFFh  
1FE000h – 1FFFFFh  
1FC000h – 1FFFFFh  
1F8000h – 1FFFFFh  
000000h – 000FFFh  
000000h – 001FFFh  
000000h – 003FFFh  
000000h – 007FFFh  
Upper 1/32  
Upper 1/16  
Upper 1/8  
Upper 1/4  
Upper 1/2  
Lower 1/32  
Lower 1/16  
Lower 1/8  
Lower 1/4  
Lower 1/2  
All  
30 and 31  
28 thru 31  
24 thru 31  
16 thru 31  
0
64 kB  
128 kB  
256 kB  
512 kB  
1 MB  
0 and 1  
0 thru 3  
0 thru 7  
0 thru 15  
0 thru 31  
2 MB  
31  
31  
31  
31  
0
4 kB  
Upper 1/512  
Upper 1/256  
Upper 1/128  
Upper 1/64  
Lower 1/512  
Lower 1/256  
Lower 1/128  
Lower 1/64  
8 kB  
16 kB  
32 kB  
4 kB  
0
8 kB  
0
16 kB  
32 kB  
0
Notes:  
1. X = don’t care.  
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.  
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Table 7.8 FL116K Block Protection (CMP = 1)  
Status Register (1)  
S25FL116K (16 Mbit) Block Protection (CMP=1) (2)  
Protected  
Density  
SEC  
TB  
BP2  
BP1  
BP0  
Protected Block(s)  
Protected Addresses  
Protected Portion  
X
X
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
X
1
0
1
X
1
0
1
X
0 thru 31  
0 thru 30  
0 thru 29  
0 thru 27  
0 thru 23  
0 thru 15  
1 thru 31  
2 and 31  
4 thru 31  
8 thru 31  
16 thru 31  
None  
000000h – 1FFFFFh  
000000h – 1EFFFFh  
000000h – 1DFFFFh  
000000h – 1BFFFFh  
000000h – 17FFFFh  
000000h – 0FFFFFh  
010000h – 1FFFFFh  
020000h – 1FFFFFh  
040000h – 1FFFFFh  
080000h – 1FFFFFh  
100000h – 1FFFFFh  
None  
All  
All  
0
1,984 kB  
1,920 kB  
1,792 kB  
1,536 kB  
1 MB  
Lower 31/32  
Lower 15/16  
Lower 7/8  
0
0
0
Lower 3/4  
0
Lower 1/2  
0
1,984 kB  
1,920 kB  
1,792 kB  
1,536 kB  
1 MB  
Upper 31/32  
Upper 15/16  
Upper 7/8  
0
0
0
Upper 3/4  
0
Upper 1/2  
X
None  
None  
1
0 thru 31  
0 thru 31  
0 thru 31  
0 thru 31  
0 thru 31  
0 thru 31  
0 thru 31  
0 thru 31  
000000h – 1FEFFFh  
000000h – 1FDFFFh  
000000h – 1FBFFFh  
000000h – 1F7FFFh  
001000h – 1FFFFFh  
002000h – 1FFFFFh  
004000h – 1FFFFFh  
008000h – 1FFFFFh  
2,044 kB  
2,040 kB  
2,032 kB  
2,016 kB  
2,044 kB  
2,040 kB  
2,032 kB  
2,016 kB  
Lower 511/512  
Lower 255/256  
Lower 127/128  
Lower 63/64  
Upper 511/512  
Upper 255/256  
Upper 127/128  
Upper 63/64  
1
1
1
1
1
1
1
Notes:  
1. X = don’t care.  
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.  
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7.4.8  
Status Register Protect (SRP1, SRP0)  
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read / write bits in the Status Register  
(SR2[0] and SR1[7]). The SRP bits control the method of write protection: software protection, hardware  
protection, power supply lock-down, or one time programmable (OTP) protection.  
Table 7.9 Status Register Protection Bits  
SRP1  
SRP0  
WP#  
Status Register  
Description  
WP# pin has no control. SR1 and SR2 can be written to after a  
Write Enable command, WEL=1. [Factory Default]  
0
0
X
Software Protection  
When WP# pin is low the SR1 and SR2 are locked and can not  
be written.  
0
0
1
1
0
1
Hardware Protected  
When WP# pin is high SR1 and SR2 are unlocked and can be  
written to after a Write Enable command, WEL=1.  
Hardware Unprotected  
Power Supply Lock-  
Down  
SR1 and SR2 are protected and can not be written to again until  
the next power-down, power-up cycle. (1)  
1
1
0
1
X
X
One Time Program (2) SR1 and SR2 are permanently protected and can not be written.  
Notes:  
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.  
2. The One Time Program feature is available upon special order. Please contact Spansion for details.  
3. Busy, WEL, and SUS (SR1[1:0] and SR2[7]) are volatile read only status bits that are never affected by the Write Status Registers  
command.  
4. The non-volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits and the OTP LB3-LB0 bits are  
not writable when protected by the SRP bits and WP# as shown in the table. The non-volatile version of these Status Register bits are  
selected for writing when the Write Enable (06h) command precedes the Write Status Registers (01h) command.  
5. The volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits are not writable when protected by  
the SRP bits and WP# as shown in the table. The volatile version of these Status Register bits are selected for writing when the Write  
Enable for volatile Status Register (50h) command precedes the Write Status Registers (01h) command. There is no volatile version of  
the LB3-LB0 bits and these bits are not affected by a volatile Write Status Registers command.  
6. The volatile SR3 bits are not protected by the SRP bits and may be written at any time by volatile (50h) Write Enable command preceding  
the Write Status Registers (01h) command.  
7.4.9  
Erase / Program Suspend Status (SUS)  
The Suspend Status bit is a read only bit in the status register (SR2[7]) that is set to 1 after executing an  
Erase / Program Suspend (75h) command. The SUS status bit is cleared to 0 by Erase / Program Resume  
(7Ah) command as well as a power-down, power-up cycle.  
7.4.10  
Security Register Lock Bits (LB3, LB2, LB1, LB0)  
The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in  
Status Register (SR2[5:2]) that provide the write protect control and status to the Security Registers. The  
default state of LB[3:1] is 0, Security Registers 1 to 3 are unlocked. LB[3:1] can be set to 1 individually using  
the Write Status Registers command. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the  
corresponding 256-byte Security Register will become read-only permanently.  
Security Register 0 is programmed with the SFDP parameters and LB0 is programmed to 1 by Spansion.  
7.4.11  
Quad Enable (QE)  
The Quad Enable (QE) bit is a non-volatile read / write bit in the Status Register (SR2[1]) that allows Quad  
SPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# are enabled.  
When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# functions are  
disabled.  
Note: If the WP# or HOLD# pins are tied directly to the power supply or ground during standard SPI or Dual  
SPI operation, the QE bit should never be set to a 1.  
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7.4.12  
Latency Control (LC)  
Status Register-3 provides bits (SR3[3:0]) to select the number of read latency cycles used in each Fast Read  
command. The Read Data command is not affected by the latency code. The binary value of this field selects  
from 1 to 15 latency cycles. The zero value selects the legacy number of latency cycles used in prior  
generation FL-K family devices. The default is 0 cycles to provide backward compatibility to legacy devices.  
The Latency Control bits may be set to select a number of read cycles optimized for the frequency in use. If  
the number of latency cycles is not sufficient for the operating frequency, invalid data will be read.  
Table 7.10 Latency Cycles Versus Frequency  
Read Command Maximum Frequency (MHz)  
Latency Control  
FAST READ  
DUAL OUTPUT  
DUAL I/O  
QUAD OUTPUT  
QUAD I/O  
0
108  
108  
88  
108  
78  
(legacy read latency)  
(8 dummy)  
(8 dummy)  
(4 mode, 0 dummy)  
(8 dummy)  
(2 mode, 4 dummy)  
1
50  
50  
94  
43  
56  
49  
59  
2
95  
85  
105  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
3
105  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
95  
70  
69  
4
105  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
108  
83  
78  
5
94  
86  
6
105  
108  
108  
108  
108  
108  
108  
108  
108  
108  
95  
7
105  
108  
108  
108  
108  
108  
108  
108  
108  
8
9
10  
11  
12  
13  
14  
15  
Notes:  
1. SCK frequency > 108 MHz SIO, 108 MHz DIO, or 108 MHz QIO is not supported by this family of devices.  
2. The Dual I/O and Quad I/O command protocols include Continuous Read Mode bits following the address. The clock cycles for these bits  
are not counted as part of the latency cycles shown in the table. Example: the legacy Dual I/O command has 4 Continuous Read Mode  
bits following the address and no additional dummy cycles. Therefore, the legacy Dual I/O command without additional read latency is  
supported only up to the frequency shown in the table for a read latency of 0 cycles. By increasing the variable read latency the frequency  
of the Dual I/O command can be increased to allow operation up to the maximum supported 108 MHz DIO frequency.  
7.4.13  
7.4.14  
Burst Wrap Enable (W4)  
Status Register-3 provides a bit (SR3[4]) to enable a read with wrap option for the Quad I/O Read command.  
When SR3[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed. When  
SR3[4]=0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes will be  
read starting at the byte address provided by the Quad I/O Read command and wrapping around at the group  
alignment boundary.  
Burst Wrap Length (W6, W5)  
Status Register-3 provides bits (SR3[1:0]) to select the alignment boundary at which reading will wrap to  
perform a cache line fill. Reading begins at the initial byte address of a Fast Read Quad IO command, then  
sequential bytes are read until the selected boundary is reached. Reading then wraps to the beginning of the  
selected boundary. This enables critical word first cache line refills. The wrap point can be aligned on 8-, 16-,  
32-, or 64-byte boundaries.  
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7.5  
7.5.1  
Device Identification  
Legacy Device Identification Commands  
Three legacy commands are supported to access device identification that can indicate the manufacturer,  
device type, and capacity (density). The returned data bytes provide the information as shown in Table 7.11.  
Table 7.11 Device Identification  
Device OPN  
Instruction  
ABh  
Data 1  
Data 2  
Data 3  
Device ID = 14h  
-
-
-
S25FL116K  
90h  
Manufacturer ID = 01h Device ID = 14h  
Manufacturer ID = 01h Device Type = 40h  
9Fh  
Capacity = 15h  
Note:  
1. The 90h instruction is followed by an address. Address = 0 selects Manufacturer ID as the first returned data as shown in the table.  
Address = 1 selects Device ID as the first returned data followed by Manufacturer ID.  
7.5.2  
Serial Flash Discoverable Parameters (SFDP)  
A Read SFDP (5Ah) command to read a JEDEC standard (JESD216) defined device information structure is  
supported. The information is stored in Security Register 0 and described in Security Register 0 - Serial Flash  
Discoverable Parameters (SFDP) on page 41.  
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8. Functional Description  
8.1  
8.1.1  
SPI Operations  
Standard SPI Commands  
The S25FL116K is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),  
Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Standard SPI commands use the SI  
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The SO  
output pin is used to read data or status from the device on the falling edge CLK.  
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode  
3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being  
transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of  
CS#. For Mode 3, the CLK signal is normally high on the falling and rising edges of CS#.  
8.1.2  
8.1.3  
Dual SPI Commands  
The S25FL116K supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read  
Dual I/O (BBh)” commands. These commands allow data to be transferred to or from the device at two to  
three times the rate of ordinary serial flash devices. The Dual SPI Read commands are ideal for quickly  
downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly  
from the SPI bus (XIP). When using Dual SPI commands, the SI and SO pins become bidirectional I/O pins:  
IO0 and IO1.  
Quad SPI Commands  
The S25FL116K supports Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, and “Fast  
Read Quad I/O (EBh)” commands. These commands allow data to be transferred to or from the device four to  
six times the rate of ordinary serial flash. The Quad Read commands offer a significant improvement in  
continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from  
the SPI bus (XIP). When using Quad SPI commands the SI and SO pins become bidirectional IO0 and IO1,  
and the WP# and HOLD# pins become IO2 and IO3 respectively. Quad SPI commands require the  
non-volatile or volatile Quad Enable bit (QE) in Status Register-2 to be set.  
8.1.4  
Hold Function  
For Standard SPI and Dual SPI operations, the HOLD# (IO3) signal allows the device interface operation to  
be paused while it is actively selected (when CS# is low). The Hold function may be useful in cases where the  
SPI data and clock signals are shared with other devices. For example, if the page buffer is only partially  
written when a priority interrupt requires use of the SPI bus, the Hold function can save the state of the  
interface and the data in the buffer so programming command can resume where it left off once the bus is  
available again. The Hold function is only available for standard SPI and Dual SPI operation, not during Quad  
SPI.  
To initiate a Hold condition, the device must be selected with CS# low. A Hold condition will activate on the  
falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold  
condition will activate after the next falling edge of CLK. The Hold condition will terminate on the rising edge of  
the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold condition will  
terminate after the next falling edge of CLK. During a Hold condition, the Serial Data Output, (SO) or IO0 and  
IO1, are high impedance and Serial Data Input, (SI) or IO0 and IO1, and Serial Clock (CLK) are ignored. The  
Chip Select (CS#) signal should be kept active (low) for the full duration of the Hold operation to avoid  
resetting the internal logic state of the device.  
8.2  
Write Protection  
Applications that use non-volatile memory must take into consideration the possibility of noise and other  
adverse system conditions that may compromise data integrity. To address this concern, the S25FL116K  
provides several means to protect the data from inadvertent program or erase.  
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8.2.1  
Write Protect Features  
Device resets when VCC is below threshold  
Time delay write disable after Power-Up  
Write enable / disable commands and automatic write disable after erase or program  
Command length protection  
– All commands that Write, Program or Erase must complete on a byte boundary (CS# driven high after  
a full 8 bits have been clocked) otherwise the command will be ignored  
Software and Hardware write protection using Status Register control  
– WP# input protection  
– Lock Down write protection until next power-up  
– One Time Program (OTP) write protection  
Write Protection using the Deep Power-down command  
Upon power-up or at power-down, the S25FL116K will maintain a reset condition while VCC is below the  
threshold value of VWI, (see Figure 5.5, Power-Up Timing and Voltage Levels on page 30). While reset, all  
operations are disabled and no commands are recognized. During power-up and after the VCC voltage  
exceeds VWI, all program and erase related commands are further disabled for a time delay of tPUW. This  
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status  
Registers commands. Note that the chip select pin (CS#) must track the VCC supply level at power-up until  
the VCC-min level and tVSL time delay is reached. If needed a pull-up resistor on CS# can be used to  
accomplish this.  
After power-up the device is automatically placed in a write-disabled state with the Status Register Write  
Enable Latch (WEL) set to a 0. A Write Enable command must be issued before a Page Program, Sector  
Erase, Block Erase, Chip Erase or Write Status Registers command will be accepted. After completing a  
program, erase or write command the Write Enable Latch (WEL) is automatically cleared to a write-disabled  
state of 0.  
Software controlled main flash array write protection is facilitated using the Write Status Registers command  
to write the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0)  
bits.  
The BP method allows a portion as small as 4-kB sector or the entire memory array to be configured as read  
only. Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be enabled or  
disabled under hardware control. See Status Registers on page 44. for further information.  
Additionally, the Deep-Power-Down (DPD) command offers an alternative means of data protection as all  
commands are ignored during the DPD state, except for the Release from Deep-Power-Down (RES ABh)  
command. Thus, preventing any program or erase during the DPD state.  
8.3  
Status Registers  
The Read and Write Status Registers commands can be used to provide status and control of the flash  
memory device.  
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9. Commands  
The command set of the S25FL116K is fully controlled through the SPI bus (see Table 9.1 to Table 9.3  
on page 55). Commands are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked  
into the SI input provides the instruction code. Data on the SI input is sampled on the rising edge of clock with  
most significant bit (MSB) first.  
Commands vary in length from a single byte to several bytes. Each command begins with an instruction code  
and may be followed by address bytes, a mode byte, read latency (dummy / don’t care) cycles, or data bytes.  
Commands are completed with the rising edge of edge CS#. Clock relative sequence diagrams for each  
command are included in the command descriptions. All read commands can be completed after any data bit.  
However, all commands that Write, Program or Erase must complete on a byte boundary (CS# driven high  
after a full 8 bits have been clocked) otherwise the command will be ignored. This feature further protects the  
device from inadvertent writes. Additionally, while the memory is being programmed or erased, all commands  
except for Read Status Register and Suspend commands will be ignored until the program or erase cycle has  
completed. When the Status Register is being written, all commands except for Read Status Register will be  
ignored until the Status Register write operation has completed.  
Table 9.1 Command Set (Configuration, Status, Erase, Program Commands(1))  
BYTE 1  
(Instruction)  
Command Name  
BYTE 2  
BYTE 3  
BYTE 4  
BYTE 5  
BYTE 6  
Read Status Register-1  
Read Status Register-2  
Read Status Register-3  
Write Enable  
05h  
35h  
33h  
06h  
SR1[7:0] (2)(4)  
SR2[7:0] (2)(4)  
SR3[7:0] (2)  
Write Enable for Volatile Status  
Register  
50h  
Write Disable  
04h  
01h  
Write Status Registers  
Set Burst with Wrap  
Page Program  
SR1[7:0]  
xxh  
SR2[7:0]  
xxh  
SR3[7:0]  
xxh  
77h  
SR3[7:0] (3)  
D7–D0  
02h  
A23–A16  
A23–A16  
A23–A16  
A15–A8  
A15–A8  
A15–A8  
A7–A0  
A7–A0  
A7–A0  
Sector Erase (4 kB)  
Block Erase (64 kB)  
Chip Erase  
20h  
D8h  
C7h/60h  
75h  
Erase / Program Suspend  
Erase / Program Resume  
7Ah  
Notes:  
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on  
the SO pin.  
2. Status Register contents will repeat continuously until CS# terminates the command.  
3. Set Burst with Wrap Input format to load SR3. See Table 7.6 on page 45.  
IO0 = x, x, x, x, x, x, W4, x]  
IO1 = x, x, x, x, x, x, W5, x]  
IO2 = x, x, x, x, x, x, W6 x]  
IO3 = x, x, x, x, x, x, x,x  
4. When changing the value of any single bit, read all other bits and rewrite the same value to them.  
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Table 9.2 Command Set (Read Commands)  
BYTE 1  
(Instruction)  
Command Name  
Read Data  
BYTE 2  
BYTE 3  
BYTE 4  
BYTE 5  
BYTE 6  
03h  
0Bh  
3Bh  
6Bh  
A23–A16  
A23–A16  
A23–A16  
A23–A16  
A15–A8  
A15–A8  
A15–A8  
A15–A8  
A7–A0  
A7–A0  
A7–A0  
A7–A0  
(D7–D0, …)  
dummy  
Fast Read  
(D7–D0, …)  
(D7–D0, …) (1)  
(D7–D0, …) (3)  
Fast Read Dual Output  
Fast Read Quad Output  
dummy  
dummy  
A7–A0,M7–M0  
(2)  
Fast Read Dual I/O  
Fast Read Quad I/O  
BBh  
EBh  
FFh  
A23–A8 (2)  
(D7–D0, …) (1)  
(D7–D0, …) (3)  
A23–A0,  
M7–M0 (4)  
(x,x,x,x,  
D7–D0, …) (5)  
Continuous Read Mode Reset  
(6)  
FFh  
Notes:  
1. Dual Output data  
IO0 = (D6, D4, D2, D0)  
IO1 = (D7, D5, D3, D1)  
2. Dual Input Address  
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0  
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1  
3. Quad Output Data  
IO0 = (D4, D0, …..)  
IO1 = (D5, D1, …..)  
IO2 = (D6, D2, …..)  
IO3 = (D7, D3, …..)  
4. Quad Input Address  
IO0 = A20, A16, A12, A8, A4, A0, M4, M0  
IO1 = A21, A17, A13, A9, A5, A1, M5, M1  
IO2 = A22, A18, A14, A10, A6, A2, M6, M2  
IO3 = A23, A19, A15, A11, A7, A3, M7, M3  
5. Fast Read Quad I/O Data  
IO0 = (x, x, x, x, D4, D0, …..)  
IO1 = (x, x, x, x, D5, D1, …..)  
IO2 = (x, x, x, x, D6, D2, …..)  
IO3 = (x, x, x, x, D7, D3, …..)  
6. This command is recommended when using the Dual or Quad “Continuous Read Mode” feature. See Section 9.3.8 and Section 9.3.9  
on page 69 for more information.  
Table 9.3 Command Set (ID, Security Commands)  
BYTE 1  
(Instruction)  
Command Name  
Deep Power-down  
BYTE 2  
BYTE 3  
BYTE 4  
BYTE 5  
BYTE 6  
B9h  
Release Power down / Device ID  
Manufacturer / Device ID (2)  
JEDEC ID  
ABh  
dummy  
dummy  
dummy  
dummy  
dummy  
00h  
Device ID (1)  
Manufacturer  
90h  
Device ID  
9Fh  
Manufacturer  
Memory Type  
Capacity  
Read SFDP Register /  
Read Unique ID Number  
5Ah  
00h  
00h  
A7–A0  
dummy  
dummy  
(D7–D0, …)  
(D7–D0, …)  
Read Security Registers (3)  
Erase Security Registers (3)  
Program Security Registers (3)  
Notes:  
48h  
44h  
42h  
A23–A16  
A23–A16  
A23–A16  
A15–A8  
A15–A8  
A15–A8  
A7–A0  
A7–A0  
A7–A0  
D7–D0, …  
1. The Device ID will repeat continuously until CS# terminates the command.  
2. See Section 7.5.1, Legacy Device Identification Commands on page 51 for Device ID information. The 90h instruction is followed by an  
address. Address = 0 selects Manufacturer ID as the first returned data as shown in the table. Address = 1 selects Device ID as the first  
returned data followed by Manufacturer ID.  
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3. Security Register Address:  
Security Register 0: A23-16 = 00h; A15-8 = 00h; A7-0 = byte address  
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address  
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address  
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address  
Security Register 0 is used to store the SFDP parameters and is always programmed and locked by Spansion.  
9.1  
9.1.1  
Configuration and Status Commands  
Read Status Registers (05h), (35h), (33h)  
The Read Status Register commands allow the 8-bit Status Registers to be read. The command is entered by  
driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2, or  
33h for Status Register-3, into the SI pin on the rising edge of CLK. The Status Register bits are then shifted  
out on the SO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 9.1. The  
Status Register bits are shown in Section 7.4, Status Registers on page 44.  
The Read Status Register-1 (05h) command may be used at any time, even while a Program, Erase, or Write  
Status Registers cycle is in progress. This allows the BUSY status bit to be checked to determine when the  
operation is complete and if the device can accept another command. The Read Status Register-2 (35h), and  
Read Status Registers (33h) may be used only when the device is in standby, not busy with an embedded  
operation.  
Status Registers can be read continuously as each repeated data output delivers the updated current value of  
each status register. Example: using the instruction code “05h” for Read Status Register-1, the first output of  
eight bits may show the device is busy, SR1[0]=1. By continuing to hold CS# low, the updated value of SR1  
will be shown in the next byte output. This repeated reading of SR1can continue until the system detects the  
Busy bit has changed back to ready status in one of the status bytes being read out. The Read Status  
Register commands are completed by driving CS# high.  
Figure 9.1 Read Status Register Command Sequence Diagram  
CS#  
SCLK  
SI  
SO  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Status  
Updated Status  
9.1.2  
Write Enable (06h)  
The Write Enable command (Figure 9.2) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.  
The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase, Write Status  
Registers and Erase / Program Security Registers command. The Write Enable command is entered by  
driving CS# low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge of CLK, and  
then driving CS# high.  
Figure 9.2 Write Enable (WREN 06h) Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
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9.1.3  
Write Enable for Volatile Status Register (50h)  
The non-volatile Status Register bits described in Section 7.4, Status Registers on page 44 can also be  
written to as volatile bits. During power up reset, the non-volatile Status Register bits are copied to a volatile  
version of the Status Register that is used during device operation. This gives more flexibility to change the  
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit  
write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile version of  
the Status Register bits, the Write Enable for Volatile Status Register (50h) command must be issued and  
immediately followed by the Write Status Registers (01h) command. Write Enable for Volatile Status Register  
command (Figure 9.3) will not set the Write Enable Latch (WEL) bit, it is only valid for the next following Write  
Status Registers command, to change the volatile Status Register bit values.  
Figure 9.3 Write Enable for Volatile Status Register Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
9.1.4  
Write Disable (04h)  
The Write Disable command resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write  
Disable command is entered by driving CS# low, shifting the instruction code “04h” into the SI pin and then  
driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion of the  
Write Status Registers, Erase / Program Security Registers, Page Program, Sector Erase, Block Erase and  
Chip Erase commands.  
Figure 9.4 Write Disable (WRDI 04h) Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
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9.1.5  
Write Status Registers (01h)  
The Write Status Registers command allows the Status Registers to be written. Only non-volatile Status  
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (SR1[7:2]) CMP, LB3, LB2, LB1, QE, SRP1 (SR2[6:0]), and the  
volatile bits SR3[6:0] can be written. All other Status Register bit locations are read-only and will not be  
affected by the Write Status Registers command. LB3-0 are non-volatile OTP bits; once each is set to 1, it  
can not be cleared to 0. The Status Register bits are shown in Section 7.4, Status Registers on page 44. Any  
reserved bits should only be written to their default value.  
To write non-volatile Status Register bits, a standard Write Enable (06h) command must previously have  
been executed for the device to accept the Write Status Registers Command (Status Register bit WEL must  
equal 1). Once write enabled, the command is entered by driving CS# low, sending the instruction code “01h”,  
and then writing the Status Register data bytes as illustrated in Figure 9.5.  
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) command must have  
been executed prior to the Write Status Registers command (Status Register bit WEL remains 0). However,  
SRP1 and LB3, LB2, LB1, LB0 can not be changed because of the OTP protection for these bits. Upon power  
off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be  
restored when power on again.  
To complete the Write Status Registers command, the CS# pin must be driven high after the eighth bit of a  
data value is clocked in (CS# must be driven high on an 8-bit boundary). If this is not done the Write Status  
Registers command will not be executed. If CS# is driven high after the eighth clock the CMP and QE bits will  
be cleared to 0 if the SRP1 bit is 0. The SR2 bits are unaffected if SRP1 is 1. If CS# is driven high after the  
eighth or sixteenth clock, the SR3 bits will not be affected.  
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven high at the  
end of the Write Status Registers command, the self-timed Write Status Registers operation will commence  
for a time duration of tW (see Section 5.7, AC Electrical Characteristics on page 31). While the Write Status  
Registers operation is in progress, the Read Status Register command may still be accessed to check the  
status of the BUSY bit. The BUSY bit is a 1 during the Write Status Registers operation and a 0 when the  
operation is finished and ready to accept other commands again. After the Write Status Registers operation  
has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.  
During volatile Status Register write operation (50h combined with 01h), after CS# is driven high at the end of  
the Write Status Registers command, the Status Register bits will be updated to the new values within the  
time period of tSHSL2 (see Section 5.7, AC Electrical Characteristics on page 31). BUSY bit will remain 0  
during the Status Register bit refresh period.  
Refer to Section 7.4, Status Registers on page 44 for detailed Status Register Bit descriptions.  
Figure 9.5 Write Status Registers Command Sequence Diagram  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Input Status Register-1  
Input Status Register-2  
Input Status Register-3  
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9.2  
9.2.1  
Program and Erase Commands  
Page Program (02h)  
The Page Program command allows from one byte to 256 bytes (a page) of data to be programmed at  
previously erased (FFh) memory locations. A Write Enable command must be executed before the device will  
accept the Page Program Command (Status Register bit WEL= 1). The command is initiated by driving the  
CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one  
data byte, into the SI pin. The CS# pin must be held low for the entire length of the command while data is  
being sent to the device. The Page Program command sequence is shown in Figure 9.6, Page Program  
Command Sequence on page 59.  
If an entire 256-byte page is to be programmed, the last address byte (the 8 least significant address bits)  
should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page  
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial  
page) can be programmed without having any effect on other bytes within the same page. One condition to  
perform a partial page program is that the number of clocks can not exceed the remaining page length. If  
more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and  
overwrite previously sent data.  
As with the write and erase commands, the CS# pin must be driven high after the eighth bit of the last byte  
has been latched. If this is not done the Page Program command will not be executed. After CS# is driven  
high, the self-timed Page Program command will commence for a time duration of tPP (Section 5.7, AC  
Electrical Characteristics on page 31). While the Page Program cycle is in progress, the Read Status  
Register command may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during  
the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other  
commands again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status  
Register is cleared to 0. The Page Program command will not be executed if the addressed page is protected  
by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.  
Figure 9.6 Page Program Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Input Data1  
Input Data2  
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9.2.2  
Sector Erase (20h)  
The Sector Erase command sets all memory within a specified sector (4 kbytes) to the erased state of all 1’s  
(FFh). A Write Enable command must be executed before the device will accept the Sector Erase Command  
(Status Register bit WEL must equal 1). The command is initiated by driving the CS# pin low and shifting the  
instruction code “20h” followed a 24-bit sector address (A23-A0) See Supply and Signal Ground (VSS  
)
on page 16. The Sector Erase command sequence is shown in Figure 9.7 on page 60.  
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the  
Sector Erase command will not be executed. After CS# is driven high, the self-timed Sector Erase command  
will commence for a time duration of tSE. Section 5.7, AC Electrical Characteristics on page 31 While the  
Sector Erase cycle is in progress, the Read Status Register command may still be accessed for checking the  
status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is  
finished and the device is ready to accept other commands again. After the Sector Erase cycle has finished  
the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase command will not  
be executed if the addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)  
bits.  
Figure 9.7 Sector Erase Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
1
0
Phase  
Instruction  
Address  
9.2.3  
64-kB Block Erase (D8h)  
The Block Erase command sets all memory within a specified block (64 kbytes) to the erased state of all 1s  
(FFh). A Write Enable command must be executed before the device will accept the Block Erase Command  
(Status Register bit WEL must equal 1). The command is initiated by driving the CS# pin low and shifting the  
instruction code “D8h” followed a 24-bit block address (A23-A0) See Supply and Signal Ground (VSS  
)
on page 16. The Block Erase command sequence is shown in Figure 9.8.  
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the  
Block Erase command will not be executed. After CS# is driven high, the self-timed Block Erase command  
will commence for a time duration of tBE (see Section 5.7, AC Electrical Characteristics on page 31). While  
the Block Erase cycle is in progress, the Read Status Register command may still be accessed for checking  
the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle  
is finished and the device is ready to accept other commands again. After the Block Erase cycle has finished  
the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase command will not be  
executed if the addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits  
(see Section 7.4, Status Registers on page 44).  
Figure 9.8 64 kB Block Erase Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
1
0
Phase  
Instruction  
Address  
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9.2.4  
Chip Erase (C7h / 60h)  
The Chip Erase command sets all memory within the device to the erased state of all 1’s (FFh). A Write  
Enable command must be executed before the device will accept the Chip Erase Command (Status Register  
bit WEL must equal 1). The command is initiated by driving the CS# pin low and shifting the instruction code  
“C7h” or “60h”. The Chip Erase command sequence is shown in Figure 9.9.  
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase  
command will not be executed. After CS# is driven high, the self-timed Chip Erase command will commence  
for a time duration of tCE (Section 5.7, AC Electrical Characteristics on page 31). While the Chip Erase cycle  
is in progress, the Read Status Register command may still be accessed to check the status of the BUSY bit.  
The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to  
accept other commands again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in  
the Status Register is cleared to 0. The Chip Erase command will not be executed if any page is protected by  
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Section 7.4, Status Registers on page 44).  
Figure 9.9 Chip Erase Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
9.2.5  
Erase / Program Suspend (75h)  
The Erase / Program Suspend command allows the system to interrupt a Sector or Block Erase operation,  
then read from or program data to any other sector. The Erase / Program Suspend command also allows the  
system to interrupt a Page Program operation and then read from any other page or erase any other sector or  
block. The Erase / Program Suspend command sequence is shown in Figure 9.10, Erase / Program Suspend  
Command Sequence on page 62.  
The Write Status Registers command (01h), Program Security Registers (42h), and Erase commands (20h,  
D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or  
Block erase operation. If written during the Chip Erase operation, the Erase Suspend command is ignored.  
The Write Status Registers command (01h), Erase Security Registers (44h), and Program commands (02h,  
32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program  
operation.  
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Table 9.4 Commands Accepted During Suspend  
Operation  
Suspended  
Command Allowed  
Instruction  
Program or Erase  
Program or Erase  
Program or Erase  
Program or Erase  
Program or Erase  
Program or Erase  
Program or Erase  
Program or Erase  
Program or Erase  
Program or Erase  
Erase  
Read Data  
Fast Read  
03h  
0Bh  
3Bh  
6Bh  
BBh  
EBh  
FFh  
05h  
35h  
06h  
02h  
20h  
D8h  
7Ah  
Fast Read Dual Output  
Fast Read Quad Output  
Fast Read Dual I/O  
Fast Read Quad I/O  
Continuous Read Mode Reset  
Read Status Register-1  
Read Status Register-2  
Write Enable  
Page Program  
Program  
Sector Erase  
Program  
Block Erase  
Program or Erase  
Erase / Program Resume  
The Erase / Program Suspend command 75h will be accepted by the device only if the SUS bit in the Status  
Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation  
is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend command will be ignored by  
the device. Program or Erase command for the sector that is being suspended will be ignored.  
A maximum of time of tSUS (Section 5.7, AC Electrical Characteristics on page 31) is required to suspend the  
erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within tSUS and  
the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase / Program Suspend. For a  
previously resumed Erase / Program operation, it is also required that the Suspend command 75h is not  
issued earlier than a minimum of time of tSUS following the preceding Resume command 7Ah.  
Unexpected power off during the Erase / Program suspend state will reset the device and release the  
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block  
that was being suspended may become corrupted. It is recommended for the user to implement system  
design techniques to prevent accidental power interruption, provide non-volatile tracking of in process  
program or erase commands, and preserve data integrity by evaluating the non-volatile program or erase  
tracking information during each system power up in order to identify and repair (re-erase and re-program)  
any improperly terminated program or erase operations.  
Figure 9.10 Erase / Program Suspend Command Sequence  
tSUS  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4 3 2 1 0  
7
6
5
4 3 2 1 0  
Phase  
Phase  
Suspend Instruction  
Read Status Instruction  
Status  
Instr. During Suspend  
Repeat Status Read Until Suspended  
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9.2.6  
Erase / Program Resume (7Ah)  
The Erase / Program Resume command “7Ah” must be written to resume the Sector or Block Erase operation  
or the Page Program operation after an Erase / Program Suspend. The Resume command “7Ah” will be  
accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0.  
After the Resume command is issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be  
set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation or the page will  
complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume  
command “7Ah” will be ignored by the device. The Erase / Program Resume command sequence is shown in  
Figure 9.11.  
It is required that a subsequent Erase / Program Suspend command not to be issued within a minimum of  
time of “tSUS” following a Resume command.  
Figure 9.11 Erase / Program Resume Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
9.3  
9.3.1  
Read Commands  
Read Data (03h)  
The Read Data command allows one or more data bytes to be sequentially read from the memory. The  
command is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a  
24-bit address (A23-A0) into the SI pin. The code and address bits are latched on the rising edge of the CLK  
pin. After the address is received, the data byte of the addressed memory location will be shifted out on the  
SO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically  
incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream  
of data. This means that the entire memory can be accessed with a single command as long as the clock  
continues. The command is completed by driving CS# high.  
The Read Data command sequence is shown in Figure 9.12. If a Read Data command is issued while an  
Erase, Program or Write cycle is in process (BUSY=1) the command is ignored and will not have any effects  
on the current cycle. The Read Data command allows clock rates from DC to a maximum of fR (see  
Section 5.7, AC Electrical Characteristics on page 31).  
Figure 9.12 Read Data Command Sequence  
CS#  
SCLK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Data1  
Data2  
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9.3.2  
Fast Read (0Bh)  
The Fast Read command is similar to the Read Data command except that it can operate at higher frequency  
than the traditional Read Data command. This is accomplished by adding eight “dummy” clocks after the  
24-bit address as shown in Figure 9.13. The dummy clocks allow the devices internal circuits additional time  
for setting up the initial address. During the dummy clocks the data value on the SI pin is a “don’t care.”  
When variable read latency is enabled, the number of dummy cycles is set by the Latency Control value in  
SR3 to optimize the latency for the frequency in use. See. Table 7.10, Latency Cycles Versus Frequency  
on page 50.  
Figure 9.13 Fast Read Command Sequence  
CS#  
SCLK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Dummy Cycles  
Data1  
9.3.3  
Fast Read Dual Output (3Bh)  
The Fast Read Dual Output (3Bh) command is similar to the standard Fast Read (0Bh) command except that  
data is output on two pins; IO0 and IO1. This allows data to be transferred from the S25FL116K at twice the  
rate of standard SPI devices. The Fast Read Dual Output command is ideal for quickly downloading code  
from flash to RAM upon power-up or for applications that cache code-segments to RAM for execution.  
Similar to the Fast Read command, the Fast Read Dual Output command can operate at higher frequency  
than the traditional Read Data command. This is accomplished by adding eight “dummy” clocks after the 24-  
bit address as shown in Figure 9.14. The dummy clocks allow the device's internal circuits additional time for  
setting up the initial address. The input data during the dummy clocks is “don’t care.” However, the IO0 pin  
should be high-impedance prior to the falling edge of the first data out clock.  
When variable read latency is enabled, the number of dummy cycles is set by the Latency Control value in  
SR3 to optimize the latency for the frequency in use. See. Table 7.10, Latency Cycles Versus Frequency  
on page 50.  
Figure 9.14 Fast Read Dual Output Command Sequence  
CS#  
SCLK  
IO0  
IO1  
7
6
5
4
3
2
1
0 23 22 21  
Address  
0
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
Phase  
Instruction  
Dummy  
Data1  
Data2  
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9.3.4  
Fast Read Quad Output (6Bh)  
The Fast Read Quad Output (6Bh) command is similar to the Fast Read Dual Output (3Bh) command except  
that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed  
before the device will accept the Fast Read Quad Output Command (Status Register bit QE must equal 1).  
The Fast Read Quad Output Command allows data to be transferred from the S25FL116K at four times the  
rate of standard SPI devices.  
The Fast Read Quad Output command can operate at higher frequency than the traditional Read Data  
command. This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in  
Figure 9.15. The dummy clocks allow the device's internal circuits additional time for setting up the initial  
address. The input data during the dummy clocks is “don’t care.” However, the IO pins should be high-  
impedance prior to the falling edge of the first data out clock.  
When variable read latency is enabled, the number of dummy cycles is set by the Latency Control value in  
SR3 to optimize the latency for the frequency in use. See. Table 7.10, Latency Cycles Versus Frequency  
on page 50.  
Figure 9.15 Fast Read Quad Output Command Sequence  
CS#  
SCK  
IO0  
IO1  
7
6
5
4
3
2
1
0
23  
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO2  
IO3  
Phase  
Instruction  
Address  
Dummy  
D1  
D2  
D3  
D4  
D5  
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9.3.5  
Fast Read Dual I/O (BBh)  
The Fast Read Dual I/O (BBh) command allows for improved random access while maintaining two IO pins,  
IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) command but with the capability to input the  
Address bits (A23-0) two bits per clock. This reduced command overhead may allow for code execution (XIP)  
directly from the Dual SPI in some applications.  
Fast Read Dual I/O with “Continuous Read Mode”  
The Fast Read Dual I/O command can further reduce instruction overhead through setting the “Continuous  
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 9.16. The upper nibble of the  
(M7-4) controls the length of the next Fast Read Dual I/O command through the inclusion or exclusion of the  
first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should  
be high-impedance prior to the falling edge of the first data out clock.  
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O command (after CS# is  
raised and then lowered) does not require the BBh instruction code, as shown in Figure 9.17. This reduces  
the command sequence by eight clocks and allows the Read address to be immediately entered after CS# is  
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after CS# is  
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A  
“Continuous Read Mode” Reset command can also be used to reset (M7-0) before issuing normal commands  
(see See Continuous Read Mode Reset (FFh or FFFFh) on page 69.).  
When variable read latency is enabled, the number of latency (Mode + Dummy) cycles is set by the Latency  
Control value in SR3 to optimize the latency for the frequency in use. See. Table 7.10, Latency Cycles Versus  
Frequency on page 50. Note that the legacy Read Dual I/O command has four Mode cycles and no Dummy  
cycles for a total of four latency cycles, Enabling the variable read latency allows for the addition of more read  
latency to enable higher frequency operation of the Dual I/O command.  
Figure 9.16 Fast Read Dual I/O Command Sequence (Initial command or previous M5-4 ≠ 10)  
CS#  
SCK  
IO0  
IO1  
7
6
5
4
3
2
1
0
22  
23  
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
Phase  
Instruction  
Address  
Mode  
Dummy  
Data1  
Data2  
Note:  
1. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these  
cycles to increase bus turn around time between Mode bits from host and returning data from the memory.  
Figure 9.17 Fast Read Dual I/O Command Sequence (Previous command set M5-4 = 10)  
CS#  
SCK  
IO0  
IO1  
6
7
4
5
2
3
0
1
22  
23  
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
Phase  
DataN  
Address  
Mode  
Dummy  
Data1  
Data2  
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9.3.6  
Fast Read Quad I/O (EBh)  
The Fast Read Quad I/O (EBh) command is similar to the Fast Read Dual I/O (BBh) command except that  
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are  
required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster  
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status  
Register-2 must be set to enable the Fast Read Quad I/O Command.  
Fast Read Quad I/O with “Continuous Read Mode”  
The Fast Read Quad I/O command can further reduce instruction overhead through setting the “Continuous  
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 9.18, Fast Read Quad I/O  
Command Sequence (Initial command or previous M5-4 ≠10) on page 67. The upper nibble of the (M7-4)  
controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first  
byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be  
high-impedance prior to the falling edge of the first data out clock.  
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O command (after CS# is  
raised and then lowered) does not require the EBh instruction code, as shown in Figure 9.19, Fast Read  
Quad I/O Command Sequence (Previous command set M5-4 = 10) on page 67. This reduces the command  
sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low.  
If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after CS# is raised and  
then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read  
Mode” Reset command can also be used to reset (M7-0) before issuing normal commands (see  
Section 9.3.8, Continuous Read Mode Reset (FFh or FFFFh) on page 69).  
When variable read latency is enabled, the number of latency (Mode + Dummy) cycles is set by the Latency  
Control value in SR3 to optimize the latency for the frequency in use. See. Table 7.10, Latency Cycles Versus  
Frequency on page 50. Note that the legacy Read Quad I/O command has two Mode cycles plus four  
Dummy cycles for a total of six latency cycles, Enabling the variable read latency allows for the addition of  
more read latency to enable higher frequency operation of the Quad I/O command.  
Figure 9.18 Fast Read Quad I/O Command Sequence (Initial command or previous M5-4 ≠10)  
CS#  
SCLK  
IO0  
IO1  
7
6
5
4
3
2
1
0
20  
21  
22  
23  
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO2  
IO3  
Phase  
Note:  
Instruction  
Address Mode  
Dummy  
D1  
D2  
D3  
D4  
1. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these  
cycles to increase bus turn around time between Mode bits from host and returning data from the memory.  
Figure 9.19 Fast Read Quad I/O Command Sequence (Previous command set M5-4 = 10)  
CS#  
SCK  
IO0  
IO1  
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
20  
21  
22  
23  
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
1
1
6
7
7
7
4
5
5
5
2
3
3
3
0
1
1
1
IO2  
IO3  
Phase  
DN-1  
DN  
Address  
Mode  
Dummy  
D1  
D2  
D3  
D4  
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Fast Read Quad I/O with “16/32/64-Byte Wrap Around”  
The Fast Read Quad I/O command can also be used to access a specific portion within a page by issuing a  
“Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or  
disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the  
data being accessed can be limited to either a 16/32/64-byte section of data. The output data starts at the  
initial address specified in the command, once it reaches the ending boundary of the 16/32/64-byte section,  
the output will wrap around to the beginning boundary automatically until CS# is pulled high to terminate the  
command.  
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill  
the cache afterwards within a fixed length (16/32/64-bytes) of data without issuing multiple read commands.  
The “Set Burst with Wrap” command allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or  
disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section  
within a page. See Section 9.3.7, Set Burst with Wrap (77h) on page 68.  
9.3.7  
Set Burst with Wrap (77h)  
The Set Burst with Wrap (77h) command is used in conjunction with “Fast Read Quad I/O” commands to  
access a fixed length and alignment of 8/16/32/64-bytes of data. Certain applications can benefit from this  
feature and improve the overall system code execution performance. This command loads the SR3 bits.  
Similar to a Quad I/O command, the Set Burst with Wrap command is initiated by driving the CS# pin low and  
then shifting the instruction code “77h” followed by 24-dummy bits and 8 “Wrap Bits”, W7-0. The command  
sequence is shown in Figure 9.20, Set Burst with Wrap Command Sequence on page 68. Wrap bit W7 and  
the lower nibble W3-0 are not used. See Status Register-3 (SR3[6:4]) for the encoding of W6-W4 in  
Section 7.4, Status Registers on page 44.  
Once W6-4 is set by a Set Burst with Wrap command, all the following “Fast Read Quad I/O” commands will  
use the W6-4 setting to access the 8/16/32/64-byte section of data. Note, Status Register-2 QE bit (SR2[1])  
must be set to 1 in order to use the Fast Read Quad I/O and Set Burst with Wrap commands. To exit the  
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should  
be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case of a system Reset while  
W4 = 0, it is recommended that the controller issues a Set Burst with Wrap command to reset W4 = 1 prior to  
any normal Read commands since S25FL116K does not have a hardware Reset Pin.  
Figure 9.20 Set Burst with Wrap Command Sequence  
CS#  
SCLK  
IO0  
IO1  
7
6
5
4
3
2
1
0
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
.X  
W4  
W5  
W6  
.X  
.X  
.X  
.X  
.X  
IO2  
IO3  
Phase  
Instruction  
Don’t Care  
Wrap  
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9.3.8  
Continuous Read Mode Reset (FFh or FFFFh)  
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O” and “Fast Read Quad  
I/O” commands to provide the highest random flash memory access rate with minimum SPI instruction  
overhead, thus allowing more efficient XIP (execute in place) with this device family.  
The “Continuous Read Mode” bits M7-0 are set by the Dual / Quad I/O Read commands. M5-4 are used to  
control whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next command. When  
M5-4 = (1,0), the next command will be treated the same as the current Dual / Quad I/O Read command  
without needing the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI  
command mode, in which all commands can be accepted. M7-6 and M3-0 are reserved bits for future use,  
either 0 or 1 values can be used.  
The Continuous Read Mode Reset command (FFh or FFFFh) can be used to set M4 = 1, thus the device will  
release the Continuous Read Mode and return to normal SPI operation, as shown in Figure 9.21.  
Figure 9.21 Continuous Read Mode Reset for Fast Read Dual or Quad I/O  
CS#  
SCK  
IO0  
IO1  
FFFFh  
IO2  
IO3  
DIO_Phase  
QIO_Phase  
Optional FFh  
Mode Bit Reset for Quad I/O  
Optional FFh  
Notes:  
1. To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The instruction is “FFh”.  
2. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh”.  
9.3.9  
Host System Reset Commands  
Since S25FL116K does not have a hardware Reset pin, if the host system memory controller resets, without  
a complete power down and power up sequence, while an S25FL116K device is set to Continuous Mode  
Read, the S25FL116K device will not recognize any initial standard SPI commands from the controller. To  
address this possibility, it is recommended to issue a Continuous Read Mode Reset (FFFFh) command as  
the first command after a system Reset. Doing so will release the device from the Continuous Read Mode  
and allow Standard SPI commands to be recognized. See Section 9.3.8, Continuous Read Mode Reset (FFh  
or FFFFh) on page 69.  
If Burst Wrap Mode is used, it is also recommended to issue a Set Burst with Wrap (77h) command that sets  
the W4 bit to one as the second command after a system Reset. Doing so will release the device from the  
Burst Wrap Mode and allow standard sequential read SPI command operation. See Section 9.3.7, Set Burst  
with Wrap (77h) on page 68.  
Issuing these commands immediately after a non-power-cycle (warm) system reset, ensures the device  
operation is consistent with the power on default device operation. The same commands may also be issued  
after device power on (cold) reset so that system reset code is the same for warm or cold reset.  
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9.4  
9.4.1  
ID and Security Commands  
Deep-Power-Down (B9h)  
Although the standby current during normal operation is relatively low, standby current can be further reduced  
with the Deep-Power-Down command. The lower power consumption makes the Deep-Power-Down (DPD)  
command especially useful for battery powered applications (see ICC1 and ICC2 in Section 5.7, AC Electrical  
Characteristics on page 31). The command is initiated by driving the CS# pin low and shifting the instruction  
code “B9h” as shown in Figure 9.22.  
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep-Power-  
Down command will not be executed. After CS# is driven high, the power-down state will entered within the  
time duration of tDP (Section 5.7, AC Electrical Characteristics on page 31). While in the power-down state  
only the Release from Deep-Power-Down / Device ID command, which restores the device to normal  
operation, will be recognized. All other commands are ignored. This includes the Read Status Register  
command, which is always available during normal operation. Ignoring all but one command also makes the  
Power Down state a useful condition for securing maximum write protection. The device always powers-up in  
the normal operation with the standby current of ICC1  
.
Figure 9.22 Deep Power-Down Command Sequence  
CS#  
SCLK  
SI  
7
6
5
4
3
2
1
0
SO  
Phase  
Instruction  
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9.4.2  
Release from Deep-Power-Down / Device ID (ABh)  
The Release from Deep-Power-Down / Device ID command is a multi-purpose command. It can be used to  
release the device from the deep-power-down state, or obtain the devices electronic identification (ID)  
number.  
To release the device from the deep-power-down state, the command is issued by driving the CS# pin low,  
shifting the instruction code “ABh” and driving CS# high as shown in Figure 9.23. Release from deep-power-  
down will take the time duration of tRES1 (Section 5.7, AC Electrical Characteristics on page 31) before the  
device will resume normal operation and other commands are accepted. The CS# pin must remain high  
during the tRES1 time duration.  
When used only to obtain the Device ID while not in the deep power-down state, the command is initiated by  
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits  
are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID values for  
the S25FL116K is listed in Section 7.5.1, Legacy Device Identification Commands on page 51. The Device ID  
can be read continuously. The command is completed by driving CS# high.  
When used to release the device from the deep-power-down state and obtain the Device ID, the command is  
the same as previously described, and shown in Figure 9.24, except that after CS# is driven high it must  
remain high for a time duration of tRES2. After this time duration the device will resume normal operation and  
other commands will be accepted. If the Release from Deep-Power-Down / Device ID command is issued  
while an Erase, Program or Write cycle is in process (when BUSY equals 1) the command is ignored and will  
not have any effects on the current cycle.  
Figure 9.23 Release from Deep-Power-Down Command Sequence  
CS#  
SCLK  
SI  
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
Figure 9.24 Read Electronic Signature (RES ABh) Command Sequence  
CS#  
SCK  
SI  
7
6
5
4
3
2
1
0
23  
1
0
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction (ABh)  
Dummy  
Device ID  
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9.4.3  
Read Manufacturer / Device ID (90h)  
The Read Manufacturer / Device ID command is an alternative to the Release from Deep-Power-Down /  
Device ID command that provides both the JEDEC assigned manufacturer ID and the specific device ID.  
The Read Manufacturer / Device ID command is very similar to the Release from Deep-Power-Down / Device  
ID command. The command is initiated by driving the CS# pin low and shifting the instruction code “90h”  
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID and the Device ID are  
shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 9.25. The Device  
ID values for the S25FL116K is listed in Section 7.5.1, Legacy Device Identification Commands on page 51. If  
the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the  
Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the  
other. The command is completed by driving CS# high.  
Figure 9.25 READ_ID (90h) Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction (90h)  
Address  
Manufacturer ID  
Device ID  
9.4.4  
Read JEDEC ID (9Fh)  
For compatibility reasons, the S25FL116K provides several commands to electronically determine the identity  
of the device. The Read JEDEC ID command is compatible with the JEDEC standard for SPI compatible  
serial flash memories that was adopted in 2003. The command is initiated by driving the CS# pin low and  
shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte and two Device ID bytes,  
Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most  
significant bit (MSB) first as shown in Figure 9.26. For memory type and capacity values refer to  
Section 7.5.1, Legacy Device Identification Commands on page 51.  
Figure 9.26 Read JEDEC ID Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Data1  
DataN  
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9.4.5  
Read SFDP Register / Read Unique ID Number (5Ah)  
The Read SFDP command is initiated by driving the CS# pin low and shifting the instruction code “5Ah”  
followed by a 24-bit address (A23-A0) into the SI pin. Eight “dummy” clocks are also required before the  
SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first  
as shown in Figure 9.27. For SFDP register values and descriptions, refer to Table 7.3, Serial Flash  
Discoverable Parameter Definition Table on page 42.  
Note: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-byte SFDP Register.  
The 5Ah command can also be used to access the Read Unique ID Number. This is a factory-set read-only  
8-byte number that is unique to each S25FL1-K device. The ID number can be used in conjunction with user  
software methods to help prevent copying or cloning of a system.  
Figure 9.27 Read SFDP Register Command Sequence  
CS#  
SCLK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Dummy Cycles  
Data1  
9.4.6  
Erase Security Registers (44h)  
The Erase Security Register command is similar to the Sector Erase command. A Write Enable command  
must be executed before the device will accept the Erase Security Register Command (Status Register bit  
WEL must equal 1). The command is initiated by driving the CS# pin low and shifting the instruction code  
“44h” followed by a 24-bit address (A23-A0) to erase one of the security registers.  
Address  
A23-16  
00h  
A15-8  
10h  
A7-0  
xxh  
xxh  
xxh  
Security Register-1  
Security Register-2  
Security Register-3  
00h  
20h  
00h  
30h  
Note:  
1. Addresses outside the ranges in the table have undefined results.  
The Erase Security Register command sequence is shown in Figure 9.28. The CS# pin must be driven high  
after the eighth bit of the last byte has been latched. If this is not done the command will not be executed.  
After CS# is driven high, the self-timed Erase Security Register operation will commence for a time duration  
of tSE (see Section 5.7, AC Electrical Characteristics on page 31). While the Erase Security Register cycle is  
in progress, the Read Status Register command may still be accessed for checking the status of the BUSY  
bit. The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is  
ready to accept other commands again. After the Erase Security Register cycle has finished the Write Enable  
Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3:1) in the Status  
Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding  
security register will be permanently locked, and an Erase Security Register command to that register will be  
ignored (see Security Register Lock Bits (LB3, LB2, LB1, LB0) on page 49).  
Figure 9.28 Erase Security Registers Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
1
0
Phase  
Instruction  
Address  
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9.4.7  
Program Security Registers (42h)  
The Program Security Register command is similar to the Page Program command. It allows from one byte to  
256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write  
Enable command must be executed before the device will accept the Program Security Register Command  
(Status Register bit WEL= 1). The command is initiated by driving the CS# pin low then shifting the instruction  
code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the SI pin. The CS# pin  
must be held low for the entire length of the command while data is being sent to the device.  
Address  
A23-16  
00h  
A15-8  
10h  
A7-0  
Security Register-1  
Security Register-2  
Security Register-3  
Byte Address  
Byte Address  
Byte Address  
00h  
20h  
00h  
30h  
Note:  
1. Addresses outside the ranges in the table have undefined results.  
The Program Security Register command sequence is shown in Figure 9.29. The Security Register Lock Bits  
(LB3:1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1,  
the corresponding security register will be permanently locked, and a Program Security Register command to  
that register will be ignored (see Security Register Lock Bits (LB3, LB2, LB1, LB0) on page 49 and Page  
Program (02h) on page 59 for detail descriptions).  
Figure 9.29 Program Security Registers Command Sequence  
CS#  
SCK  
SI  
SO  
7
6
5
4
3
2
1
0
23  
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Input Data1  
Input Data2  
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9.4.8  
Read Security Registers (48h)  
The Read Security Register command is similar to the Fast Read command and allows one or more data  
bytes to be sequentially read from one of the three security registers. The command is initiated by driving the  
CS# pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight  
“dummy” clocks into the SI pin. The code and address bits are latched on the rising edge of the CLK pin. After  
the address is received, and following the eight dummy cycles, the data byte of the addressed memory  
location will be shifted out on the SO pin at the falling edge of CLK with most significant bit (MSB) first.  
Locations with address bits A23-A16 not equal to zero, have undefined data. The byte address is  
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte  
address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register, and  
continue to increment. The command is completed by driving CS# high. The Read Security Register  
command sequence is shown in Figure 9.30. If a Read Security Register command is issued while an Erase,  
Program, or Write cycle is in process (BUSY=1), the command is ignored and will not have any effects on the  
current cycle. The Read Security Register command allows clock rates from DC to a maximum of FR (see  
Section 5.7, AC Electrical Characteristics on page 31).  
Address  
A23-16  
00h  
A15-8  
00h  
A7-0  
Security Register-0 (SFDP)  
Security Register-1  
Security Register-2  
Security Register-3  
Byte Address  
Byte Address  
Byte Address  
Byte Address  
00h  
10h  
00h  
20h  
00h  
30h  
Note:  
1. Addresses outside the ranges in the table have undefined results.  
Figure 9.30 Read Security Registers Command Sequence  
CS#  
SCLK  
SI  
7
6
5
4
3
2
1
0
23  
1
0
SO  
7
6
5
4
3
2
1
0
Phase  
Instruction  
Address  
Dummy Cycles  
Data1  
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10. Data Integrity  
10.1 Endurance  
The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural  
requirements for performing valid endurance and retention tests based on a qualification specification. This  
methodology is intended to determine the ability of a flash device to sustain repeated data changes without  
failure (program / erase endurance) and to retain data for the expected life (data retention). Endurance and  
retention qualification specifications are specified in JESD47 or may be developed using knowledge-based  
methods as in JESD94.  
10.1.1  
Erase Endurance  
Table 10.1 Erase Endurance  
Parameter  
Min  
Typical  
Unit  
Erase per sector  
100K  
cycle  
Note:  
1. Data retention of 20 years is based on 1K erase cycles or less.  
10.2 Initial Delivery State  
The device is shipped from Spansion with non-volatile bits / default states set as follows:  
The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).  
The Unique Device ID is programmed to a random number seeded by the date and time of device test.  
The SFDP Security Register address space 0 contains the values as defined in Table 7.3, Serial Flash  
Discoverable Parameter Definition Table on page 42. Security Register address spaces 1 to 3 are erased:  
i.e. all bits are set to 1 (each byte contains FFh).  
Status Register-1 contains 00h.  
Status Register-2 contains 04h.  
Status Register-3 contains 70h.  
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Ordering Information  
11. Ordering Part Number  
The ordering part number is formed by a valid combination of the following:  
S25FL1  
16  
K
0X  
M
F
I
01  
1
Packing Type  
0
1
3
= Tray  
= Tube  
= 13” Tape and Reel  
Model Number (Additional Ordering Options)  
01 = 8-lead SO package (208 mil) / 8-contact WSON  
02 = 5x5 ball BGA package  
03 = 4x6 ball BGA package (208 mil)  
04 = 8-lead SO package (150 mil)  
Temperature Range  
I
=
Industrial (–40°C to +85°C)  
V
=
Automotive (–40°C to +105°C)  
Package Materials  
F
= Lead (Pb)-free  
H
= Low-halogen, Lead (Pb)-free  
Package Type  
M
N
B
= 8-lead SO package  
= 8-contact WSON package  
= 24-ball 6x8 mm BGA package, 1.0 mm pitch  
Speed  
0X = 108 MHz  
Device Technology  
K
= 90 nm floating gate process technology  
Density  
16 = 16 Mbits  
Device Family  
S25FL1  
Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory  
11.1 Valid Combinations  
The valid combinations supported for this family.  
Table 11.1 Valid Combinations  
Base Ordering Part  
Number  
Package and  
Temperature  
Speed Option  
Model Number  
Packing Type  
Package Marking  
01  
04  
01  
04  
01  
01  
02  
03  
02  
03  
FL116KIF01  
FL116KIF4  
MFI  
FL116KVF01  
FL116KVF4  
FL116KIF01  
FL116KVF01  
FL116KIH02  
FL116KIH03  
FL116KVH02  
FL116KVH03  
MFV  
0, 1, 3  
NFI  
FL116K  
0X  
NFV  
BHI  
0, 3  
BHV  
12. Contacting Spansion  
Obtain the latest list of company locations and contact information at  
http://www.spansion.com/About/Pages/Locations.aspx  
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13. Revision History  
Section  
Description  
Revision 01 (January 11, 2013)  
Initial release  
Revision 02 (April 10, 2013)  
Features  
Updated Cycling Endurance information  
DC Electrical Characteristics  
AC Electrical Characteristics  
Updated the typical value of ICC1 and added Max values for ICC1 and ICC2  
Updated Write Status Registers Time and Block Erase Time values  
Added a paragraph  
Data Integrity  
Updated Erase Endurance information  
Removed Data Retention section  
Revision 03 (August 26, 2013)  
Global  
Added Erase / Program Suspend and Erase / Program Resume features  
Revision 04 (October 1, 2013)  
Promoted data sheet from Advance Information to Preliminary  
Replaced USON with WSON  
Global  
DC Electrical Characteristics Table  
Revision 05 (October 16, 2013)  
Features  
Removed input and output capacitance  
Added the Unique ID security feature  
Added VDD(low) Time parameter  
Power-Up Timing and Voltage Levels  
Table  
Modified Parameter Header 4 and JEDEC Flash Parameters 8  
Added byte address for Unique ID  
Serial Flash Discoverable Parameter  
Definition Table  
Status Register-2 (SR2) Table  
Corrected SPRI description  
Command Set (ID, Security Commands)  
Table  
Added Unique ID to the list of security commands  
Read SFDP Register (5Ah)  
Revision 06 (November 6, 2013)  
Global  
Modified the command name and added a paragraph  
Added Automotive (–40°C to +105°C) Temperature range  
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Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without  
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as  
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to  
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal  
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under  
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,  
the prior authorization by the respective government entity will be required for export of those products.  
Trademarks and Notice  
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under  
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this  
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,  
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any  
damages of any kind arising out of the use of the information in this document.  
Copyright © 2013 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and  
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used  
are for informational purposes only and may be trademarks of their respective owners.  
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