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Features  
• Single 2.7V - 3.6V Supply  
• Serial Peripheral Interface (SPI) Compatible  
– Supports SPI Modes 0 and 3  
– Supports RapidS Operation  
– Supports Dual- and Quad-Input Program  
– Supports Dual- and Quad-Output Read  
• Very High Operating Frequencies  
– 100 MHz for RapidS  
32-Megabit  
2.7-volt  
Minimum  
– 85 MHz for SPI  
– Clock-to-Output (tV) of 5 ns Maximum  
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications  
– Uniform 4-Kbyte Block Erase  
– Uniform 32-Kbyte Block Erase  
– Uniform 64-Kbyte Block Erase  
SPI Serial Flash  
Memory with  
Dual-I/O and  
Quad-I/O  
– Full Chip Erase  
• Individual Sector Protection with Global Protect/Unprotect Feature  
– 64 Sectors of 64-Kbytes Each  
• Hardware Controlled Locking of Protected Sectors via WP Pin  
• Sector Lockdown  
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only  
• 128-Byte Programmable OTP Security Register  
• Flexible Programming  
Support  
– Byte/Page Program (1 to 256 Bytes)  
• Fast Program and Erase Times  
– 1.5 ms Typical Page Program (256 Bytes) Time  
– 50 ms Typical 4-Kbyte Block Erase Time  
– 250 ms Typical 32-Kbyte Block Erase Time  
– 400 ms Typical 64-Kbyte Block Erase Time  
• Program and Erase Suspend/Resume  
• Automatic Checking and Reporting of Erase/Program Failures  
• Software Controlled Reset  
AT25DQ321A  
Preliminary  
• JEDEC Standard Manufacturer and Device ID Read Methodology  
• Low Power Dissipation  
– 7 mA Active Read Current (Typical at 20 MHz)  
– 5 µA Deep Power-Down Current (Typical)  
• Endurance: 100,000 Program/Erase Cycles  
• Data Retention: 20 Years  
• Complies with Full Industrial Temperature Range  
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options  
– 8-lead SOIC (150-mil and 208-mil wide)  
– 16-lead SOIC (300-mil wide)  
– 8-pad Very Thin DFN (5 x 6 x 0.6 mm)  
8718A–DFLASH–04/10  
1.  
Description  
The AT25DQ321A is a serial interface Flash memory device designed for use in a wide variety of high-volume  
consumer based applications in which program code is shadowed from Flash memory into embedded or external  
RAM for execution. The flexible erase architecture of the AT25DQ321A, with its erase granularity as small as 4-  
Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.  
The physical sectoring and the erase block sizes of the AT25DQ321A have been optimized to meet the needs of  
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the  
memory space can be used much more efficiently. Because certain code modules and data storage segments  
must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with  
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space  
efficiency allows additional code routines and data storage segments to be added while still maintaining the same  
overall device density.  
The AT25DQ321A also offers a sophisticated method for protecting individual sectors against erroneous or  
malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a  
system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory  
array securely protected. This is useful in applications where program code is patched or updated on a subroutine  
or module basis, or in applications where data storage segments need to be modified without running the risk of  
errant modifications to the program code segments. In addition to individual sector protection capabilities, the  
AT25DQ321A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be  
either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors  
do not have to be unprotected one-by-one prior to initial programming.  
To take code and data protection to the next level, the AT25DQ321A incorporates a sector lockdown mechanism  
that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.  
This addresses the need of certain secure applications that require portions of the Flash memory array to be  
permanently protected against malicious attempts at altering program code, data modules, security information, or  
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time  
Programmable) Security Register that can be used for purposes such as unique device serialization, system-level  
Electronic Serial Number (ESN) storage, locked key storage, etc.  
Specifically designed for use in 3-volt systems, the AT25DQ321A supports read, program, and erase operations  
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.  
2
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
2.  
Pin Descriptions and Pinouts  
Table 2-1.  
Pin Descriptions  
Asserted  
Symbol  
Name and Function  
State  
Type  
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is  
deasserted, the device will be deselected and normally be placed in standby  
mode (not Deep Power-Down mode), and the SO pin will be in a high-  
impedance state. When the device is deselected, data will not be accepted on  
the SI pin.  
CS  
Low  
Input  
A high-to-low transition on the CS pin is required to start an operation, and a  
low-to-high transition is required to end an operation. When ending an internally  
self-timed operation such as a program or erase cycle, the device will not enter  
the standby mode until the completion of the operation.  
SERIAL CLOCK: This pin is used to provide a clock to the device and is used  
to control the flow of data to and from the device. Command, address, and input  
data present on the SI pin or I/O pins is always latched in on the rising edge of  
SCK, while output data on the SO pin or I/O pins is always clocked out on the  
falling edge of SCK.  
SCK  
-
Input  
SERIAL INPUT (I/O0): The SI pin is used to shift data into the device. The SI  
pin is used for all data input including command and address sequences. Data  
on the SI pin is always latched in on the rising edge of SCK.  
With the Dual-Input and Quad-Input Byte/Page Program commands, the SI pin  
is used as an input pin (I/O0) in conjunction with other pins to allow two bits (on  
I/O1-0) or four bits (on I/O3-0) of data to be clocked in on every rising edge of  
SCK. With the Dual-Output and Quad-Output Read Array commands, the SI pin  
becomes an output pin (I/O0) and, along with other pins, allows two bits (on I/O1-  
0) or four bits (on I/O3-0) of data to be clocked out on every falling edge of SCK.  
To maintain consistency with SPI nomenclature, the SI (I/O0) pin will be  
referenced as SI throughout the document with exception to sections dealing  
with the Dual-Input and Quad-Input Byte/Page Program commands as well as  
the Dual-Output and Quad-Output Read Array commands in which it will be  
referenced as I/O0.  
SI (I/O0)  
-
Input/Output  
Data present on the SI pin will be ignored whenever the device is deselected  
(CS is deasserted).  
SERIAL OUTPUT (I/O1): The SO pin is used to shift data out from the device.  
Data on the SO pin is always clocked out on the falling edge of SCK.  
With the Dual-Input and Quad-Input Byte/Page Program commands, the SO pin  
becomes an input pin (I/O1) and, along with other pins, allows two bits (on I/O1-0  
)
or four bits (on I/O3-0) of data to be clocked in on every rising edge of SCK. With  
the Dual-Output and Quad-Output Read Array commands, the SO pin is used  
as an output pin (I/O1) in conjunction with other pins to allow two bits (on I/O1-0  
)
SO (I/O1)  
or four bits (on I/O3-0) of data to be clocked out on every falling edge of SCK. To  
maintain consistency with SPI nomenclature, the SO (I/O1) pin will be  
referenced as SO throughout the document with exception to sections dealing  
with the Dual-Input and Quad-Input Byte/Page Program commands as well as  
the Dual-Output and Quad-Output Read Array commands in which it will be  
referenced as I/O1.  
-
Input/Output  
The SO pin will be in a high-impedance state whenever the device is deselected  
(CS is deasserted).  
3
8718A–DFLASH–04/10  
Table 2-1.  
Symbol  
Pin Descriptions (Continued)  
Asserted  
State  
Name and Function  
Type  
WRITE PROTECT (I/O2): The WP# pin controls the hardware locking feature of  
the device. See “Protection Commands and Features” on page 23. for more  
details on protection features and the WP pin.  
With the Quad-Input Byte/Page Program command, the WP pin becomes an  
input pin (I/O2) and, along with other pins, allows four bits (on I/O3-0) of data to  
be clocked in on every rising edge of SCK. With the Quad-Output Read Array  
command, the WP pin becomes an output pin (I/O2) and, when used with other  
pins, allows four bits (on I/O3-0) of data to be clocked out on every falling edge of  
SCK. The QE bit in the Configuration Register must be set in order for the WP  
pin to be used as an I/O data pin.  
WP (I/O2)  
Low  
Input/Output  
The WP pin must be driven at all times or pulled-high using an external pull-up  
resistor.  
HOLD (I/O3): The HOLD pin is used to temporarily pause serial communication  
without deselecting or resetting the device. While the HOLD pin is asserted,  
transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin  
will be in a high-impedance state.  
The CS pin must be asserted, and the SCK pin must be in the low state in order  
for a Hold condition to start. A Hold condition pauses serial communication only  
and does not have an affect on internally self-timed operations such as a  
program or erase cycle. See “Hold” on page 49. for additional details on the  
Hold operation.  
HOLD (I/O3)  
Low  
Input/Output  
With the Quad-Input Byte/Page Program command, the HOLD pin becomes an  
input pin (I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to  
be clocked in on every rising edge of SCK. With the Quad-Output Read Array  
command, the HOLD pin becomes an output pin (I/O3) and, when used with  
other pins, allows four bits (on I/O3-0) of data to be clocked out on every falling  
edge of SCK. The QE bit in the Configuration Register must be set in order for  
the HOLD pin to be used as an I/O data pin.  
The HOLD pin must be driven at all times or pulled-high using an external pull-  
up resistor.  
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to  
the device.  
VCC  
-
-
Power  
Power  
Operations at invalid VCC voltages may produce spurious results and should not  
be attempted.  
GROUND: The ground reference for the power supply. GND should be  
connected to the system ground.  
GND  
Figure 2-1. Pin Configurations  
8-UDFN  
8-SOIC  
16-SOIC  
16  
8
7
6
5
1
2
3
4
CS  
SO (I/O1)  
WP (I/O2)  
GND  
VCC  
CS  
SO (I/O1)  
WP (I/O2)  
GND  
VCC  
1
2
3
4
8
7
6
5
NC  
VCC  
NC  
NC  
NC  
NC  
CS  
SO  
1
2
3
4
5
6
7
8
SCK  
SI  
HOLD (I/O3)  
SCK  
HOLD (I/O3)  
SCK  
15  
14  
13  
12  
11  
10  
9
NC  
NC  
NC  
NC  
GND  
WP  
SI (I/O0)  
SI (I/O0)  
4
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
3.  
Block Diagram  
Figure 3-1. Block Diagram  
CONTROL AND  
PROTECTION LOGIC  
I/O BUFFERS  
AND LATCHES  
CS  
SRAM  
DATA BUFFER  
SCK  
INTERFACE  
CONTROL  
AND  
LOGIC  
SI (I/O )  
0
Y-DECODER  
Y-GATING  
SO (I/O )  
1
FLASH  
MEMORY  
ARRAY  
WP (I/O )  
2
X-DECODER  
HOLD (I/O )  
3
Note: I/O  
pin naming convention is used for Dual-I/O and Quad-I/O commands  
3-0  
4.  
Memory Array  
To provide the greatest flexibility, the memory array of the AT25DQ321A can be erased in four levels of granularity  
including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which  
each sector can be individually protected from program and erase operations. The size of the physical sectors is  
optimized for both code and data storage applications, allowing both code and data segments to reside in their own  
isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the  
breakdown of each physical sector.  
5
8718A–DFLASH–04/10  
Figure 4-1. Memory Architecture Diagram  
Block Erase Detail  
Page Program Detail  
Internal Sectoring for  
Sector Protection  
Function  
64KB  
Block Erase  
32KB  
Block Erase  
4KB  
Block Erase  
1-256 Byte  
Page Program  
(02h Command)  
Block Address  
Range  
Page Address  
Range  
(D8h Command) (52h Command) (20h Command)  
3FFFFFh – 3FF000h  
3FEFFFh – 3FE000h  
3FDFFFh – 3FD000h  
3FCFFFh – 3FC000h  
3FBFFFh – 3FB000h  
3FAFFFh – 3FA000h  
3F9FFFh – 3F9000h  
3F8FFFh – 3F8000h  
3F7FFFh – 3F7000h  
3F6FFFh – 3F6000h  
3F5FFFh – 3F5000h  
3F4FFFh – 3F4000h  
3F3FFFh – 3F3000h  
3F2FFFh – 3F2000h  
3F1FFFh – 3F1000h  
3F0FFFh – 3F0000h  
3EFFFFh – 3EF000h  
3EEFFFh – 3EE000h  
3EDFFFh – 3ED000h  
3ECFFFh – 3EC000h  
3EBFFFh – 3EB000h  
3EAFFFh – 3EA000h  
3E9FFFh – 3E9000h  
3E8FFFh – 3E8000h  
3E7FFFh – 3E7000h  
3E6FFFh – 3E6000h  
3E5FFFh – 3E5000h  
3E4FFFh – 3E4000h  
3E3FFFh – 3E3000h  
3E2FFFh – 3E2000h  
3E1FFFh – 3E1000h  
3E0FFFh – 3E0000h  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
3FFFFFh – 3FFF00h  
3FFEFFh – 3FFE00h  
3FFDFFh – 3FFD00h  
3FFCFFh – 3FFC00h  
3FFBFFh – 3FFB00h  
3FFAFFh – 3FFA00h  
3FF9FFh – 3FF900h  
3FF8FFh – 3FF800h  
3FF7FFh – 3FF700h  
3FF6FFh – 3FF600h  
3FF5FFh – 3FF500h  
3FF4FFh – 3FF400h  
3FF3FFh – 3FF300h  
3FF2FFh – 3FF200h  
3FF1FFh – 3FF100h  
3FF0FFh – 3FF000h  
3FEFFFh – 3FEF00h  
3FEEFFh – 3FEE00h  
3FEDFFh – 3FED00h  
3FECFFh – 3FEC00h  
3FEBFFh – 3FEB00h  
3FEAFFh – 3FEA00h  
3FE9FFh – 3FE900h  
3FE8FFh – 3FE800h  
4KB  
4KB  
4KB  
4KB  
32KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
64KB  
(Sector 63)  
64KB  
4KB  
32KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
32KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
64KB  
(Sector 62)  
64KB  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
256 Bytes  
0017FFh – 001700h  
0016FFh – 001600h  
0015FFh – 001500h  
0014FFh – 001400h  
0013FFh – 001300h  
0012FFh – 001200h  
0011FFh – 001100h  
0010FFh – 001000h  
000FFFh – 000F00h  
000EFFh – 000E00h  
000DFFh – 000D00h  
000CFFh – 000C00h  
000BFFh – 000B00h  
000AFFh – 000A00h  
0009FFh – 000900h  
0008FFh – 000800h  
0007FFh – 000700h  
0006FFh – 000600h  
0005FFh – 000500h  
0004FFh – 000400h  
0003FFh – 000300h  
0002FFh – 000200h  
0001FFh – 000100h  
0000FFh – 000000h  
4KB  
32KB  
4KB  
4KB  
4KB  
4KB  
00FFFFh – 00F000h  
00EFFFh – 00E000h  
00DFFFh – 00D000h  
00CFFFh – 00C000h  
00BFFFh – 00B000h  
00AFFFh – 00A000h  
009FFFh – 009000h  
008FFFh – 008000h  
007FFFh – 007000h  
006FFFh – 006000h  
005FFFh – 005000h  
004FFFh – 004000h  
003FFFh – 003000h  
002FFFh – 002000h  
001FFFh – 001000h  
000FFFh – 000000h  
4KB  
4KB  
4KB  
4KB  
32KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
4KB  
64KB  
(Sector 0)  
64KB  
4KB  
32KB  
4KB  
4KB  
4KB  
4KB  
6
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
5.  
Device Operation  
The AT25DQ321A is controlled by a set of instructions that are sent from a host controller, commonly referred to as  
the SPI Master. The SPI Master communicates with the AT25DQ321A via the SPI bus which is comprised of four  
signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).  
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect  
to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The  
AT25DQ321A supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI  
Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode  
and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and  
always output on the falling edge of SCK.  
Figure 5-1. SPI Mode 0 and 3  
CS  
SCK  
06%  
/6%  
SI  
06%  
/6%  
SO  
5.1  
Dual-I/O and Quad-I/O Operation  
The AT25DQ321A features a dual-input program mode and a dual-output read mode that allows two bits of data to  
be clocked into or out of the device every clock cycle to improve throughputs. To accomplish this, both the SI and  
SO pins are utilized as inputs/outputs for the transfer of data bytes. With the Dual-Input Byte/Page Program  
command, the the SO pin becomes an input along with the SI pin. Alternatively, with the Dual-Output Read Array  
command, the SI pin becomes an output along with the SO pin. For both Dual-I/O commands, the SO pin will be  
referred to as I/O1 and the SI pin will be referred to as I/O0.  
The device also supports a quad-input program mode and a quad-output read mode in which the WP and HOLD  
pins become data pins for even higher throughputs. For the Quad-Input Byte/Page Program command and for the  
Quad-Output Read Array command, the HOLD, WP, SO, and SI pins are referred to as I/O3-0 where HOLD  
becomes I/O3, WP becomes I/O2, SO becomes I/O1, and SI becomes I/O0. The QE bit in the Configuration  
Register must be set in order for both Quad-I/O commands to be enabled and for the HOLD and WP pins to be  
converted to I/O data pins.  
7
8718A–DFLASH–04/10  
6.  
Commands and Addressing  
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been  
asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode,  
instruction dependent information such as address and data bytes would then be clocked out by the host controller.  
All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended  
by deasserting the CS pin.  
Opcodes not supported by the AT25DQ321A will be ignored by the device and no operation will be started. The  
device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being  
deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address  
information is sent to the device, then no operation will be performed and the device will simply return to the idle  
state and wait for the next operation.  
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.  
Since the upper address limit of the AT25DQ321A memory array is 3FFFFFh, address bits A23-A22 are always  
ignored by the device.  
Table 6-1.  
Command Listing  
Clock  
Frequency  
Address  
Bytes  
Dummy  
Bytes  
Data  
Bytes  
Command  
Opcode  
Read Commands  
1Bh  
0Bh  
03h  
3Bh  
6Bh  
0001 1011  
Up to 100 MHz  
Up to 85 MHz  
Up to 33 MHz  
Up to 70 MHz  
Up to 70 MHz  
3
3
3
3
3
2
1
0
1
1
1+  
1+  
1+  
1+  
1+  
Read Array  
0000 1011  
0000 0011  
0011 1011  
0110 1011  
Dual-Output Read Array  
Quad-Output Read Array  
Program and Erase Commands  
Block Erase (4 KBytes)  
20h  
52h  
D8h  
60h  
C7h  
02h  
A2h  
32h  
B0h  
D0h  
0010 0000  
0101 0010  
1101 1000  
0110 0000  
1100 0111  
0000 0010  
1010 0010  
0011 0010  
1011 0000  
1101 0000  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
3
3
3
0
0
3
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Block Erase (32 KBytes)  
Block Erase (64 KBytes)  
0
0
Chip Erase  
0
Byte/Page Program (1 to 256 Bytes)  
Dual-Input Byte/Page Program (1 to 256 Bytes)  
Quad-Input Byte/Page Program (1 to 256 Bytes)  
Program/Erase Suspend  
Program/Erase Resume  
Protection Commands  
1+  
1+  
1+  
0
0
Write Enable  
06h  
04h  
36h  
39h  
0000 0110  
0000 0100  
0011 0110  
0011 1001  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
0
0
3
3
0
0
0
0
0
0
0
0
Write Disable  
Protect Sector  
Unprotect Sector  
Global Protect/Unprotect  
Use Write Status Register Byte 1 Command  
8
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
Table 6-1.  
Command  
Command Listing (Continued)  
Clock  
Frequency  
Address  
Bytes  
Dummy  
Bytes  
Data  
Bytes  
Opcode  
0011 1100  
Read Sector Protection Registers  
3Ch  
Up to 100 MHz  
3
0
1+  
Security Commands  
Sector Lockdown  
33h  
34h  
35h  
9Bh  
77h  
0011 0011  
0011 0100  
0011 0101  
1001 1011  
0111 0111  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
3
3
3
3
3
0
0
0
0
2
1
Freeze Sector Lockdown State  
Read Sector Lockdown Registers  
Program OTP Security Register  
Read OTP Security Register  
Status and Configuration Register Commands  
Read Status Register  
1
1+  
1+  
1+  
05h  
01h  
31h  
3Fh  
3Eh  
0000 0101  
0000 0001  
0011 0001  
0011 1111  
0011 1110  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
Up to 100 MHz  
0
0
0
0
0
0
0
0
0
0
1+  
1
Write Status Register Byte 1  
Write Status Register Byte 2  
Read Configuration Register  
Write Configuration Register  
Miscellaneous Commands  
Reset  
1
1+  
1
F0h  
9Fh  
B9h  
ABh  
1111 0000  
1001 1111  
1011 1001  
1010 1011  
Up to 100 MHz  
Up to 85 MHz  
Up to 100 MHz  
Up to 100 MHz  
0
0
0
0
0
0
0
0
1
1 to 4  
0
Read Manufacturer and Device ID  
Deep Power-Down  
Resume from Deep Power-Down  
0
7.  
Read Commands  
7.1  
Read Array  
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply  
providing the clock signal once the initial starting address has been specified. The device incorporates an internal  
address counter that automatically increments on every clock cycle.  
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends  
on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at  
any clock frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency  
read operations up to the maximum specified by fRDLF. The 1Bh opcode allows the highest read performance  
possible and can be used at any clock frequency up to the maximum specified by fMAX; however, use of the 1Bh  
opcode at clock frequencies above fCLK should be reserved to systems employing the RapidS protocol.  
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or  
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be  
clocked in to specify the starting address location of the first byte to read within the memory array. Following the  
three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode  
is used for the Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the  
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in after  
the address bytes.  
9
8718A–DFLASH–04/10  
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,  
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a  
byte first. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back  
at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array  
to the beginning of the array.  
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS  
pin can be deasserted at any time and does not require that a full byte of data be read.  
Figure 7-1. Read Array – 1Bh Opcode  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ ꢇꢃ ꢇꢂ ꢇꢀ ꢇꢁ ꢇꢇ ꢇꢆ ꢇꢄ ꢇꢅ ꢇꢉ ꢇꢈ ꢆꢃ ꢆꢂ ꢆꢀ ꢆꢁ ꢆꢇ ꢆꢆ ꢆꢄ  
SCK  
SI  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
'21ꢌ7ꢊ&$5(  
'21ꢌ7ꢊ&$5(  
ꢃ
06%  
ꢃ
ꢃ
ꢂ
ꢂ
ꢃ
ꢂ
ꢂ
$
06%  
$
$
$
$
$
$
$
$
;
06%  
;
;
;
;
;
;
;
;
06%  
;
;
;
;
;
;
;
'$7$ꢊ%<7(ꢊꢂ  
+,*+ꢋ,03('$1&(  
'
06%  
'
'
'
'
'
'
'
'
06%  
'
SO  
Figure 7-2. Read Array – 0Bh Opcode  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ ꢇꢃ ꢇꢂ ꢇꢀ ꢇꢁ ꢇꢇ ꢇꢆ ꢇꢄ ꢇꢅ ꢇꢉ  
SCK  
SI  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
$
'21ꢌ7ꢊ&$5(  
ꢃ
06%  
ꢃ
ꢃ
ꢃ
ꢂ
ꢃ
ꢂ
ꢂ
$
06%  
$
$
$
$
$
$
$
;
06%  
;
;
;
;
;
;
;
'$7$ꢊ%<7(ꢊꢂ  
+,*+ꢋ,03('$1&(  
'
06%  
'
'
'
'
'
'
'
'
06%  
'
SO  
Figure 7-3. Read Array – 03h Opcode  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ ꢇꢃ  
SCK  
SI  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
ꢃ
06%  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢂ
ꢂ
$
06%  
$
$
$
$
$
$
$
$
'$7$ꢊ%<7(ꢊꢂ  
+,*+ꢋ,03('$1&(  
'
06%  
'
'
'
'
'
'
'
'
06%  
'
SO  
10  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
7.2  
Dual-Output Read Array  
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to  
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial  
starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read  
Array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.  
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by fRDDO  
.
To perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must  
be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to  
specify the starting address location of the first byte to read within the memory array. Following the three address  
bytes, a single dummy byte must also be clocked into the device.  
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data  
being output on both the I/O1 and I/O0 pins. The data is always output with the MSB of a byte first, and the MSB is  
always output on the I/O1 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O1 pin  
while bit 6 of the same data byte will be output on the I/O0 pin. During the next clock cycle, bits 5 and 4 of the first  
data byte will be output on the I/O1 and I/O0 pins, respectively. The sequence continues with each byte of data  
being output after every four clock cycles. When the last byte (3FFFFFh) of the memory array has been read, the  
device will continue reading back at the beginning of the array (000000h). No delays will be incurred when  
wrapping around from the end of the array to the beginning of the array.  
Deasserting the CS pin will terminate the read operation and put the I/O1-0 pins into a high-impedance state. The  
CS pin can be deasserted at any time and does not require that a full byte of data be read.  
Figure 7-4. Dual-Output Read Array  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ ꢇꢃ ꢇꢂ ꢇꢀ ꢇꢁ ꢇꢇ ꢇꢆ ꢇꢄ ꢇꢅ ꢇꢉ  
SCK  
SI (I/O0)  
SO (I/O1)  
287387  
287387  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
'21ꢌ7ꢊ&$5(  
'$7$ꢊ%<7(ꢊꢂ '$7$ꢊ%<7(ꢊꢀ  
ꢃ
06%  
ꢃ
ꢂ
ꢂ
ꢂ
ꢃ
ꢂ
ꢂ
$
06%  
$
$
$
$
$
$
$
$
;
06%  
;
;
;
;
;
;
;
'
'
'
'
'
'
'
'
'
'
'
ꢇꢊ  
'
'
'
'
'
'
'
'
ꢄꢊ  
ꢅꢊ  
ꢇꢊ  
ꢆꢊ  
ꢀꢊ  
ꢁꢊ  
ꢃꢊ  
ꢄꢊ  
ꢀꢊ  
ꢃꢊ  
ꢂꢊ  
ꢄꢊ  
ꢇ
ꢆ
+,*+ꢋ,03('$1&(  
'
ꢆꢊ  
ꢂꢊ  
ꢅꢊ  
ꢁꢊ  
ꢅꢊ  
06%  
06%  
7.3  
Quad-Output Read Array  
The Quad-Output Read Array command is similar to the Dual-Output Read Array command and can be used to  
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial  
starting address has been specified. Unlike the Dual-Output Read Array command, however, the Quad-Output  
Read Array command allows four bits of data to be clocked out of the device on every clock cycle rather than two.  
The Quad-Output Read Array command can be used at any clock frequency up to the maximum specified by  
fRDQO. To perform the Quad-Output Read Array operation, the CS pin must first be asserted and the opcode of 6Bh  
must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in  
to specify the starting address location of the first byte to read within the memory array. Following the three  
address bytes, a single dummy byte must also be clocked into the device.  
11  
8718A–DFLASH–04/10  
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data  
being output on the I/O3-0 pins. The data is always output with the MSB of a byte first, and the MSB is always  
output on the I/O3 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits  
6, 5, and 4 of the same data byte will be output on the I/O2, I/O1, and I/O0 pins, respectively. During the next clock  
cycle, bits 3, 2, 1, and 0 of the first data byte will be output on the I/O3, I/O2, I/O1, and I/O0 pins, respectively. The  
sequence continues with each byte of data being output after every two clock cycles. When the last byte  
(3FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array  
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the  
array.  
Deasserting the CS pin will terminate the read operation and put the I/O3-0 pins into a high-impedance state. The  
CS pin can be deasserted at any time and does not require that a full byte of data be read.  
Figure 7-5. Quad-Output Read Array  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ ꢇꢃ ꢇꢂ ꢇꢀ ꢇꢁ ꢇꢇ ꢇꢆ ꢇꢄ ꢇꢅ ꢇꢉ  
%<7(ꢊꢂ %<7(ꢊꢀ %<7(ꢊꢁ %<7(ꢊꢇ %<7(ꢊꢆ  
SCK  
287  
287  
287  
287  
287  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
'21ꢌ7ꢊ&$5(  
ꢃ
06%  
ꢂ
ꢂ
ꢃ
ꢂ
ꢃ
ꢂ
ꢂ
$
06%  
$
$
$
$
$
$
$
$
;
06%  
;
;
;
;
;
;
;
'
'
'
'
ꢃꢊ  
'
ꢇꢊ  
'
'
'
'
ꢇꢊ  
'
ꢇꢊ  
ꢃꢊ  
ꢇꢊ  
ꢃꢊ  
ꢇꢊ  
ꢃꢊ  
ꢃ
I/O0  
(SI)  
+,*+ꢋ,03('$1&(  
+,*+ꢋ,03('$1&(  
+,*+ꢋ,03('$1&(  
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
ꢆꢊ  
ꢂꢊ  
ꢆꢊ  
ꢂꢊ  
ꢆꢊ  
ꢂꢊ  
ꢆꢊ  
ꢂꢊ  
ꢆꢊ  
ꢂ
I/O1  
(SO)  
'
'
'
'
ꢄꢊ  
ꢅꢊ  
ꢀꢊ  
ꢁꢊ  
ꢄꢊ  
ꢅꢊ  
ꢀꢊ  
ꢄꢊ  
ꢀꢊ  
ꢁꢊ  
ꢄꢊ  
ꢅꢊ  
ꢀꢊ  
ꢁꢊ  
ꢄꢊ  
ꢀ
ꢁ
I/O2  
(WP)  
ꢁꢊ  
ꢅꢊ  
ꢅꢊ  
I/O3  
(HOLD)  
06%  
06%  
06%  
06%  
06%  
8.  
Program and Erase Commands  
8.1  
Byte/Page Program  
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be  
programmed into previously erased memory locations. An erased memory location is one that has all eight bits set  
to the logical “1” state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write  
Enable command must have been previously issued to the device (see “Write Enable” on page 23) to set the Write  
Enable Latch (WEL) bit of the Status Register to a logical “1” state.  
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the  
three address bytes denoting the first byte location of the memory array to begin programming at. After the address  
bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer.  
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are  
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this  
situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the  
12  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes  
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and  
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page  
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In  
addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into  
the internal buffer.  
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the  
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data  
bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the  
page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is  
internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.  
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin  
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the  
device will abort the operation and no data will be programmed into the memory array. In addition, if the address  
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”  
on page 25) or locked down (see “Sector Lockdown” on page 31), then the Byte/Page Program command will not  
be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the  
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address  
being sent, an incomplete byte of data being sent, the CS pin being deasserted on non-byte boundaries, or  
because the memory location to be programmed is protected or locked down.  
While the device is programming, the Status Register can be read and will indicate that the device is busy. For  
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to  
determine if the data bytes have finished programming. At some point before the program cycle completes, the  
WEL bit in the Status Register will be reset back to the logical “0” state.  
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to  
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.  
Figure 8-1. Byte Program  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ  
SCK  
SI  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
'$7$ꢊ,1  
ꢃ
06%  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢂ
ꢃ
$
06%  
$
$
$
$
$
$
$
$
'
06%  
'
'
'
'
'
'
'
+,*+ꢋ,03('$1&(  
SO  
13  
8718A–DFLASH–04/10  
Figure 8-2. Page Program  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ  
SCK  
SI  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
'$7$ꢊ,1ꢊ%<7(ꢊꢂ  
'$7$ꢊ,1ꢊ%<7(ꢊQ  
ꢃ
06%  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢂ
ꢃ
$
$
$
$
$
$
'
06%  
'
'
'
'
'
'
'
'
06%  
'
'
'
'
'
'
'
06%  
+,*+ꢋ,03('$1&(  
SO  
8.2  
Dual-Input Byte/Page Program  
The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be  
used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory  
locations. Unlike the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program  
command allows two bits of data to be clocked into the device on every clock cycle rather than just one.  
Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been  
previously issued to the device (see “Write Enable” on page 23) to set the Write Enable Latch (WEL) bit of the  
Status Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h  
must be clocked into the device followed by the three address bytes denoting the first byte location of the memory  
array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the  
device two bits at a time on both the I/O1 and I/O0 pins.  
The data is always input with the MSB of a byte first, and the MSB is always input on the I/O1 pin. During the first  
clock cycle, bit 7 of the first data byte would be input on the I/O1 pin while bit 6 of the same data byte would be input  
on the I/O0 pin. During the next clock cycle, bits 5 and 4 of the first data byte would be input on the I/O1 and I/O0  
pins, respectively. The sequence would continue with each byte of data being input after every four clock cycles.  
Like the standard Byte/Page Program command, all data clocked into the device is stored in an internal buffer.  
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are  
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this  
situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the  
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes  
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and  
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page  
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In  
addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into  
the internal buffer.  
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the  
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data  
bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the  
page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is  
internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.  
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin  
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the  
14  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
device will abort the operation and no data will be programmed into the memory array. In addition, if the address  
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”  
on page 25) or locked down (see “Sector Lockdown” on page 31), then the Byte/Page Program command will not  
be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the  
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address  
being sent, an incomplete byte of data being sent, the CS pin being deasserted on non-byte boundaries, or  
because the memory location to be programmed is protected or locked down.  
While the device is programming, the Status Register can be read and will indicate that the device is busy. For  
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to  
determine if the data bytes have finished programming. At some point before the program cycle completes, the  
WEL bit in the Status Register will be reset back to the logical “0” state.  
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to  
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.  
Figure 8-3. Dual-Input Byte Program  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ  
,1387  
SCK  
SI (I/O0)  
SO (I/O1)  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
'$7$ꢊ%<7(  
'
'
'
'
ꢂ
06%  
ꢃ
ꢂ
ꢃ
ꢃ
ꢃ
ꢂ
ꢃ
$
06%  
$
$
$
$
$
$
$
$
ꢄ
ꢇ
ꢀ
ꢃ
ꢂ
+,*+ꢋ,03('$1&(  
'
'
'
'
ꢅ
ꢆ
ꢁ
06%  
Figure 8-4. Dual-Input Page Program  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ ꢁꢅ ꢁꢉ ꢁꢈ  
SCK  
SI (I/O0)  
SO (I/O1)  
,1387  
,1387  
,1387  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
'$7$ꢊ%<7(ꢊꢂ '$7$ꢊ%<7(ꢊꢀ  
'$7$ꢊ%<7(ꢊQ  
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
ꢂ
06%  
ꢃ
ꢂ
ꢃ
ꢃ
ꢃ
ꢂ
ꢃ
$
06%  
$
$
$
$
$
$
$
$
ꢄ
ꢅ
ꢇ
ꢆ
ꢀ
ꢁ
ꢃ
ꢂ
ꢄ
ꢅ
ꢇ
ꢆ
ꢀ
ꢁ
ꢃ
ꢂ
ꢄ
ꢇ
ꢀ
ꢃ
+,*+ꢋ,03('$1&(  
'
'
'
'
'
'
ꢅ
ꢆ
ꢁ
ꢂ
06%  
06%  
06%  
15  
8718A–DFLASH–04/10  
8.3  
Quad-Input Byte/Page Program  
The Quad-Input Byte/Page Program command is similar to the Dual-Input Byte/Page Program command and can  
be used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory  
locations. Unlike the Dual-Input Byte/Page Program command, however, the Quad-Input Byte/Page Program  
command allows four bits of data to be clocked into the device on every clock cycle rather than two.  
Before the Quad-Input Byte/Page Program command can be started, the Write Enable command must have been  
previously issued to the device (See “Write Enable” on page 23.) to set the Write Enable Latch (WEL) bit of the  
Status Register to a logical “1” state. To perform a Quad-Input Byte/Page Program command, an opcode of 32h  
must be clocked into the device followed by the three address bytes denoting the first byte location of the memory  
array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the  
device four bits at a time on the I/O3-0 pins.  
The data is always input with the MSB of a byte first, and the MSB is always input on the I/O3 pin. During the first  
clock cycle, bit 7 of the first data byte would be input on the I/O3 pin while bits 6, 5, and 4 of the same data byte  
would be input on the I/O2, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the  
first data byte would be input on the I/O3, I/O2, I/O1, and I/O0 pins, respectively. The sequence would continue with  
each byte of data being input after every two clock cycles. Like the standard Byte/Page Program and Dual-Input  
Byte/Page Program commands, all data clocked into the device is stored in an internal buffer.  
If the starting memory address denoted by A23-A0 does not fall on a 256-byte page boundary (A7-A0 are not all 0),  
then special circumstances regarding which memory locations to be programmed will apply. In this situation, any  
data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the  
same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent  
to the device, then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the  
last byte of data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h  
through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 256  
bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer.  
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the  
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data  
bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the  
page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is  
internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.  
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin  
is deasserted, and the CS pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the  
device will abort the operation and no data will be programmed into the memory array. In addition, if the address  
specified by A23-A0 points to a memory location within a sector that is in the protected state (See “Protect Sector”  
on page 25.) or locked down (See “Sector Lockdown” on page 31.), then the Quad-Input Byte/Page Program  
command will not be executed, and the device will return to the idle state once the CS pin has been deasserted.  
The WEL bit in the Status Register will be reset back to the logical “0” state if the program cycle aborts due to an  
incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on non-byte  
boundaries, or because the memory location to be programmed is protected or locked down.  
While the device is programming, the Status Register can be read and will indicate that the device is busy. For  
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to  
determine if the data bytes have finished programming. At some point before the program cycle completes, the  
WEL bit in the Status Register will be reset back to the logical “0” state.  
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to  
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.  
16  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
Figure 8-5. Quad-Input Byte Program  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33  
BYTE  
SCK  
OPCODE  
ADDRESS BITS A23-A0  
IN  
D
D
D
D
D
0
0
1
1
0
0
1
0
A
A
A
A
A
A
A
A
A
I/O0  
(SI)  
4
5
6
7
0
1
2
3
MSB  
MSB  
HIGH-IMPEDANCE  
HIGH-IMPEDANCE  
HIGH-IMPEDANCE  
D
D
D
I/O1  
(SO)  
I/O2  
(WP)  
I/O3  
(HOLD)  
MSB  
Figure 8-6. Quad-Input Page Program  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12  
29 30 31 32 33 34 35 36 37 38 39  
BYTE 1 BYTE 2 BYTE 3 BYTE 4  
SCK  
BYTE n  
IN  
OPCODE  
ADDRESS BITS A23-A0  
IN  
IN  
IN  
IN  
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
D
1
D
2
D
3
0
0
1
1
0
0
1
0
A
A
A
A
A
A
A
A
A
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O0  
(SI)  
MSB  
MSB  
HIGH-IMPEDANCE  
HIGH-IMPEDANCE  
HIGH-IMPEDANCE  
D
D
D
D
D
D
D
D
D
D
D
D
I/O1  
(SO)  
I/O2  
(WP)  
I/O3  
(HOLD)  
MSB  
MSB  
MSB  
MSB  
MSB  
17  
8718A–DFLASH–04/10  
8.4  
Block Erase  
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one  
of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode  
of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase  
command can be started, the Write Enable command must have been previously issued to the device to set the  
WEL bit of the Status Register to a logical “1” state.  
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must  
be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address  
within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device  
will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the  
block is internally self-timed and should take place in a time of tBLKE  
.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded  
by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values  
can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored, and for a 64-Kbyte  
erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded  
by the device, the complete three address bytes must still be clocked into the device before the CS pin is  
deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device  
will abort the operation and no erase operation will be performed.  
If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked  
down state, then the Block Erase command will not be executed, and the device will return to the idle state once  
the CS pin has been deasserted.  
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an  
incomplete address being sent, the CS pin being deasserted on non-byte boundaries, or because a memory  
location within the region to be erased is protected or locked down.  
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the  
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the  
tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL  
bit in the Status Register will be reset back to the logical “0” state.  
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase  
properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.  
Figure 8-7. Block Erase  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
ꢉ
ꢈ
ꢂꢃ ꢂꢂ ꢂꢀ  
ꢀꢄ ꢀꢅ ꢀꢉ ꢀꢈ ꢁꢃ ꢁꢂ  
SCK  
SI  
23&2'(  
$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ  
&
06%  
&
&
&
&
&
&
&
$
06%  
$
$
$
$
$
$
$
$
$
$
$
+,*+ꢋ,03('$1&(  
SO  
18  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
8.5  
Chip Erase  
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip  
Erase command can be started, the Write Enable command must have been previously issued to the device to set  
the WEL bit of the Status Register to a logical “1” state.  
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device  
functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of  
the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no  
address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When  
the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-  
timed and should take place in a time of tCHPE  
.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be  
deasserted on a byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if any  
sector of the memory array is in the protected or locked down state, then the Chip Erase command will not be  
executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the  
Status Register will be reset back to the logical “0” state if the CS pin is deasserted on non-byte boundaries or if a  
sector is in the protected or locked down state.  
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the  
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the  
t
CHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the  
WEL bit in the Status Register will be reset back to the logical “0” state.  
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase  
properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.  
Figure 8-8. Chip Erase  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
SCK  
SI  
23&2'(  
&
06%  
&
&
&
&
&
&
&
+,*+ꢋ,03('$1&(  
SO  
19  
8718A–DFLASH–04/10  
8.6  
Program/Erase Suspend  
In some code plus data storage applications, it is often necessary to process certain high-level system interrupts  
that require relatively immediate reading of code or data from the Flash memory. In such an instance, it may not be  
possible for the system to wait the microseconds or milliseconds required for the Flash memory to complete a  
program or erase cycle. The Program/Erase Suspend command allows a program or erase operation in progress  
to a particular 64-Kbyte sector of the Flash memory array to be suspended so that other device operations can be  
performed. For example, by suspending an erase operation to a particular sector, the system can perform  
functions such as a program or read operation within another 64-Kbyte sector in the device. Other device  
operations, such as a Read Status Register, can also be performed while a program or erase operation is  
suspended. Table 8-1 outlines the operations that are allowed and not allowed during a program or erase suspend.  
Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need  
to be issued prior to the Program/Erase Suspend command being issued. Therefore, the Program/Erase Suspend  
command operates independently of the state of the WEL bit in the Status Register.  
To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of B0h must be clocked  
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will  
be ignored. When the CS pin is deasserted, the program or erase operation currently in progress will be  
suspended within a time of tSUSP. The Program Suspend (PS) bit or the Erase Suspend (ES) bit in the Status  
Register will then be set to the logical “1” state to indicate that the program or erase operation has been  
suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is ready for another  
operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin  
must be deasserted on non-byte boundary (multiples of eight bits); otherwise, no suspend operation will be  
performed.  
If the Program/Erase Suspend command is issued while the device is not busy performing a program or erase  
operation, (CRDY/BSY is in the logic “1” state), then the device is simply ignore the Program/Erase Suspend  
command and the PS and ES bits in the status Register will indicate that the device is not in a suspend state, (PS  
and ES will be a logic “0”).  
Read operations are not allowed to a 64-Kbyte sector that has had its program or erase operation suspended. If a  
read is attempted to a suspended sector, then the device will output undefined data. Therefore, when performing a  
Read Array operation to an unsuspended sector and the device’s internal address counter increments and crosses  
the sector boundary to a suspended sector, the device will then start outputting undefined data continuously until  
the address counter increments and crosses a sector boundary to an unsuspended sector.  
A program operation is not allowed to a sector that has been erase suspended. If a program operation is attempted  
to an erase suspended sector, then the program operation will abort and the WEL bit in the Status Register will be  
reset back to the logical “0” state. Likewise, an erase operation is not allowed to a sector that has been program  
suspended. If attempted, the erase operation will abort and the WEL bit in the Status Register will be reset to a  
logical “0” state.  
During an Erase Suspend, a program operation to a different 64-Kbyte sector can be started and subsequently  
suspended. This results in a simultaneous Erase Suspend/Program Suspend condition and will be indicated by the  
states of both the ES and PS bits in the Status Register being set to the logical “1” state.  
If a Reset operation (see “Reset” on page 44) is performed while a sector is erase suspended, the suspend  
operation will abort and the contents of the block in the suspended sector will be left in an undefined state.  
However, if a Reset is performed while a sector is program suspended, the suspend operation will abort but only  
the contents of the page that was being programmed and subsequently suspended will be undefined. The  
remaining pages in the 64-Kbyte sector will retain their previous contents.  
20  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a  
Protect Sector operation, then the device will simply ignore the opcode and no operation will be performed. The  
state of the WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE  
(Sector Lockdown Enabled) bits, will not be affected.  
Table 8-1.  
Operations Allowed and Not Allowed During a Program or Erase Suspend.  
Operation During  
Program Suspend  
Operation During  
Erase Suspend  
Command  
Read Commands  
Read Array (All Opcodes)  
Allowed  
Allowed  
Program and Erase Commands  
Block Erase  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
Allowed  
Not Allowed  
Not Allowed  
Allowed  
Chip Erase  
Byte/Page Program (All Opcodes)  
Program/Erase Suspend  
Program/Erase Resume  
Protection Commands  
Write Enable  
Allowed  
Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
Allowed  
Allowed  
Allowed  
Write Disable  
Protect Sector  
Not Allowed  
Not Allowed  
Not Allowed  
Allowed  
Unprotect Sector  
Global Protect/Unprotect  
Read Sector Protection Registers  
Security Commands  
Sector Lockdown  
Not Allowed  
Not Allowed  
Allowed  
Not Allowed  
Not Allowed  
Allowed  
Freeze Sector Lockdown State  
Read Sector Lockdown Registers  
Program OTP Security Register  
Read OTP Security Register  
Status and Configuration Register Commands  
Read Status Register  
Not Allowed  
Allowed  
Not Allowed  
Allowed  
Allowed  
Not Allowed  
Allowed  
Allowed  
Not Allowed  
Allowed  
Write Status Register (All Opcodes)  
Read Configuration Register  
Write Configuration Register  
Miscellaneous Commands  
Reset  
Not Allowed  
Not Allowed  
Allowed  
Allowed  
Allowed  
Allowed  
Read Manufacturer and Device ID  
Deep Power-Down  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
Resume from Deep Power-Down  
21  
8718A–DFLASH–04/10  
Figure 8-9. Program/Erase Suspend  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
SCK  
SI  
23&2'(  
ꢂ
06%  
ꢃ
ꢂ
ꢂ
ꢃ
ꢃ
ꢃ
ꢃ
+,*+ꢋ,03('$1&(  
SO  
8.7  
Program/Erase Resume  
The Program/Erase Resume command allows a suspended program or erase operation to be resumed and  
continue programming a Flash page or erasing a Flash memory block where it left off. As with the Program/Erase  
Suspend command, the Write Enable command does not need to be issued prior to the Program/Erase Resume  
command being issued. Therefore, the Program/Erase Resume command operates independently of the state of  
the WEL bit in the Status Register.  
To perform a Program/Erase Resume, the CS pin must first be asserted and the opcode of D0h must be clocked  
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will  
be ignored. When the CS pin is deasserted, the program or erase operation currently suspended will be resumed  
within a time of tRES. The PS bit or the ES bit in the Status Register will then be reset back to the logical “0” state to  
indicate that the program or erase operation is no longer suspended. In addition, the RDY/BSY bit in the Status  
Register will indicate that the device is busy performing a program or erase operation. The complete opcode must  
be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary  
(multiples of eight bits); otherwise, no resume operation will be performed.  
During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command  
will result in the program operation resuming first. After the program operation has been completed, the  
Program/Erase Resume command must be issued again in order for the erase operation to be resumed.  
While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase  
Suspend command will be ignored. Therefore, if a resumed program or erase operation needs to be subsequently  
suspended again, the system must either wait the entire tRES time before issuing the Program/Erase Suspend  
command, or it must check the status of the RDY/BSY bit or the appropriate PS or ES bit in the Status Register to  
determine if the previously suspended program or erase operation has resumed.  
Figure 8-10. Program/Erase Resume  
CS  
ꢃ
ꢂ
ꢀ
ꢁ
ꢇ
ꢆ
ꢄ
ꢅ
SCK  
SI  
23&2'(  
ꢂ
06%  
ꢂ
ꢃ
ꢂ
ꢃ
ꢃ
ꢃ
ꢃ
+,*+ꢋ,03('$1&(  
SO  
22  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
9.  
Protection Commands and Features  
9.1  
Write Enable  
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1”  
state. The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector  
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status Register, or Write  
Configuration Register command can be executed. This makes the issuance of these commands a two step  
process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in  
the Status Register is not set prior to the issuance of one of these commands, then the command will not be  
executed.  
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into  
the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be  
ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The  
complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be  
deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and  
the state of the WEL bit will not change.  
Figure 9-1. Write Enable  
CS  
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SO  
23  
8718A–DFLASH–04/10  
9.2  
Write Disable  
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical  
"0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector  
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status Register, and Write  
Configuration Register commands will not be executed. Other conditions can also cause the WEL bit to be reset;  
for more details, refer to the WEL bit section of the Status Register description.  
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked  
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will  
be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The  
complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be  
deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state  
of the WEL bit will not change.  
Figure 9-2. Write Disable  
CS  
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24  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
9.3  
Protect Sector  
Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection Register that is used  
to control the software protection of a sector. Upon device power-up, each Sector Protection Register will default to  
the logical “1” state indicating that all sectors are protected and cannot be programmed or erased.  
Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection  
Register to the logical “1” state. The following table outlines the two states of the Sector Protection Registers.  
Table 9-1.  
Sector Protection Register Values  
Value  
Sector Protection Status  
0
1
Sector is unprotected and can be programmed and erased.  
Sector is protected and cannot be programmed or erased. This is the default state.  
Before the Protect Sector command can be issued, the Write Enable command must have been previously issued  
to set the WEL bit in the Status Register to a logical “1”. To issue the Protect Sector command, the CS pin must  
first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes  
designating any address within the sector to be protected. Any additional data clocked into the device will be  
ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector  
addressed by A23-A0 will be set to the logical “1” state, and the sector itself will then be protected from program  
and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state.  
The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin  
must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the  
operation. When the device aborts the Protect Sector operation, the state of the Sector Protection Register will be  
unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.  
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection  
Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of  
the Status Register (please refer to the Status Register description for more details). If the Sector Protection  
Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will  
reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been  
deasserted.  
Figure 9-3. Protect Sector  
CS  
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25  
8718A–DFLASH–04/10  
9.4  
Unprotect Sector  
Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector  
Protection Register to the logical “0” state (see Table 9-1 for Sector Protection Register values). Every physical  
sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software  
protection of a sector.  
Before the Unprotect Sector command can be issued, the Write Enable command must have been previously  
issued to set the WEL bit in the Status Register to a logical “1”. To issue the Unprotect Sector command, the CS  
pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been  
clocked in, the three address bytes designating any address within the sector to be unprotected must be clocked  
in. Any additional data clocked into the device after the address bytes will be ignored. When the CS pin is  
deasserted, the Sector Protection Register corresponding to the sector addressed by A23-A0 will be reset to the  
logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be reset  
back to the logical “0” state.  
The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin  
must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the  
state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a  
logical “0”.  
As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers  
can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status  
Register (please refer to the Status Register description for more details). If the Sector Protection Registers are  
locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the  
WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been  
deasserted.  
Figure 9-4. Unprotect Sector  
CS  
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26  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
9.5  
Global Protect/Unprotect  
The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect  
Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect  
Sector command to individually unprotect certain sectors and individually reprotect them later by using the Protect  
Sector command. Likewise, a system can globally unprotect the entire memory array and then individually protect  
certain sectors as needed.  
Performing a Global Protect or Global Unprotect is accomplished by writing a certain combination of data to the  
Status Register using the Write Status Register Byte 1 command (see “Write Status Register Byte 1” on page 40  
for command execution details). The Write Status Register command is also used to modify the SPRL (Sector  
Protection Registers Locked) bit to control hardware and software locking.  
To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met, and the system must write  
a logical “1” to bits 5, 4, 3, and 2 of the first byte of the Status Register. Conversely, to perform a Global Unprotect,  
the same WP and SPRL conditions must be met but the system must write a logical “0” to bits 5, 4, 3, and 2 of the  
first byte of the Status Register. Table 9-2 details the conditions necessary for a Global Protect or Global Unprotect  
to be performed.  
Sectors that have been erase or program suspended must remain in the unprotected state. If a Global Protect  
operation is attempted while a sector is erase or program suspended, the protection operation will abort, the  
protection states of all sectors in the Flash memory array will not change, and WEL bit in the Status Register will be  
reset back to a logical “0”.  
27  
8718A–DFLASH–04/10  
Table 9-2.  
Valid SPRL and Global Protect/Unprotect Conditions  
New Write Status  
Register Byte 1  
Data  
Current  
SPRL  
Value  
New  
SPRL  
Value  
WP  
State  
Bit  
7 6 5 4 3 2 1 0  
Protection Operation  
0 x 0 0 0 0 x x  
0 x 0 0 0 1 x x  
Global Unprotect – all Sector Protection Registers reset to 0  
No change to current protection.  
No change to current protection.  
No change to current protection.  
Global Protect – all Sector Protection Registers set to 1  
0
0
0
0
0
0 x 1 1 1 0 x x  
0 x 1 1 1 1 x x  
0
0
1
0
1
0
1 x 0 0 0 0 x x  
1 x 0 0 0 1 x x  
Global Unprotect – all Sector Protection Registers reset to 0  
No change to current protection.  
No change to current protection.  
No change to current protection.  
Global Protect – all Sector Protection Registers set to 1  
1
1
1
1
1
1 x 1 1 1 0 x x  
1 x 1 1 1 1 x x  
No change to the current protection level. All sectors currently protected will remain protected  
and all sectors currently unprotected will remain unprotected.  
x x x x x x x x  
The Sector Protection Registers are hard-locked and cannot be changed when the WP pin is  
LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur.  
In addition, the SPRL bit cannot be changed (the WP pin must be HIGH in order to change  
SPRL back to a 0).  
0 x 0 0 0 0 x x  
0 x 0 0 0 1 x x  
Global Unprotect – all Sector Protection Registers reset to 0  
No change to current protection.  
No change to current protection.  
No change to current protection.  
Global Protect – all Sector Protection Registers set to 1  
0
0
0
0
0
0 x 1 1 1 0 x x  
0 x 1 1 1 1 x x  
1 x 0 0 0 0 x x  
1 x 0 0 0 1 x x  
Global Unprotect – all Sector Protection Registers reset to 0  
No change to current protection.  
No change to current protection.  
No change to current protection.  
Global Protect – all Sector Protection Registers set to 1  
1
1
1
1
1
1 x 1 1 1 0 x x  
1 x 1 1 1 1 x x  
0 x 0 0 0 0 x x  
0 x 0 0 0 1 x x  
0
0
0
0
0
No change to the current protection level. All sectors currently protected will remain  
protected, and all sectors currently unprotected will remain unprotected.  
0 x 1 1 1 0 x x  
0 x 1 1 1 1 x x  
The Sector Protection Registers are soft-locked and cannot be changed when the  
current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur.  
However, the SPRL bit can be changed back to a 0 from a 1 since the WP pin is  
HIGH. To perform a Global Protect/Unprotect, the Write Status Register command  
must be issued again after the SPRL bit has been changed from a 1 to a 0.  
1
1
1 x 0 0 0 0 x x  
1 x 0 0 0 1 x x  
1
1
1
1
1
1 x 1 1 1 0 x x  
1 x 1 1 1 1 x x  
Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not  
locked), then writing a 00h to the first byte of the Status Register will perform a Global Unprotect without changing  
the state of the SPRL bit. Similarly, writing a 7Fh to the first byte of the Status Register will perform a Global Protect  
and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an  
FFh if software-locking or hardware-locking is desired along with the Global Protect.  
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the  
system can simply write a 0Fh to the first byte of the Status Register to change the SPRL bit from a logical “1” to a  
logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from  
28  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made to the  
Sector Protection Registers).  
When writing to the first byte of the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will be  
decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit 7, the SPRL  
bit, will actually be modified. Therefore, when reading the first byte of the Status Register, bits 5, 4, 3, and 2 will not  
reflect the values written to them but will instead indicate the status of the WP pin and the sector protection status.  
Please refer to “Read Status Register” on page 36 and Table 11-1 on page 36 for details on the Status Register  
format and what values can be read for bits 5, 4, 3, and 2.  
9.6  
Read Sector Protection Registers  
The Sector Protection Registers can be read to determine the current software protection status of each sector.  
Reading the Sector Protection Registers, however, will not determine the status of the WP pin.  
To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of  
3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address  
within the sector must be clocked in. After the last address byte has been clocked in, the device will begin  
outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte  
of either FFh or 00h to denote the value of the appropriate Sector Protection Register.  
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock  
frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the  
correct status of the appropriate Sector Protection Register.  
Table 9-3.  
Read Sector Protection Register - Output Data  
Output Data  
Sector Protection Register Value  
00h  
FFh  
Sector Protection Register value is 0 (sector is unprotected).  
Sector Protection Register value is 1 (sector is protected).  
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS  
pin can be deasserted at any time and does not require that a full byte of data be read.  
In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the  
Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to “Read  
Status Register” on page 36 for more details).  
Figure 9-5. Read Sector Protection Register  
CS  
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29  
8718A–DFLASH–04/10  
9.7  
Protected States and the Write Protect (WP) Pin  
The WP pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown  
status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers  
Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware  
locking to be active, two conditions must be met-the WP pin must be asserted and the SPRL bit must be in the  
logical “1” state.  
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked.  
Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be  
locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the  
Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the  
protection status of a sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be  
reset back to the logical “0” state using the Write Status Register command. When resetting the SPRL bit back to a  
logical “0”, it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector  
Protection Registers remain soft-locked until after the Write Status Register command has been executed.  
If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”, the only way to reset  
the bit back to the logical “0” state is to power-cycle the device. This allows a system to power-up with all sectors  
software protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and  
then hardware locked at a later time by simply setting the SPRL bit in the Status Register.  
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit in the Status  
Register can still be set to a logical “1” to lock the Sector Protection Registers. This provides a software locking  
ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. When changing  
the SPRL bit to a logical “1” from a logical “0”, it is also possible to perform a Global Protect or Global Unprotect at  
the same time by writing the appropriate values into bits 5, 4, 3, and 2 of the first byte of the Status Register.  
Tables 9-4 and 9-5 detail the various protection and locking states of the device.  
Table 9-4.  
Sector Protection Register States  
Sector Protection Register  
Sector  
n(1)  
WP  
n(1)  
0
Unprotected  
Protected  
X
(Don't Care)  
1
Note:  
1. “n” represents a sector number  
Table 9-5.  
Hardware and Software Locking  
WP  
SPRL Locking SPRL Change Allowed Sector Protection Registers  
Can be modified  
from 0 to 1  
Unlocked and modifiable using the Protect and Unprotect Sector  
commands. Global Protect and Unprotect can also be performed.  
0
0
1
0
1
Locked in current state. Protect and Unprotect Sector commands  
will be ignored. Global Protect and Unprotect cannot be  
performed.  
Hardware  
Locked  
0
1
1
Locked  
Can be modified  
from 0 to 1  
Unlocked and modifiable using the Protect and Unprotect Sector  
commands. Global Protect and Unprotect can also be performed.  
Locked in current state. Protect and Unprotect Sector commands  
will be ignored. Global Protect and Unprotect cannot be  
performed.  
Software Can be modified  
Locked from 1 to 0  
30  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
10. Security Commands  
10.1 Sector Lockdown  
Certain applications require that portions of the Flash memory array be permanently protected against malicious  
attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys,  
and routines. To address these applications, the device incorporates a sector lockdown mechanism that allows any  
combination of individual 64-Kbyte sectors to be permanently locked so that they become read only. Once a sector  
is locked down, it can never be erased or programmed again, and it can never be unlocked from the locked down  
state.  
Each 64-Kbyte physical sector has a corresponding single-bit Sector Lockdown Register that is used to control the  
lockdown status of that sector. These registers are nonvolatile and will retain their state even after a device power-  
cycle or reset operation. The following table outlines the two states of the Sector Lockdown Registers.  
Table 10-1. Sector Lockdown Register Values  
Value Sector Lockdown Status  
0
1
Sector is not locked down and can be programmed and erased. This is the default state.  
Sector is permanently locked down and can never be programmed or erased again.  
Issuing the Sector Lockdown command to a particular sector address will set the corresponding Sector Lockdown  
Register to the logical “1” state. Each Sector Lockdown Register can only be set once; therefore, once set to the  
logical “1” state, a Sector Lockdown Register cannot be reset back to the logical “0” state.  
Before the Sector Lockdown command can be issued, the Write Enable command must have been previously  
issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdown Enabled (SLE) bit  
in the Status Register must have also been previously set to the logical “1” state by using the Write Status Register  
Byte 2 command (see “Write Status Register Byte 2” on page 41). To issue the Sector Lockdown command, the  
CS pin must first be asserted and the opcode of 33h must be clocked into the device followed by three address  
bytes designating any address within the 64-Kbyte sector to be locked down. After the three address bytes have  
been clocked in, a confirmation byte of D0h must also be clocked in immediately following the three address bytes.  
Any additional data clocked into the device after the first byte of data will be ignored. When the CS pin is  
deasserted, the Sector Lockdown Register corresponding to the sector addressed by A23-A0 will be set to the  
logical “1” state, and the sector itself will then be permanently locked down from program and erase operations  
within a time of tLOCK. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state.  
The complete three address bytes and the correct confirmation byte value of D0h must be clocked into the device  
before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits);  
otherwise, the device will abort the operation. When the device aborts the Sector Lockdown operation, the state of  
the corresponding Sector Lockdown Register as well as the SLE bit in the Status Register will be unchanged;  
however, the WEL bit in the Status Register will be reset to a logical “0”.  
As a safeguard against accidental or erroneous locking down of sectors, the Sector Lockdown command can be  
enabled and disabled as needed by using the SLE bit in the Status Register. In addition, the current sector  
lockdown state can be frozen so that no further modifications to the Sector Lockdown Registers can be made (see  
“Freeze Sector Lockdown State” below). If the Sector Lockdown command is disabled or if the sector lockdown  
state is frozen, then any attempts to issue the Sector Lockdown command will be ignored, and the device will reset  
the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been  
deasserted.  
31  
8718A–DFLASH–04/10  
Figure 10-1. Sector Lockdown  
CS  
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10.2 Freeze Sector Lockdown State  
The current sector lockdown state can be permanently frozen so that no further modifications to the Sector  
Lockdown Registers can be made; therefore, the Sector Lockdown command will be permanently disabled, and no  
additional sectors can be locked down aside from those already locked down. Any attempts to issue the Sector  
Lockdown command after the sector lockdown state has been frozen will be ignored.  
Before the Freeze Sector Lockdown State command can be issued, the Write Enable command must have been  
previously issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdown  
Enabled (SLE) bit in the Status Register must have also been previously set to the logical “1” state. To issue the  
Freeze Sector Lockdown State command, the CS pin must first be asserted and the opcode of 34h must be  
clocked into the device followed by three command specific address bytes of 55AA40h. After the three address  
bytes have been clocked in, a confirmation byte of D0h must be clocked in immediately following the three address  
bytes. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the current  
sector lockdown state will be permanently frozen within a time of tLOCK. In addition, the WEL bit in the Status  
Register will be reset back to the logical “0” state, and the SLE bit will be permanently reset to a logical “0” to  
indicate that the Sector Lockdown command is permanently disabled.  
The complete and correct three address bytes and the confirmation byte must be clocked into the device before the  
CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise,  
the device will abort the operation. When the device aborts the Freeze Sector Lockdown State operation, the WEL  
bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged.  
Figure 10-2. Freeze Sector Lockdown State  
CS  
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32  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
10.3 Read Sector Lockdown Registers  
The Sector Lockdown Registers can be read to determine the current lockdown status of each physical 64-Kbyte  
sector. To read the Sector Lockdown Register for a particular 64-Kbyte sector, the CS pin must first be asserted  
and the opcode of 35h must be clocked in. Once the opcode has been clocked in, three address bytes designating  
any address within the 64-Kbyte sector must be clocked in. After the address bytes have been clocked in, data will  
be output on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of  
either FFh or 00h to denote the value of the appropriate Sector Lockdown Register.  
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock  
frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the  
correct status of the appropriate Sector Lockdown Register.  
Table 10-2. Read Sector Lockdown Register - Output Data  
Output Data  
00h  
Sector Lockdown Register Value  
Sector Lockdown Register value is 0 (sector is not locked down).  
Sector Lockdown Register value is 1 (sector is permanently locked down).  
FFh  
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS  
pin can be deasserted at any time and does not require that a full byte of data be read.  
Figure 10-3. Read Sector Lockdown Register  
CS  
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10.4 Program OTP Security Register  
The device contains a specialized OTP (One-Time Programmable) Security Register that can be used for  
purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key  
storage, etc. The OTP Security Register is independent of the main Flash memory array and is comprised of a total  
of 128 bytes of memory divided into two portions. The first 64 bytes (byte locations 0 through 63) of the OTP  
Security Register are allocated as a one-time user-programmable space. Once these 64 bytes have been  
programmed, they cannot be erased or reprogrammed. The remaining 64 bytes of the OTP Security Register (byte  
locations 64 through 127) are factory programmed by Atmel and will contain a unique value for each device. The  
factory programmed data is fixed and cannot be changed.  
33  
8718A–DFLASH–04/10  
Table 10-3. OTP Security Register  
Security Register  
Byte Number  
0
1
. . .  
62  
63  
64  
65  
. . .  
126  
127  
One-Time User Programmable  
Factory Programmed by Atmel  
The user-programmable portion of the OTP Security Register does not need to be erased before it is programmed.  
In addition, the Program OTP Security Register command operates on the entire 64-byte user-programmable  
portion of the OTP Security Register at one time. Once the user-programmable space has been programmed with  
any number of bytes, the user-programmable space cannot be programmed again; therefore, it is not possible to  
only program the first two bytes of the register and then program the remaining 62 bytes at a later time.  
Before the Program OTP Security Register command can be issued, the Write Enable command must have been  
previously issued to set the WEL bit in the Status Register to a logical “1”. To program the OTP Security Register,  
the CS pin must first be asserted and an opcode of 9Bh must be clocked into the device followed by the three  
address bytes denoting the first byte location of the OTP Security Register to begin programming at. Since the size  
of the user-programmable portion of the OTP Security Register is 64 bytes, the upper order address bits do not  
need to be decoded by the device. Therefore, address bits A23-A6 will be ignored by the device and their values  
can be either a logical “1” or “0”. After the address bytes have been clocked in, data can then be clocked into the  
device and will be stored in the internal buffer.  
If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP Security Register  
memory space (A5-A0 are not all 0), then special circumstances regarding which OTP Security Register locations  
to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the  
64-byte user-programmable space will wrap around back to the beginning of the OTP Security Register. For  
example, if the starting address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device,  
then the first two bytes of data will be programmed at OTP Security Register addresses 00003Eh and 00003Fh  
while the last byte of data will be programmed at address 000000h. The remaining bytes in the OTP Security  
Register (addresses 000001h through 00003Dh) will not be programmed and will remain in the erased state (FFh).  
In addition, if more than 64 bytes of data are sent to the device, then only the last 64 bytes sent will be latched into  
the internal buffer.  
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the  
appropriate OTP Security Register locations based on the starting address specified by A23-A0 and the number of  
data bytes sent to the device. If less than 64 bytes of data were sent to the device, then the remaining bytes within  
the OTP Security Register will not be programmed and will remain in the erased state (FFh). The programming of  
the data bytes is internally self-timed and should take place in a time of tOTPP. It is not possible to suspend the  
programming of the OTP Security Register.  
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin  
is deasserted, and the CS pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the  
device will abort the operation and the user-programmable portion of the OTP Security Register will not be  
programmed. The WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security  
Register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the  
CS pin being deasserted on non-byte boundaries, or because the user-programmable portion of the OTP Security  
Register was previously programmed.  
While the device is programming the OTP Security Register, the Status Register can be read and will indicate that  
the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting  
the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security  
Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state.  
34  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte  
user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again.  
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the  
contents of the buffer will be altered from its previous state when this command is issued.  
Figure 10-4. Program OTP Security Register  
CS  
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10.5 Read OTP Security Register  
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the  
maximum clock frequency specified by fMAX. To read the OTP Security Register, the CS pin must first be asserted  
and the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address  
bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security  
Register. Following the three address bytes, two dummy bytes must be clocked into the device before data can be  
output.  
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP  
Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has  
been read, the device will continue reading back at the beginning of the register (000000h). No delays will be  
incurred when wrapping around from the end of the register to the beginning of the register.  
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS  
pin can be deasserted at any time and does not require that a full byte of data be read.  
Figure 10-5. Read OTP Security Register  
CS  
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35  
8718A–DFLASH–04/10  
11. Status Register Commands  
11.1 Read Status Register  
The two-byte Status Register can be read to determine the device’s ready/busy status, as well as the status of  
many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any  
time, including during an internally self-timed program or erase operation.  
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the  
device. After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin  
during every subsequent clock cycle. After the second byte of the Status Register has been clocked out, the  
sequence will repeat itself starting again with the first byte of the Status Register as long as the CS pin remains  
asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each  
repeating sequence will output new data. The RDY/BSY status is available for both bytes of the Status Register  
and is updated for each byte.  
At clock frequencies above fCLK, the first two bytes of data output from the Status Register will not be valid.  
Therefore, if operating at clock frequencies above fCLK, at least four bytes of data must be clocked out from the  
device in order to read the correct values of both bytes of the Status Register.  
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-  
impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.  
Table 11-1. Status Register Format – Byte 1  
Bit(1)  
Name  
Type(2)  
R/W  
R
Description  
0
1
0
0
1
0
1
Sector Protection Registers are unlocked (default).  
Sector Protection Registers are locked.  
Reserved for future use.  
7
6
5
SPRL  
RES  
EPE  
Sector Protection Registers Locked  
Reserved for future use  
Erase/Program Error  
Erase or program operation was successful.  
Erase or program error detected.  
WP is asserted.  
R
4
WPP  
SWP  
WEL  
Write Protect (WP) Pin Status  
Software Protection Status  
Write Enable Latch Status  
R
R
WP is deasserted.  
All sectors are software unprotected (all Sector  
Protection Registers are 0).  
00  
01  
Some sectors are software protected. Read  
individual Sector Protection Registers to determine  
which sectors are protected.  
3:2  
10  
11  
Reserved for future use.  
All sectors are software protected (all Sector  
Protection Registers are 1 – default).  
0
1
0
1
Device is not write enabled (default).  
Device is write enabled.  
1
0
R
R
Device is ready.  
RDY/BSY Ready/Busy Status  
Device is busy with an internal operation.  
Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command.  
2. R/W = Readable and writeable  
R = Readable only  
36  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
Table 11-2. Status Register Format – Byte 2  
Bit(2)  
Name  
Type(2)  
Description  
Reserved for future use.  
7
6
5
RES  
RES  
RES  
Reserved for future use  
Reserved for future use  
Reserved for future use  
R
R
R
0
0
0
0
1
Reserved for future use.  
Reserved for future use.  
Reset command is disabled (default).  
Reset command is enabled.  
4
RSTE  
Reset Enabled  
R/W  
Sector Lockdown and Freeze Sector Lockdown State  
commands are disabled (default).  
0
1
3
SLE  
Sector Lockdown Enabled  
R/W  
Sector Lockdown and Freeze Sector Lockdown State  
commands are enabled.  
0
1
0
1
0
1
No sectors are program suspended (default).  
A sector is program suspended.  
No sectors are erase suspended (default).  
A sector is erase suspended.  
2
1
0
PS  
ES  
Program Suspend Status  
Erase Suspend Status  
R
R
R
Device is ready.  
RDY/BSY Ready/Busy Status  
Device is busy with an internal operation.  
Notes: 1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Register Byte 2 command.  
2. R/W = Readable and writeable  
R = Readable only  
11.1.1 SPRL Bit  
The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL  
bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect  
Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect  
and Global Unprotect features cannot be performed. Any sectors that are presently protected will remain protected,  
and any sectors that are presently unprotected will remain unprotected.  
When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and can be modified (the  
Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features, will  
be processed as normal). The SPRL bit defaults to the logical “0” state after device power-up. The Reset command  
has no effect on the SPRL bit.  
The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then  
the SPRL bit may only be changed from a logical “0” (Sector Protection Registers are unlocked) to a logical “1”  
(Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical “0” using the Write Status  
Register Byte 1 command, the WP pin will have to first be deasserted.  
The SPRL bit is the only bit of Status Register Byte 1 that can be user modified via the Write Status Register Byte  
1 command.  
37  
8718A–DFLASH–04/10  
11.1.2 EPE Bit  
The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one  
byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the  
logical “1” state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an  
attempt to erase or program a protected region or a locked down sector, an attempt to erase or program a  
suspended sector, or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated  
after every erase and program operation.  
11.1.3 WPP Bit  
The WPP bit can be read to determine if the WP pin has been asserted or not.  
11.1.4 SWP Bits  
The SWP bits provide feedback on the software protection status for the device. There are three possible  
combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using the  
Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been  
protected, then the individual Sector Protection Registers can be read with the Read Sector Protection Registers  
command to determine which sectors are in fact protected.  
11.1.5 WEL Bit  
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0”  
state, the device will not accept any Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector  
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status Register, or Write  
Configuration Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset  
operation. In addition, the WEL bit will be reset to the logical “0” state automatically under the following conditions:  
• Write Disable operation completes successfully  
• Write Status Register operation completes successfully or aborts  
• Write Configuration Register operation completes successfully or aborts  
• Protect Sector operation completes successfully or aborts  
• Unprotect Sector operation completes successfully or aborts  
• Sector Lockdown operation completes successfully or aborts  
• Freeze Sector Lockdown State operation completes successfully or aborts  
• Program OTP Security Register operation completes successfully or aborts  
• Byte/Page Program operation completes successfully or aborts  
• Block Erase operation completes successfully or aborts  
• Chip Erase operation completes successfully or aborts  
• Hold condition aborts  
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete  
or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to  
be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Protect Sector,  
Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status  
Register, or Write Configuration Register command must have been clocked into the device.  
38  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
11.1.6 RSTE Bit  
The RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the logical “0” state (the  
default state after power-up), the Reset command is disabled and any attempts to reset the device using the Reset  
command will be ignored. When the RSTE bit is in the logical “1” state, the Reset command is enabled.  
The RSTE bit will retain its state as long as power is applied to the device. Once set to the logical “1” state, the  
RSTE bit will remain in that state until it is modified using the Write Status Register Byte 2 command or until the  
device has been power cycled. The Reset command itself will not change the state of the RSTE bit.  
11.1.7 SLE Bit  
The SLE bit is used to enable and disable the Sector Lockdown and Freeze Sector Lockdown State commands.  
When the SLE bit is in the logical “0” state (the default state after power-up), the Sector Lockdown and Freeze  
Sector Lockdown commands are disabled. If the Sector Lockdown and Freeze Sector Lockdown commands are  
disabled, then any attempts to issue the commands will be ignored. This provides a safeguard for these commands  
against accidental or erroneous execution. When the SLE bit is in the logical “1” state, the Sector Lockdown and  
Freeze Sector Lockdown State commands are enabled.  
Unlike the WEL bit, the SLE bit does not automatically reset after certain device operations. Therefore, once set,  
the SLE bit will remain in the logical “1” state until it is modified using the Write Status Register Byte 2 command or  
until the device has been power cycled. The Reset command has no effect on the SLE bit.  
If the Freeze Sector Lockdown State command has been issued, then the SLE bit will be permanently reset in the  
logical “0” state to indicate that the Sector Lockdown command has been disabled.  
11.1.8 PS Bit  
The PS bit indicates whether or not a sector is in the Program Suspend state.  
11.1.9 ES Bit  
The ES bit indicates whether or not a sector is in the Erase Suspend state.  
11.1.10 RDY/BSY Bit  
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in  
progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data  
must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a  
logical “0”.  
Figure 11-1. Read Status Register  
CS  
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39  
8718A–DFLASH–04/10  
11.2 Write Status Register Byte 1  
The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to perform  
a Global Protect or Global Unprotect operation. Before the Write Status Register Byte 1 command can be issued,  
the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical  
“1”.  
To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and the opcode of 01h must  
be clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a  
don’t care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two  
additional don’t care bits (see Table 11-3). Any additional data bytes that are sent to the device will be ignored.  
When the CS pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status  
Register will be reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before the  
Write Status Register Byte 1 command was executed (the prior state of the SPRL bit) will determine whether or not  
a Global Protect or Global Unprotect will be performed. Please refer to “Global Protect/Unprotect” on page 27 for  
more details.  
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin  
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,  
the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL  
bit in the Status Register will be reset back to the logical “0” state.  
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the SPRL  
bit to a logical “0” while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored, and  
the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a  
logical “0”, the WP pin must be deasserted.  
Table 11-3. Write Status Register Byte 1 Format  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SPRL  
X
Global Protect/Unprotect  
X
X
Figure 11-2. Write Status Register Byte 1  
CS  
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40  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
11.3 Write Status Register Byte 2  
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using  
the Write Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register  
during normal device operation, and the SLE bit can only be modified if the sector lockdown state has not been  
frozen. Before the Write Status Register Byte 2 command can be issued, the Write Enable command must have  
been previously issued to set the WEL bit in the Status Register to a logical “1”.  
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the opcode of 31h must  
be clocked into the device followed by one byte of data. The one byte of data consists of three don’t care bits, the  
RSTE bit value, the SLE bit value, and three additional don’t care bits (see Table 11-4). Any additional data bytes  
that are sent to the device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status  
Register will be modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The SLE bit will  
only be modified if the Freeze Sector Lockdown State command has not been previously issued.  
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin  
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,  
the state of the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the  
logical “0” state.  
Table 11-4. Write Status Register Byte 2 Format  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
X
X
X
RSTE  
SLE  
X
X
X
Figure 11-3. Write Status Register Byte 2  
CS  
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41  
8718A–DFLASH–04/10  
11.4 Read Configuration Register  
The non-volatile Configuration Register can be read to determine if the Quad-Input Byte/Page Program and Quad-  
Output Read Array commands have been enabled. Unlike the Status Register, the Configuration Register can only  
be read when the device is in an idle state (when the RDY/BSY bit of the Status Register indicates that the device  
is in a ready state).  
To read the Configuration Register, the CS pin must first be asserted and the opcode of 3Fh must be clocked into  
the device. After the opcode has been clocked in, the device will begin outputting the one byte of Configuration  
Register data on the SO pin during subsequent clock cycles. The data being output will be a repeating byte as  
long as the CS pin remains asserted and the clock pin is being pulsed.  
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock  
frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the  
correct value of the Configuration Register.  
Deasserting the CS pin will terminate the Read Configuration Register operation and put the SO pin into a high-  
impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.  
The Configuration Register is a non-volatile register; therefore, the contents of the Configuration Register are not  
affected by power cycles or power-on reset operations.  
Table 11-5. Configuration Register Format  
Bit(1)  
Name  
Type(2)  
R/W  
R
Description  
Quad-Input/Output commands and operation  
disabled.  
0
7
QE  
Quad Enable  
Quad-Input/Output commands and operation  
enabled (WP and HOLD disabled).  
1
0
6:0  
RES  
Reserved for future use  
Reserved for future use.  
Notes: 1. Only bit 7 of the Configuration Register will be modified when using the Write Configuration Register command.  
2. R/W = Readable and writeable  
R = Readable only  
11.4.1 QE Bit  
The QE bit is used to control whether the Quad-Input Byte/Page Program and Quad-Output Read Array  
commands are enabled or disabled. When the QE bit is in the logical “1” state, the Quad-Input Byte/Page Program  
and Quad-Output Read Array commands are enabled and will be recognized by the device. In addition, the WP  
and HOLD functions are disabled, and the WP and HOLD pins themselves operate as a bidirectional input/output  
pins (WP is I/O2 and HOLD is I/O3).  
When the QE bit is in the logical “0” state, the Quad-Input Byte/Page Program and Quad-Output Read Array  
commands are disabled and will not be recognized by the device as valid commands, and the WP and HOLD pins  
function as normal control pins. The WP and HOLD pins should be externally pulled-high to avoid erroneous or  
unwanted device operation.  
The Reset command has no effect on the QE bit. The QE bit defaults to the logical “0” state when devices are  
initially shipped from Atmel.  
42  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
Figure 11-4. Read Configuration Register  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24  
SCK  
SI  
OPCODE  
0
MSB  
0
1
1
1
1
1
1
CONFIGURATION  
REGISTER OUT  
CONFIGURATION  
REGISTER OUT  
HIGH-IMPEDANCE  
D
X
X
X
X
X
X
X
D
X
X
X
X
X
X
X
D
X
SO  
MSB  
MSB  
MSB  
11.5 Write Configuration Register  
The Write Configuration Register command is used to modify the QE bit of the non-volatile Configuration Register.  
Before the Write Configuration Register command can be issued, the Write Enable command must have been  
previously issued to set the WEL bit in the Status Register to a logical “1”.  
To issue the Write Configuration Register command, the CS pin must first be asserted and the opcode of 3Eh must  
be clocked into the device followed by one byte of data. The one byte of data consists of the QE bit value and  
seven don’t care bits (Table 11-6). Any additional data clocked into the device will be ignored. When the CS pin is  
deasserted, the QE bit of the Configuration Register will be modified within a time of tWRCR, and the WEL bit in the  
Status Register will be reset back to a logical “0”.  
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin  
must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the  
value of the Configuration Register will not change, and the WEL bit in the Status Register will be reset back to the  
logical “0” state.  
The Configuration Register is a non-volatile register and is subject to the same program/erase endurance  
characteristics of the main memory array.  
The programming of the Configuration Register is internally self-timed and should take place in a time of tWRCR.  
While the Configuration Register is being updated, the Status Register can be read and will indicate that the device  
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tWRCR  
time to determine if the Configuration Register has completed the programming cycle. At some point before the  
programming cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state.  
Table 11-6. Write Configuration Register Format  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
QE  
X
X
X
X
X
X
X
43  
8718A–DFLASH–04/10  
Figure 11-5. Write Configuration Register  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
SCK  
SI  
CONFIGURATION  
REGISTER IN  
OPCODE  
0
0
1
1
1
1
1
0
D
X
X
X
X
X
X
X
MSB  
MSB  
HIGH-IMPEDANCE  
SO  
12. Other Commands and Functions  
12.1 Reset  
In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait  
the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally.  
The Reset command allows a program or erase operation in progress to be ended abruptly and returns the device  
to an idle state. Since the need to reset the device is immediate, the Write Enable command does not need to be  
issued prior to the Reset command being issued. Therefore, the Reset command operates independently of the  
state of the WEL bit in the Status Register.  
The Reset command can only be executed if the command has been enabled by setting the Reset Enabled  
(RSTE) bit in the Status Register to a logical “1”. If the Reset command has not been enabled (the RSTE bit is in  
the logical “0” state), then any attempts at executing the Reset command will be ignored.  
To perform a Reset, the CS pin must first be asserted and the opcode of F0h must be clocked into the device. No  
address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the device immediately  
after the opcode. Any additional data clocked into the device after the confirmation byte will be ignored. When the  
CS pin is deasserted, the program or erase operation currently in progress will be terminated within a time of tRST  
.
Since the program or erase operation may not complete before the device is reset, the contents of the page being  
programmed or the block being erased cannot be guaranteed to be valid.  
The Reset command has no effect on the states of the Sector Protection Registers, the Sector Lockdown  
Registers, the Configuration Register, or the SPRL, RSTE, and SLE bits in the Status Register. The WEL, PS, and  
ES bits of the Status Register, however, will be reset back to their default states. If a Reset operation is performed  
while a sector is erase suspended, the suspend operation will abort, and the contents of the block being erased in  
the suspended sector will be left in an undefined state. If a Reset is performed while a sector is program  
suspended, the suspend operation will abort, and the contents of the page that was being programmed and  
subsequently suspended will be undefined. The remaining pages in the 64-Kbyte sector will retain their previous  
contents.  
The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and  
the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no Reset operation will be  
performed.  
44  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
Figure 12-1. Reset  
CS  
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12.2 Read Manufacturer and Device ID  
Identification information can be read from the device to enable systems to electronically query and identify the  
device while it is in system. The identification method and the command opcode comply with the JEDEC standard  
for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The  
type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor  
specific Device ID, and the vendor specific Extended Device Information.  
The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all  
Flash devices are capable of operating at very high clock frequencies, applications should be designed to read the  
identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used  
in the application can be identified properly. Once the identification process is complete, the application can then  
increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher  
clock frequencies.  
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into  
the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO  
pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two  
bytes of Device ID information. The fourth byte output will be the Extended Device Information (EDI) String Length,  
which will be 01h indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin  
will go into a high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data  
will be output. As indicated in the JEDEC standard, reading the EDI String Length and any subsequent data is  
optional.  
Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a  
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be  
read.  
45  
8718A–DFLASH–04/10  
Table 12-1. Manufacturer and Device ID Information  
Byte No.  
Data Type  
Value  
1Fh  
88h  
1
2
3
4
5
Manufacturer ID  
Device ID (Part 1)  
Device ID (Part 2)  
00h  
[Optional to read] Extended Device Information (EDI) String Length  
[Optional to read] EDI Byte 1  
01h  
00h  
Table 12-2. Manufacturer and Device ID Details  
Hex  
Data Type  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details  
JEDEC Assigned Code  
Manufacturer ID  
1Fh  
87h  
00h  
JEDEC Code: 0001 1111 (1Fh for Atmel)  
0
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
Family Code:  
Density Code: 00111 (32-Mbit)  
100 (Quad-I/O or Rapid4™)  
Family Code  
Density Code  
1
Device ID (Part 1)  
Device ID (Part 2)  
0
Sub Code  
0
0
1
Product Variant  
Sub Code:  
000 (Quad-I/O series)  
Product Variant: 00000 (Standard version)  
0
0
0
Table 12-3.  
Hex  
Byte Number  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details  
RFU  
0
Device Revision  
RFU:  
Reserved for Future Use  
1
00h  
Density Code: 00000 (Initial version)  
0
0
0
0
0
0
0
Figure 12-2. Read Manufacturer and Device ID  
CS  
0
6
7
8
14 15 16  
22 23 24  
30 31 32  
38 39 40  
46  
SCK  
SI  
OPCODE  
9Fh  
HIGH-IMPEDANCE  
1Fh  
86h  
00h  
01h  
00h  
EDI  
SO  
MANUFACTURER ID  
DEVICE ID  
BYTE 1  
DEVICE ID  
BYTE 2  
EDI  
STRING LENGTH  
DATA BYTE 1  
Note: Each transition  
shown for SI and SO represents one byte (8 bits)  
46  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
12.3 Deep Power-Down  
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS  
pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability  
to place the device into an even lower power consumption state called the Deep Power-Down mode.  
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command  
will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be  
ignored, the mode can be used as an extra protection mechanism against program and erase operations.  
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of  
B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored.  
When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of  
tEDPD  
.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on  
a byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby  
mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle.  
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase  
cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation  
has been completed in order for the device to enter the Deep Power-Down mode.  
Figure 12-3. Deep Power-Down  
CS  
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47  
8718A–DFLASH–04/10  
12.4 Resume from Deep Power-Down  
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-  
Down command must be issued. The Resume from Deep Power-Down command is the only command that the  
device will recognized while in the Deep Power-Down mode.  
To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of ABh must be  
clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS  
pin is deasserted, the device will exit the Deep Power-Down mode within the maximum time of tRDPD and return to  
the standby mode. After the device has returned to the standby mode, normal command operations such as Read  
Array can be resumed.  
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on a  
byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down  
mode.  
Figure 12-4. Resume from Deep Power-Down  
CS  
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48  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
12.5 Hold  
The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock  
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a  
program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the  
operation, and the erase cycle will continue until it is finished.  
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting  
the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold  
mode won’t be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as  
long as the HOLD pin and CS pin are asserted.  
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin  
will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.  
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low  
pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning  
of the next SCK low pulse.  
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will  
be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.  
Figure 12-5. Hold Mode  
CS  
SCK  
HOLD  
+ROG  
+ROG  
+ROG  
49  
8718A–DFLASH–04/10  
13. Electrical Specifications  
13.1 Absolute Maximum Ratings*  
Temperature under Bias................. -55C to +125C  
Storage Temperature...................... -65C to +150C  
*NOTICE: Stresses beyond those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device.  
Functional operation of the device at these ratings or any  
other conditions beyond those indicated in the operational  
sections of this specification is not implied. Exposure to  
absolute maximum rating conditions for extended periods  
may affect device reliability. Voltage extremes referenced in  
the "Absolute Maximum Ratings" are intended to accommo-  
date short duration undershoot/overshoot conditions and  
does not imply or guarantee functional device operation at  
these levels for any extended period of time.  
All Input Voltages  
(including NC Pins)  
with Respect to Ground ......................-0.6V to +4.1V  
All Output Voltages  
with Respect to Ground ..............-0.6V to VCC + 0.5V  
13.2 DC and AC Operating Range  
AT25DQ321A  
-40C to 85C  
2.7V to 3.6V  
Operating Temperature (Case)  
VCC Power Supply  
Ind.  
13.3 DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Units  
CS, WP, HOLD = VCC  
,
ISB  
Standby Current  
25  
50  
µA  
all inputs at CMOS levels  
CS, WP, HOLD = VCC  
,
IDPD  
Deep Power-down Current  
5
12  
10  
8
10  
19  
17  
14  
12  
10  
8
µA  
all inputs at CMOS levels  
f = 100 MHz; IOUT = 0 mA;  
CS = VIL, VCC = Max  
f = 85 MHz; IOUT = 0 mA;  
CS = VIL, VCC = Max  
f = 66 MHz; IOUT = 0 mA;  
CS = VIL, VCC = Max  
ICC1  
Active Current, Read Operation  
mA  
f = 50 MHz; IOUT = 0 mA;  
CS = VIL, VCC = Max  
7
f = 33 MHz; IOUT = 0 mA;  
CS = VIL, VCC = Max  
6
f = 20 MHz; IOUT = 0 mA;  
CS = VIL, VCC = Max  
5
ICC2  
ICC3  
ILI  
Active Current, Program Operation  
Active Current, Erase Operation  
Input Leakage Current  
CS = VCC, VCC = Max  
CS = VCC, VCC = Max  
VIN = CMOS levels  
10  
12  
20  
20  
1
mA  
mA  
µA  
50  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
13.3 DC Characteristics (Continued)  
Symbol  
ILO  
Parameter  
Condition  
Min  
Typ  
Max  
1
Units  
µA  
V
Output Leakage Current  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
VOUT = CMOS levels  
VIL  
0.3 x VCC  
VIH  
0.7 x VCC  
V
VOL  
IOL = 1.6 mA; VCC = Min  
IOH = -100 µA; VCC = Min  
0.4  
V
VOH  
VCC - 0.2V  
V
13.4 AC Characteristics – Maximum Clock Frequencies  
Symbol  
RapidS and SPI Operation  
Maximum Clock Frequency for All Operations – RapidS Operation Only  
Parameter  
Min  
Max  
Units  
fMAX  
100  
85  
MHz  
MHz  
(excluding 03h, 0Bh, 3Bh, 6Bh, and 9F opcodes)  
Maximum Clock Frequency for All Operations  
(excluding 03h opcode)  
fCLK  
fRDLF  
fRDDO  
fRDQO  
Maximum Clock Frequency for 03h Opcode (Read Array – Low Frequency)  
Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read)  
Maximum Clock Frequency for 6Bh Opcode (Quad-Output Read)  
33  
70  
70  
MHz  
MHz  
MHz  
51  
8718A–DFLASH–04/10  
13.5 AC Characteristics – All Other Parameters  
Symbol  
tCLKH  
Parameter  
Min  
4.3  
4.3  
0.1  
0.1  
35  
5
Max  
Units  
ns  
Clock High Time  
tCLKL  
Clock Low Time  
ns  
(1)  
tCLKR  
Clock Rise Time, Peak-to-Peak (Slew Rate)  
Clock Fall Time, Peak-to-Peak (Slew Rate)  
Chip Select High Time  
V/ns  
V/ns  
ns  
(1)  
tCLKF  
tCSH  
tCSLS  
tCSLH  
tCSHS  
tCSHH  
tDS  
Chip Select Low Setup Time (relative to Clock)  
Chip Select Low Hold Time (relative to Clock)  
Chip Select High Setup Time (relative to Clock)  
Chip Select High Hold Time (relative to Clock)  
Data In Setup Time  
ns  
5
ns  
5
ns  
5
ns  
2
ns  
tDH  
Data In Hold Time  
1
ns  
(1)  
tDIS  
Output Disable Time  
5
5
ns  
(2)  
tV  
Output Valid Time  
ns  
tOH  
Output Hold Time  
2
5
5
5
5
ns  
tHLS  
tHLH  
tHHS  
tHHH  
HOLD Low Setup Time (relative to Clock)  
HOLD Low Hold Time (relative to Clock)  
HOLD High Setup Time (relative to Clock)  
HOLD High Hold Time (relative to Clock)  
HOLD Low to Output High-Z  
ns  
ns  
ns  
ns  
(1)  
tHLQZ  
5
5
ns  
(1)  
tHHQX  
HOLD High to Output Low-Z  
ns  
(1)(3)  
tWPS  
Write Protect Setup Time  
20  
ns  
(1)(3)  
tWPH  
Write Protect Hold Time  
100  
ns  
(1)  
tSECP  
Sector Protect Time (from Chip Select High)  
Sector Unprotect Time (from Chip Select High)  
Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High)  
Chip Select High to Deep Power-Down  
Chip Select High to Standby Mode  
Reset Time  
20  
20  
200  
1
ns  
(1)  
tSECUP  
ns  
(1)  
tLOCK  
µs  
(1)  
tEDPD  
µs  
(1)  
tRDPD  
8
µs  
tRST  
30  
µs  
Note:  
1. Not 100% tested (value guaranteed by design and characterization).  
2. 15 pF load at frequencies above 70 MHz, 30 pF otherwise.  
3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1.  
52  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
13.6 Program and Erase Characteristics  
Symbol  
Parameter  
Min  
Typ  
1.5  
20  
Max  
Units  
ms  
(1)  
tPP  
Page Program Time (256 Bytes)  
Byte Program Time  
5.0  
tBP  
µs  
4 Kbytes  
32 Kbytes  
64 Kbytes  
50  
200  
600  
950  
56  
(1)  
tBLKE  
Block Erase Time  
250  
400  
36  
ms  
(1)(2)  
tCHPE  
Chip Erase Time  
Suspend Time  
sec  
µs  
Program  
Erase  
10  
20  
tSUSP  
25  
40  
Program  
Erase  
10  
20  
tRES  
Resume Time  
µs  
12  
20  
(1)  
tOTPP  
OTP Security Register Program Time  
Write Status Register Time  
200  
500  
200  
35  
µs  
ns  
(2)  
tWRSR  
tWRCR  
Write Configuration Register Time  
15  
ms  
Notes: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles.  
2. Not 100% tested (value guaranteed by design and characterization).  
13.7 Power-up Conditions  
Symbol  
tVCSL  
Parameter  
Min  
Max  
Units  
µs  
Minimum VCC to Chip Select Low Time  
Power-up Device Delay Before Program or Erase Allowed  
Power-on Reset Voltage  
100  
tPUW  
10  
ms  
V
VPOR  
1.8  
2.2  
13.8 Input Test Waveforms and Measurement Levels  
0.9VCC  
AC  
AC  
DRIVING  
LEVELS  
MEASUREMENT  
LEVEL  
VCC/2  
0.1VCC  
tR, tF < 2 ns (10% to 90%)  
13.9 Output Test Load  
DEVICE  
UNDER  
TEST  
15 pF (frequencies above 70 MHz)  
or  
30pF  
53  
8718A–DFLASH–04/10  
14. AC Waveforms  
Figure 14-1. Serial Input Timing  
W&6+  
CS  
W&6/6  
W&6/+  
W&/./  
W&6++  
W&/.+  
W&6+6  
SCK  
W'6  
W'+  
06%  
/6%  
06%  
SI  
+,*+ꢋ,03('$1&(  
SO  
Figure 14-2. Serial Output Timing  
CS  
W&/.+  
W&/./  
W',6  
SCK  
SI  
W2+  
W9  
W9  
SO  
Figure 14-3. WP Timing for Write Status Register Byte 1 Command When SPRL = 1  
CS  
W:36  
W:3+  
WP  
SCK  
SI  
ꢃ
ꢃ
ꢃ
;
06%  
06%ꢊ2)  
/6%ꢊ2)  
:5,7(ꢊ67$786ꢊ5(*,67(5  
'$7$ꢊ%<7(  
06%ꢊ2)  
:5,7(ꢊ67$786ꢊ5(*,67(5  
%<7(ꢊꢂꢊ23&2'(  
1(;7ꢊ23&2'(  
+,*+ꢋ,03('$1&(  
SO  
54  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
Figure 14-4. HOLD Timing – Serial Input  
CS  
SCK  
W+++  
W+/6  
W+/+  
W++6  
HOLD  
SI  
+,*+ꢋ,03('$1&(  
SO  
Figure 14-5. HOLD Timing – Serial Output  
CS  
SCK  
W+++  
W+/6  
W+/+  
W++6  
HOLD  
SI  
W+/4=  
W++4;  
SO  
55  
8718A–DFLASH–04/10  
15. Ordering Information  
15.1 Ordering Code Detail  
A T 2 5 D Q 3 2 1 A - 5 3 H - B  
Atmel Designator  
Product Family  
Shipping Carrier Option  
B = Bulk (tubes)  
Y = Bulk (trays)  
T = Tape and reel  
Device Grade  
H = Green, NiPdAu lead finish  
Industrial Temperature range  
(-40°C to +85°C)  
Device Density  
16 = 16-megabit  
Package Option  
53 = 16-lead 0.300” wide SOIC  
Interface  
1 = Serial  
S
= 8-lead, 0.208” wide SOIC  
MA= 8-pad, 5 x 6 x 0.300” wide SOIC  
15.2 Green Package Options (Pb/Halide-free/RoHS Compliant)  
Max.Freq.  
Ordering Code  
Package  
Lead (Pad) Finish Operating Voltage  
(MHz)  
Operation Range  
AT25DQ321A-MH-B  
AT25DQ321A-MH-T  
8MA1  
AT25DQ321A-SH-B  
AT25DQ321A-SH-T  
Industrial  
8S1  
16S  
NiPdAu  
2.7V to 3.6V  
100  
(-40°C to +85°C)  
AT25DQ321A-53H-B  
AT25DQ321A-53H-T  
Note:  
The shipping carrier option code is not marked on the devices.  
Package Type  
8MA1  
8-pad (5 x 6 x 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN)  
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)  
16-lead, 0.300” Wide, Plastic Gull Wing Small Outline Package (SOIC)  
8S1  
16S  
56  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
16. Packaging Information  
16.1 8MA1 – UDFN  
E
C
Pin 1 ID  
Side View  
D
y
Top View  
A1  
A
K
E2  
Option A  
Pin #1  
8
1
2
3
Pin #1 Notch  
(0.20 R)  
Chamfer  
(C 0.35)  
COMMON DIMENSIONS  
(Unit of Measure = mm)  
(Option B)  
7
SYMBOL  
MIN  
0.45  
0.00  
0.35  
NOM  
0.55  
0.02  
0.40  
0.152 REF  
5.00  
4.00  
6.00  
3.40  
1.27  
0.60  
–
MAX  
0.60  
0.05  
0.48  
NOTE  
e
D2  
A
6
A1  
b
5
4
C
D
D2  
E
5.10  
4.20  
6.10  
3.60  
4.90  
3.80  
5.90  
3.20  
b
Bottom View  
L
E2  
e
0.75  
0.08  
–
L
0.50  
0.00  
0.20  
Notes: 1. This package conforms to JEDEC reference MO-229,  
Saw Singulation.  
y
2. The terminal #1 ID is a Laser-marked Feature.  
K
–
4/15/08  
TITLE  
GPC  
YFG  
DRAWING NO.  
REV.  
Package Drawing Contact:  
8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally  
packagedrawings@atmel.com Enhanced Plastic Ultra Thin Dual Flat No Lead  
8MA1  
D
Package (UDFN)  
57  
8718A–DFLASH–04/10  
16.2 8S1 – JEDEC SOIC  
C
GND  
4
NC  
3
NC  
2
NC  
1
E
E1  
L
5
6
7
8
SDA  
SCL  
NC  
VCC  
Ø
Top View  
End View  
e
b
COMMON DIMENSIONS  
(Unit of Measure = mm)  
A
SYMBOL  
MIN  
1.35  
0.10  
0.31  
0.17  
4.80  
3.81  
5.79  
NOM  
MAX  
1.75  
0.25  
0.51  
0.25  
5.05  
3.99  
6.20  
NOTE  
A1  
A
–
A1  
b
–
–
C
D
E1  
E
–
–
D
–
–
Side View  
e
1.27 BSC  
Notes: 1. These drawings are for general information only. Refer  
to JEDEC Drawing MS-012, Variation AA for proper  
dimensions, tolerances, datums, etc.  
1.27  
8˚  
L
0.40  
0˚  
–
–
θ
12/11/09  
TITLE  
GPC  
SWB  
DRAWING NO.  
REV.  
8S1, 8-lead, (0.150” Wide Body),  
packagedrawings@atmel.com Plastic Gull Wing Outline (JEDEC SOIC)  
Package Drawing Contact:  
8S1  
E
58  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
AT25DQ321A [Preliminary]  
16.3 16S – SOIC  
1
End View  
E
H
E
N
L
Top View  
C
e
b
A1  
A
D
COMMON DIMENSIONS  
(Unit of Measure = mm)  
Side View  
SYMBOL  
MIN  
2.35  
0.10  
0.31  
NOM  
MAX  
2.65  
0.30  
0.51  
NOTE  
A
A1  
b
–
Notes: 1. This drawing is for general information only; refer to  
JEDEC Drawing MS-013, Variation AA for additional  
information.  
–
–
2. Dimension D does not include mold Flash, protrusions  
or gate burrs. Mold Flash, protrusion and gate burrs  
shall not exceed 0.15 mm (0.006") per side.  
3. Dimension E does not include inter-lead Flash or  
protrusion. Inter-lead flash and protrusions shall not  
exceed 0.25 mm (0.010") per side.  
2
3
D
E
H
L
10.30 BSC  
7.50 BSC  
10.30 BSC  
–
1.27  
0.33  
4
0.40  
0.20  
e
1.27 BSC  
4. L is the length of the terminal for soldering to a  
substrate.  
C
11/02/05  
TITLE  
DRAWING NO.  
REV.  
Package Drawing Contact:  
packagedrawings@atmel.com  
16S, 16-lead, 0.300" Wide Body, Plastic Gull  
Wing Small Outline Package (SOIC)  
16S  
A
59  
8718A–DFLASH–04/10  
17. Revision History  
Doc. Rev.  
Date  
Comments  
8718A  
4/2010  
Initial document release  
60  
AT25DQ321A [Preliminary]  
8718A–DFLASH–04/10  
Headquarters  
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Sales Contact  
www.atmel.com  
dataflash@atmel.com  
www.atmel.com/contacts  
Literature Requests  
www.atmel.com/literature  
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8718A–DFLASH–04/10