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S19FL064P MirrorBit® ROM  
64-Mbit CMOS 3.0 Volt MirrorBit ROM  
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus  
Data Sheet (Preliminary)  
S19FL064P MirrorBit® ROM Cover Sheet  
Notice to Readers: This document states the current technical specifications regarding the Spansion  
product(s) described herein. Each product described herein may be designated as Advance Information,  
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.  
Publication Number S19FL064P_00  
Revision 01  
Issue Date July 29, 2009  
D a t a S h e e t ( P r e l i m i n a r y )  
Notice On Data Sheet Designations  
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of  
product information or intended specifications throughout the product life cycle, including development,  
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify  
that they have the latest information before finalizing their design. The following descriptions of Spansion data  
sheet designations are presented here to highlight their presence and definitions.  
Advance Information  
The Advance Information designation indicates that Spansion Inc. is developing one or more specific  
products, but has not committed any design to production. Information presented in a document with this  
designation is likely to change, and in some cases, development on the product may discontinue. Spansion  
Inc. therefore places the following conditions upon Advance Information content:  
“This document contains information on one or more products under development at Spansion Inc.  
The information is intended to help you evaluate this product. Do not design in this product without  
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed  
product without notice.”  
Preliminary  
The Preliminary designation indicates that the product development has progressed such that a commitment  
to production has taken place. This designation covers several aspects of the product life cycle, including  
product qualification, initial production, and the subsequent phases in the manufacturing process that occur  
before full production is achieved. Changes to the technical specifications presented in a Preliminary  
document should be expected while keeping these aspects of production under consideration. Spansion  
places the following conditions upon Preliminary content:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. The Preliminary status of this document indicates that product qualification has been  
completed, and that initial production has begun. Due to the phases of the manufacturing process that  
require maintaining efficiency and quality, this document may be revised by subsequent versions or  
modifications due to changes in technical specifications.”  
Combination  
Some data sheets contain a combination of products with different designations (Advance Information,  
Preliminary, or Full Production). This type of document distinguishes these products and their designations  
wherever necessary, typically on the first page, the ordering information page, and pages with the DC  
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first  
page refers the reader to the notice on this page.  
Full Production (No Designation on Document)  
When a product has been in production for a period of time such that no changes or only nominal changes  
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include  
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed  
option, temperature range, package type, or V range. Changes may also include those needed to clarify a  
IO  
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following  
conditions to documents in this category:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. Spansion Inc. deems the products to have been in sufficient production volume such  
that subsequent versions of this document are not expected to change. However, typographical or  
specification corrections, or modifications to the valid combinations offered may occur.”  
Questions regarding these document designations may be directed to your local sales office.  
2
S19FL064P MirrorBit® ROM  
S19FL064P_00_01 July 29, 2009  
S19FL064P MirrorBit® ROM  
64-Mbit CMOS 3.0 Volt MirrorBit ROM  
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus  
Data Sheet (Preliminary)  
Distinctive Characteristics  
Architectural Advantages  
Performance Characteristics  
„ Single power supply operation  
„ Speed  
– Normal READ (Serial): 40 MHz clock rate  
– Full voltage range: 2.7 to 3.6V  
– FAST_READ (Serial): 104 MHz clock rate (maximum)  
– DUAL I/O FAST_READ: 80 MHz clock rate or  
20 MB/s effective data rate  
– QUAD I/O FAST_READ: 80 MHz clock rate or  
40 MB/s effective data rate  
„ Device ID  
– JEDEC standard two-byte electronic signature  
– RES command one-byte electronic signature for backward  
compatibility  
„ Process technology  
– Manufactured on 0.09 µm MirrorBit® process technology  
„ Power saving standby mode  
– Standby Mode 80 µA (typical)  
„ Package option  
– Deep Power-Down Mode 3 µA (typical)  
– Industry Standard Pinouts  
– 16-pin SO package (300 mils)  
„ Data retention  
– 20 years typical  
General Description  
The S19FL064P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Serial Peripheral Interface (SPI) read-only memory device.  
The S19FL064P device is fully backward compatible with the S19FL064A device.  
The S19FL064P device adds the following high-performance features using 4 new instructions:  
„ Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz  
„ Quad Output Read using SI, SO, IO2 and HOLD# pins as output pins at a clock rate of up to 80 MHz  
„ Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz  
„ Quad I/O High Performance Read using SI, SO, IO2 and HOLD# pins as input and output pins at a clock rate of up to 80 MHz  
Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for read functions.  
Publication Number S19FL064P_00  
Revision 01  
Issue Date July 29, 2009  
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-  
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document  
may be revised by subsequent versions or modifications due to changes in technical specifications.  
D a t a S h e e t ( P r e l i m i n a r y )  
Table of Contents  
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.  
2.  
3.  
4.  
5.  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
5.1  
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
6.  
7.  
Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
7.1  
7.2  
7.3  
7.4  
Dual and Quad I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
8.  
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
8.1  
8.2  
8.3  
8.4  
8.5  
8.6  
8.7  
8.8  
8.9  
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Dual Output Read Mode (DOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Quad Output Read Mode (QOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
DUAL I/O High Performance Read Mode (DIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Quad I/O High Performance Read Mode (QIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Read Identification (RDID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Read-ID (READ_ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Deep Power-Down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
8.10 Release from Deep Power-Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
9.  
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
10. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
11. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
12. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
14. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
15. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
15.1 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
16. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
16.1 SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . 33  
17. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
4
S19FL064P MirrorBit® ROM  
S19FL064P_00_01 July 29, 2009  
D a t a S h e e t ( P r e l i m i n a r y )  
Figures  
Figure 2.1  
Figure 6.1  
Figure 6.2  
Figure 7.1  
Figure 8.1  
Figure 8.2  
Figure 8.3  
Figure 8.4  
Figure 8.5  
Figure 8.6  
Figure 8.7  
Figure 8.8  
Figure 8.9  
16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 15  
Dual Output Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Quad Output Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
DUAL I/O High Performance Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Continuous Dual I/O High Performance Read Instruction Sequence . . . . . . . . . . . . . . . . . . 19  
QUAD I/O High Performance Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Continuous QUAD I/O High Performance Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . 21  
Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 21  
Figure 8.10 Read-ID (RDID) Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 8.11 Deep Power-Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 8.12 Release from Deep Power-Down (RES) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 8.13 Release from Deep Power-Down and RES Command Sequence . . . . . . . . . . . . . . . . . . . . 25  
Figure 9.1  
Figure 9.2  
Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Power-down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 11.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 11.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figure 14.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 15.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 15.2 SPI Mode 0 (0,0) Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 15.3 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 15.4 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
July 29, 2009 S19FL064P_00_01  
S19FL064P MirrorBit® ROM  
5
D a t a S h e e t ( P r e l i m i n a r y )  
Tables  
Table 5.1  
Table 7.1  
Table 8.1  
Table 8.2  
Table 8.3  
Table 9.1  
Table 12.1  
Table 13.1  
Table 14.1  
S19FL064P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9  
Configuration Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
Manufacturer & Device ID - RDID (JEDEC 9Fh): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22  
READ_ID Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22  
Power-Up / Power-Down Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28  
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29  
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30  
6
S19FL064P MirrorBit® ROM  
S19FL064P_00_01 July 29, 2009  
D a t a S h e e t ( P r e l i m i n a r y )  
1. Block Diagram  
SRAM  
PS  
X
D
E
C
Array - L  
Array - R  
Logic  
RD  
DATA PATH  
IO  
2. Connection Diagrams  
Figure 2.1 16-pin Plastic Small Outline Package (SO)  
16  
15  
14  
SCK  
1
2
3
HOLD#/IO3  
VCC  
SI/IO0  
DNC  
DNC  
DNC  
DNC  
DNC  
13  
4
5
DNC  
DNC  
12  
6
11  
DNC  
GND  
IO2  
CS#  
7
10  
9
SO/IO1  
8
Note  
DNC = Do Not Connect (Reserved for future use)  
IO2 = NC on Single I/O use  
July 29, 2009 S19FL064P_00_01  
S19FL064P MirrorBit® ROM  
7
D a t a S h e e t ( P r e l i m i n a r y )  
3. Input/Output Descriptions  
Signal  
I/O  
Description  
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK.  
Functions as an input pin in Dual and Quad I/O modes.  
SO/IO1  
I/O  
Serial Data Input: Transfers instructions and addresses serially into the device. Device latches  
commands, addresses on SI on the rising edge of SCK. Functions as an output pin in Dual and  
Quad I/O mode.  
SI/IO0  
SCK  
I/O  
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on  
rising edge of SCK. Triggers output on SO after the falling edge of SCK.  
Input  
Chip Select: Places device in active power mode when driven low. Deselects device and places  
CS#  
Input SO at high impedance when high. After power-up, device requires a falling edge on CS# before  
any command is written.  
Hold: Pauses any serial communication with the device without deselecting it. When driven low,  
SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be  
driven low. Functions as an output pin in Quad I/O mode.  
HOLD#/IO3  
I/O  
I/O  
IO2  
VCC  
GND  
IO2: NC on Single I/O mode. Functions as an output pin in Quad I/O mode.  
Input Supply Voltage  
Input Ground  
4. Logic Symbol  
V
CC  
SO/IO1  
SI/IO0  
SCK  
CS#  
IO2  
HOLD#/IO3  
GND  
8
S19FL064P MirrorBit® ROM  
S19FL064P_00_01 July 29, 2009  
D a t a S h e e t ( P r e l i m i n a r y )  
5. Ordering Information  
The ordering part number is formed by a valid combination of the following:  
S19FL  
064  
P
M
F
0
001  
0
1
Packing Type (Note 1)  
1
=
Tube  
3
=
13” Tape and Reel  
Option  
0
=
Reserved for Future Use  
Unique ROM ID  
001 Unique ROM ID code (Note 2)  
=
Model Number  
16-pin SO package  
0
=
Package Materials  
Lead (Pb)-free  
F
=
Package Type  
SOIC package  
M
=
Device Technology  
P
=
0.09 µm MirrorBit® Process Technology  
Density  
064  
=
64 Mbit  
Device Family  
S19FL  
Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) MirrorBit ROM  
Note  
All S19FL-P devices are offered over the industrial temperature (-40°C to 85°C) range and 104 MHz (serial), 80 MHz (dual/quad) maximum  
clock rate.  
5.1  
Valid Combinations  
Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device.  
Table 5.1 S19FL064P Valid Combinations Table  
S19FL-P Valid Combinations  
Base Ordering Part Number  
Package & Material  
Model Number  
Unique ROM ID  
Option  
Packing Type  
S19FL064P  
MF  
0
XXX (Note 2)  
0
1, 3 (Note 1)  
Note  
1. Type 1 is standard. Specify other options as required.  
2. Unique ROM ID is assigned by the factory.  
July 29, 2009 S19FL064P_00_01  
S19FL064P MirrorBit® ROM  
9
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6. Spansion SPI Modes  
A microcontroller can use either of its two SPI modes to control Spansion SPI ROM devices:  
„ CPOL = 0, CPHA = 0 (Mode 0)  
„ CPOL = 1, CPHA = 1 (Mode 3)  
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for  
both modes.  
When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:  
„ SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)  
„ SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)  
Figure 6.1 Bus Master and Memory Devices on the SPI Bus  
SO  
SPI Interface with  
(CPOL, CPHA) =  
(0, 0) or (1, 1)  
SI  
SCK  
SCK SO SI  
SCK SO SI  
SCK SO SI  
Bus Master  
SPI Memory  
SPI Memory  
SPI Memory  
Device  
Device  
Device  
CS3 CS2 CS1  
CS#  
CS#  
CS#  
Note  
The Hold (HOLD#) signal should be driven high (logic level 1) or low (logic level 0) as appropriate.  
Figure 6.2 SPI Modes Supported  
CS#  
CPOL CPHA  
Mode 0  
SCK  
0
0
1
1
Mode 3  
SCK  
SI  
MSB  
SO  
MSB  
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7. Device Operations  
All Spansion SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device  
that supports an inactive clock while CS# is held low.  
7.1  
Dual and Quad I/O Mode  
The S19FL064P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode  
and the Dual/Quad I/O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows  
data to be transferred to or from the device at two to four times the rate of standard SPI devices. When  
operating in the Dual or Quad I/O High Performance Mode (BBh or EBh instructions), data can be read at fast  
speed using two or four data bits at a time, and the 3-byte address can be input two or four address bits at a  
time.  
7.2  
7.3  
Active Power and Standby Power Modes  
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high. The  
device then goes into the Standby Power mode, and power consumption drops to I . The Deep Power-  
Down (DP) command provides additional data protection against inadvertent signals. After writing the DP  
command the device reduces its power consumption to I  
SB  
.
DP  
Configuration Register  
The Configuration Register contains the control bits that can be read or set by specific commands.  
„ The QUAD bit is non-volatile and sets the pin out of the device to Quad mode; that is HOLD# becomes  
IO3. The instructions for Serial, Dual Output, and Dual I/O reads will function as normal. The HOLD#  
functionality will not work when the device is set in Quad mode.  
Table 7.1 Configuration Register Table  
Bit  
7
Bit Name  
NA  
Bit Function  
Description  
-
-
-
-
-
-
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
1 = Quad I/O  
6
NA  
5
NA  
4
NA  
3
NA  
2
NA  
1
0
QUAD  
NA  
Puts the device into Quad I/O mode  
-
0 = Dual or Serial I/O (Default)  
Not Used  
Note  
(Default) indicates the value of each Configuration Register bit set upon initial factory shipment.  
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7.4  
Hold Mode (HOLD#)  
The Hold input (HOLD#) stops any serial communication with the device.  
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, standard use). If the  
falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of  
SCK (non-standard use).  
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge  
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-  
standard use) See Figure 7.1.  
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the  
Hold mode.  
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains  
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the  
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,  
followed by driving CS# low.  
Note: The HOLD Mode feature is disabled during Quad I/O Mode.  
Figure 7.1 Hold Mode Operation  
SCK  
HOLD#  
Hold  
Hold  
Condition  
Condition  
(standard use)  
(non-standard use)  
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8. Command Definitions  
The host system must shift all commands, addresses, and data in and out of the device, beginning with the  
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte  
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on  
the rising edge of SCK. Table 8.1 lists the complete set of commands.  
Every command sequence begins with a one-byte command code. The command may be followed by  
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the  
command sequence has been written.  
The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Read (DOR),  
Quad Output Read (QOR), Dual I/O High Performance Read (DIOR), Quad I/O High Performance Read  
(QIOR), Read Status Register (RDSR), Read Configuration Register (RCR), Read Manufacturer and Device  
ID (READ_ID), Read Identification (RDID) and Release from Deep Power-Down and Read Electronic  
Signature (RES) command sequences are followed by a data output sequence on SO. CS# can be driven  
high after any bit of the sequence is output to terminate the operation.  
The instruction set is listed in Table 8.1.  
Table 8.1 Instruction Set  
Mode  
Bit  
Cycle  
Data  
Byte  
Cycle  
One byte Command  
Code  
Address  
Byte Cycle  
Dummy  
Byte Cycle  
Operation  
Command  
Description  
READ  
FAST_READ  
DOR  
(03h) 0000 0011  
(0Bh) 0000 1011  
(3Bh) 0011 1011  
(6Bh) 0110 1011  
(BBh) 1011 1011  
(EBh) 1110 1111  
(9Fh) 1001 1111  
(90h) 1001 0000  
Read Data bytes  
3
3
3
3
3
3
0
3
0
0
0
0
1
1
0
0
0
1
1
1
0
2
0
0
1 to ∞  
1 to ∞  
1 to ∞  
1 to ∞  
1 to ∞  
1 to ∞  
1 to 81  
1 to ∞  
Read Data bytes at Fast Speed  
Dual Output Read  
QOR  
Quad Output Read  
Read  
DIOR  
Dual I/O High Performance Read  
Quad I/O High Performance Read  
Read Identification  
QIOR  
RDID  
READ_ID  
Read Manufacturer and Device Identification  
Configuration  
Register  
RCR  
DP  
(35h) 0011 0101  
Read Configuration Register (CFG)  
0
0
0
1 to ∞  
(B9h) 1011 1001  
(ABh) 1010 1011  
Deep Power-Down  
0
0
0
0
0
0
0
0
Release from Deep Power-Down Mode  
Power Saving  
RES  
Release from Deep Power-Down and Read  
Electronic Signature  
(ABh) 1010 1011  
0
0
3
1 to ∞  
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8.1  
Read Data Bytes (READ)  
The Read Data Bytes (READ) command reads data from the memory array at the frequency (f  
) presented  
SCK  
at the SCK input, with a maximum speed of 40 MHz. The host system must first select the device by driving  
CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0). Each bit is  
latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a  
frequency f  
, on the falling edge of SCK.  
SCK  
Figure 8.1 and Table 8.1 on page 13 detail the READ command sequence. The first address byte specified  
can start at any location of the memory array. The device automatically increments to the next higher address  
after each byte of data is output. The entire memory array can therefore be read with a single READ  
command. When the highest address is reached, the address counter reverts to 00000h, allowing the read  
sequence to continue indefinitely.  
The READ command is terminated by driving CS# high at any time during data output.  
Figure 8.1 Read Data Bytes (READ) Command Sequence  
CS#  
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39  
Mode 3  
SCK  
Mode 0  
Command  
24 Bit Address  
23 22 21  
2
0
1
3
SI  
MSB  
Data Out 1  
Data Out 2  
Hi-Z  
SO  
6
4
2
7
1 0  
7
5
3
MSB  
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8.2  
Read Data Bytes at Higher Speed (FAST_READ)  
The FAST_READ command reads data from the memory array at the frequency (f  
) presented at the SCK  
SCK  
input, with a maximum speed of 104 MHz. The host system must first select the device by driving CS# low.  
The FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte.  
Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on  
SO at a frequency f  
, on the falling edge of SCK.  
SCK  
The FAST_READ command sequence is shown in Figure 8.2 and Table 8.1 on page 13. The first address  
byte specified can start at any location of the memory array. The device automatically increments to the next  
higher address after each byte of data is output. The entire memory array can therefore be read with a single  
FAST_READ command. When the highest address is reached, the address counter reverts to 000000h,  
allowing the read sequence to continue indefinitely.  
The FAST_READ command is terminated by driving CS# high at any time during data output.  
Figure 8.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence  
CS#  
33  
0
1
2
5
6
7
8
9
29 30  
32  
38 39 40 41  
44 45 46  
42 43  
Mode 3  
31  
34 35 36 37  
3
4
10  
28  
47  
SCK  
Mode 0  
24 Bit Address  
Dummy Byte  
Command  
23  
3
2
22 21  
1
0
6
5
4
2
0
1
7
3
SI  
Hi-Z  
3
7
6
4
2
1
0
5
7
SO  
MSB  
MSB  
DATA OUT 1  
DATA OUT 2  
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8.3  
Dual Output Read Mode (DOR)  
The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out  
2 bits at a time using 2 pins (SI/IO0 and SO/IO1) instead of 1 bit, at a maximum frequency of 80 MHz. The  
Dual Output Read mode effectively doubles the data transfer rate compared to the FAST_READ instruction.  
The host system must first select the device by driving CS# low. The Dual Output Read command is then  
written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge  
of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through the  
IO0 (SI) & IO1 (SO) pins at a frequency f  
on the falling edge of SCK.  
SCK  
The Dual Output Read command sequence is shown in Figure 8.3 and Table 8.1 on page 13. The first  
address byte specified can start at any location of the memory array. The device automatically increments to  
the next higher address after each byte of data is output. The entire memory array can therefore be read with  
a single Dual Output Read command. When the highest address is reached, the address counter reverts to  
00000h, allowing the read sequence to continue indefinitely.  
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.  
The Dual Output Read command is terminated by driving CS# high at any time during data output.  
Figure 8.3 Dual Output Read Instruction Sequence  
CS#  
0
1
2
5
6
7
8
9
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47  
3
4
10  
SCK  
24 Bit  
Address  
Instruction  
Dummy Byte  
SI Switches from Input to Output  
SI/IO0  
23 22 21  
6
3
2
1
0
7
*
6
5
4
3
2
1
0
6
4
2
0
6
4
5
2
0
1
*
Hi-Z  
3
5
3
1
7
7
*
7
*
SO/IO1  
Byte 1  
Byte 2  
*MSB  
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8.4  
Quad Output Read Mode (QOR)  
The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out  
4 bits at a time using 4 pins (SI/IO0, SO/IO1, IO2 and HOLD#/IO3) instead of 1 bit, at a maximum frequency  
of 80 MHz. The Quad Output Read mode effectively doubles the data transfer rate compared to the Dual  
Output Read instruction, and is four times the data transfer rate of the FAST_READ instruction.  
The host system must first select the device by driving CS# low. The Quad Output Read command is then  
written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge  
of SCK. Then the memory contents, at the address that are given, are shifted out four bits at a time through  
IO0 (SI), IO1 (SO), IO2, and IO3 (HOLD#) pins at a frequency f  
on the falling edge of SCK.  
SCK  
The Quad Output Read command sequence is shown in Figure 8.4 and Table 8.1 on page 13. The first  
address byte specified can start at any location of the memory array. The device automatically increments to  
the next higher address after each byte of data is output. The entire memory array can therefore be read with  
a single Quad Output Read command. When the highest address is reached, the address counter reverts to  
00000h, allowing the read sequence to continue indefinitely.  
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.  
The Quad Output Read command is terminated by driving CS# high at any time during data output.  
The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the  
S19FL device.  
Figure 8.4 Quad Output Read Instruction Sequence  
CS#  
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47  
0
1
2
3
4
5
6
7
8
9 10  
SCK  
24 Bit  
Address  
Instruction  
Dummy Byte  
SI Switches from Input to Output  
SI/IO0  
3
2
1
0
7
6
5
4
3
1
0
23 22 21  
0
1
0
1
2
*
0
1
4
5
4
5
0
4
4
5
4
*
Hi-Z  
Hi-Z  
5
1
5
SO/IO1  
IO2  
6
2
6
2
6
6
6
2
2
Hi-Z  
3
3
7
*
7
*
3
7
*
3
7
*
7
*
HOLD#/IO3  
DATA DATA DATA DATA  
OUT 1 OUT 2 OUT 3 OUT 4  
*MSB  
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8.5  
DUAL I/O High Performance Read Mode (DIOR)  
The Dual I/O High Performance Read instruction is similar to the Dual Output Read instruction, except that it  
improves throughput by allowing input of the address bits (A23-A0) using 2 bits per SCK via two input pins  
(SI/IO2 and SO/IO1), at a maximum frequency of 80 MHz.  
The host system must first select the device by driving CS# low. The Dual I/O High Performance Read  
command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with two  
bits latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out  
two bits at a time through IO0 (SI) and IO1 (SO).  
The DUAL I/O High Performance Read command sequence is shown in Figure 8.5 and Table 8.1  
on page 13. The first address byte specified can start at any location of the memory array. The device  
automatically increments to the next higher address after each byte of data is output. The entire memory  
array can therefore be read with a single DUAL I/O High Performance Read command. When the highest  
address is reached, the address counter reverts to 00000h, allowing the read sequence to continue  
indefinitely.  
In addition, address jumps can be done without exiting the Dual I/O High Performance Mode through the  
setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 8.5). This added feature  
removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble  
(bits 7-4) of the Mode bits control the length of the next Dual I/O High Performance instruction through the  
inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON’T  
CARE (“x”). If the Mode bits equal Axh, then the device remains in Dual I/O High Performance Read Mode  
and the next address can be entered (after CS# is raised high and then asserted low) without requiring the  
BBh instruction opcode, as shown in Figure 8.6, thus eliminating eight cycles for the instruction sequence.  
However, if the Mode bits are any value other than Axh, then the next instruction (after CS# is raised high and  
then asserted low) requires the instruction sequence, which is normal operation. The following sequences will  
release the device from Dual I/O High Performance Read mode; after which, the device can accept standard  
SPI instructions:  
1. During the Dual I/O High Performance Instruction Sequence, if the Mode bits are any value other  
than Axh, then the next time CS# is raised high and then asserted low, the device will be released  
from Dual I/O High Performance Read mode.  
2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and  
data input (IO0 & IO1) are not set for a valid instruction sequence, then the device will be released  
from Dual I/O High Performance Read mode.  
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.  
The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be  
driven high at any time during data output to terminate a read operation.  
Figure 8.5 DUAL I/O High Performance Read Instruction Sequence  
CS#  
0
1
2
3
4
5
6
7
8
9
10  
18 19 20 21 22 23 24 25 26 27 28 29 30 31  
SCK  
24 Bit  
Address  
Instruction  
IO0 & IO1 Switches from Input to Output  
2
2
6
4
5
6
2
6
4
5
6
4
5
0
1
0
1
20  
21  
2
0
1
22  
0
1
SI/IO0  
Hi-Z  
3
3
3
7
*
3
7
7
*
23  
7
*
SO/IO1  
*
*
Mode Bits  
Byte 1  
Byte 2  
*MSB  
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Figure 8.6 Continuous Dual I/O High Performance Read Instruction Sequence  
CS#  
SCK  
0
1
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
24 Bit  
Address  
IO0 & IO1 Switches from Input to Output  
22 20  
2
6
4
2
0
1
6
4
5
2
0
6
0
1
6
4
5
2
0
1
SI/IO0  
SO/IO1  
23  
7
*
21  
3
3
3
5
3
7
*
1
7
*
7
*
*
Byte 2  
*MSB  
Byte 1  
Mode Bits  
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8.6  
Quad I/O High Performance Read Mode (QIOR)  
The Quad I/O High Performance Read instruction is similar to the Quad Output Read instruction, except that  
it further improves throughput by allowing input of the address bits (A23-A0) using 4 bits per SCK via four  
input pins (SI/IO0, SO/IO1, IO2 and HOLD#/IO3), at a maximum frequency of 80 MHz.  
The host system must first select the device by driving CS# low. The Quad I/O High Performance Read  
command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with four  
bits latched on the rising edge of SCK. Note that four dummy clocks are required prior to the data input. Then  
the memory contents, at the address that is given, are shifted out four bits at a time through IO0 (SI), IO1  
(SO), IO2, and IO3 (HOLD#).  
The Quad I/O High Performance Read command sequence is shown in Figure 8.7 and Table 8.1 on page 13.  
The first address byte specified can start at any location of the memory array. The device automatically  
increments to the next higher address after each byte of data is output. The entire memory array can  
therefore be read with a single Quad I/O High Performance Read command. When the highest address is  
reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.  
In addition, address jumps can be done without exiting the Quad I/O High Performance Mode through the  
setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 8.7). This added feature the  
removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble  
(bits 7-4) of the Mode bits control the length of the next Quad I/O High Performance instruction through the  
inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON'T  
CARE (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode  
and the next address can be entered (after CS# is raised high and then asserted low) without requiring the  
EBh instruction opcode, as shown in Figure 8.8, thus eliminating eight cycles for the instruction sequence.  
The following sequences will release the device from Quad I/O High Performance Read mode; after which,  
the device can accept standard SPI instructions:  
1. During the Quad I/O High Performance Instruction Sequence, if the Mode bits are any value other  
than Axh, then the next time CS# is raised high and then asserted low the device will be released  
from Quad I/O High Performance Read mode.  
2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and  
data input (IO0, IO1, IO2, & IO3) are not set for a valid instruction sequence, then the device will be  
released from Quad I/O High Performance Read mode.  
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.  
The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be  
driven high at any time during data output to terminate a read operation.  
Figure 8.7 QUAD I/O High Performance Instruction Sequence  
CS#  
0
1
2
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22 23 24 25 26  
SCK  
24 Bit  
Address  
Instruction  
IO’s Switches from Input to Output  
SI/IO0  
16  
0
1
0
4
20  
0
1
2
3
4
5
4
5
0
4
Hi-Z  
5
17  
18  
19  
1
5
6
21  
22  
1
2
3
SO/IO1  
Hi-Z  
Hi-Z  
IO2  
6
6
6
2
2
7
7
3
3
7
HOLD#/IO3  
23  
7
*
*
*
*
*
DUMMY DUMMY  
Mode Bits  
Byte 1  
Byte 2  
*MSB  
20  
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Figure 8.8 Continuous QUAD I/O High Performance Instruction Sequence  
CS#  
SCK  
0
1
4
5
6
7
8
9
10 11  
12 13 14 15 16  
24 Bit  
Address  
IO’s Switches from Input to Output  
16  
20  
SI/IO0  
0
0
4
0
4
4
5
0
1
4
5
17  
21  
22  
5
6
1
2
3
1
5
6
1
2
3
SO/IO1  
IO2  
18  
6
2
6
2
7
7
*
3
3
HOLD#/IO3  
7
*
19  
7
23  
*
*
*
DUMMY  
DUMMY  
Mode Bits  
Byte 1  
Byte 2  
*MSB  
8.7  
Read Identification (RDID)  
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the  
two-byte device identification. The manufacturer identification is assigned by JEDEC; for Spansion devices, it  
is 01h. The device identification (2 bytes) is assigned by the device manufacturer.  
See Table 8.2 on page 22 for device ID data.  
The host system must first select the device by driving CS# low. The RDID command is then written to SI,  
and each bit is latched on the rising edge of SCK. The 3-byte device identification data is output from the  
memory array on SO at a frequency f  
, on the falling edge of SCK.  
SCK  
The RDID command sequence is shown in Figure 8.9 and Table 8.1 on page 13.  
Driving CS# high after the device identification data has been read at least once terminates the RDID  
command. Driving CS# high at any time during data output also terminates the RDID operation.  
Figure 8.9 Read Identification (RDID) Command Sequence and Data-Out Sequence  
CS#  
1
28  
30  
29  
31  
2
3
4
5
6
18  
17  
Mode 3  
0
7
14 15 16  
8
9
10 11 12 13  
SCK  
SI  
Mode 0  
Command  
Manufacturer Identification  
Device Identification  
Hi-Z  
0
1
3
2
14  
13  
SO  
15  
MSB  
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Table 8.2 Manufacturer & Device ID - RDID (JEDEC 9Fh):  
Manuf.  
Device Id  
ID  
# Extended  
bytes  
Device  
Byte 0  
Byte 1  
Byte 2  
Byte 3  
S19FL064P SPI ROM  
01h  
02h  
16h  
4Dh  
Notes  
1. Byte 0 is Manufacturer ID of Spansion.  
2. Byte 1 & 2 is Device Id.  
3. Byte 3 is Extended Device Information String Length, to indicate how many Extended Device Information bytes will follow.  
4. Bytes 4, 5 and 6 are Spansion reserved (do not use).  
5. For Bytes 07h-0Fh and 3Dh-3Fh, the data will be read as 0xFF.  
6. Bytes 10h-50h are factory programmed per JEDEC standard.  
8.8  
Read-ID (READ_ID)  
The READ_ID instruction provides the S19FL064P manufacturer and device information and is provided as  
an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC  
Read Identification (RDID) commands.  
The instruction is initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code  
“90h” followed by a 24-bit address (which is either 00000h or 00001h). Following this, the Manufacturer ID  
and the Device ID are shifted out on the SO output pin starting after the falling edge of the SCK serial clock  
input signal. If the 24-bit address is set to 000000h, the Manufacturer ID is read out first followed by the  
Device ID. If the 24-bit address is set to 000001h, then the Device ID is read out first followed by the  
Manufacturer ID. The Manufacturer ID and the Device ID are always shifted out on the SO output pin with the  
MSB first, as shown in Figure 10-14. Once the device is in Read-ID mode, the Manufacturer ID and Device ID  
output data toggles between address 000000H and 000001H until terminated by a low to high transition on  
the CS# input pin. The maximum clock frequency for the Read-ID (90h) command is at 104 MHz  
(FAST_READ). The Manufacturer ID & Device ID is output continuously until terminated by a low to high  
transition on CS# chip select input pin.  
Figure 8.10 Read-ID (RDID) Command Timing Diagram  
CS#  
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47  
SCK  
Instruction  
24-Bit Address  
SI  
23  
21  
2
22  
3
1
0
MSB  
Manufacture Identification  
Device Identification  
High Impedance  
7
6
5
4
3
2
1
SO  
0
Table 8.3 READ_ID Data-Out Sequence  
Address  
00000h  
00001h  
Uniform  
01h  
Manufacturer Identification  
Device Identification  
16h  
22  
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8.9  
Deep Power-Down (DP)  
The Deep Power-Down (DP) command provides the lowest power consumption mode of the device. It is  
intended for periods when the device is not in active use, and ignores all commands except for the Release  
from Deep Power-Down (RES) command. The standard standby mode, which the device goes into  
automatically when CS# is high (and all operations in progress are complete), should generally be used for  
the lowest power consumption when the quickest return to device activity is required.  
The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the  
entire duration of the DP sequence. The command sequence is shown in Figure 8.11 and Table 8.1  
on page 13.  
The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise  
the device does not execute the command. After a delay of t the device enters the DP mode and current  
DP,  
reduces from I to I (see Table 13.1 on page 29).  
SB  
DP  
Once the device has entered the DP mode, all commands are ignored except the RES command (which  
releases the device from the DP mode). The RES command also provides the Electronic Signature of the  
device to be output on SO, if desired (see Section 8.10 and 8.10.1).  
DP mode automatically terminates when power is removed, and the device always powers up in the standard  
standby mode.  
Figure 8.11 Deep Power-Down (DP) Command Sequence  
CS#  
t
DP  
0
1
2
3
4
5
6
7
Mode 3  
SCK  
Mode 0  
Command  
SI  
Hi-Z  
SO  
Standby Mode  
Deep Power-down Mode  
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8.10 Release from Deep Power-Down (RES)  
The device requires the Release from Deep Power-Down (RES) command to exit the Deep Power-Down  
mode. When the device is in the Deep Power-Down mode, all commands except RES are ignored.  
The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire  
duration of the sequence. The command sequence is shown in Figure 8.12 and Table 8.1 on page 13.  
The host system must drive CS# high t  
after the 8-bit RES command byte. The device transitions  
RES(max)  
from DP mode to the standby mode after a delay of t  
can execute any read command.  
(see Figure 15.1). In the standby mode, the device  
RES  
Figure 8.12 Release from Deep Power-Down (RES) Command Sequence  
CS#  
7
0
2
3
5
1
4
6
Mode 3  
SCK  
Mode 0  
tRES  
Command  
SI  
Hi-Z  
SO  
Deep Power-down Mode  
Standby Mode  
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8.10.1  
Release from Deep Power-Down and Read Electronic Signature (RES)  
The device features an 8-bit Electronic Signature, which can be read using the RES command. See  
Figure 8.13 and Table 8.1 on page 13 for the command sequence and signature value. The Electronic  
Signature is not to be confused with the identification data obtained using the RDID command. The device  
offers the Electronic Signature so that it can be used with previous devices that offered it; however, the  
Electronic Signature should not be used for new designs, which should read the RDID data instead.  
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each  
bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is  
shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the  
Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to  
output the Electronic Signature repeatedly.  
When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of t  
, as  
RES  
previously described. The RES command always provides access to the Electronic Signature of the device  
and can be applied even if DP mode has not been entered.  
Figure 8.13 Release from Deep Power-Down and RES Command Sequence  
CS#  
2
28 29 30  
31 32 33 34  
1
8
36 37  
35  
9
38 39  
0
3
4
5
6
7
10  
SCK  
t
RES  
3 Dummy Bytes  
Command  
SI  
3
1
0
2
23 22  
MSB  
21  
Electronic ID  
Hi-Z  
7
6
5
4
3
2
1
0
SO  
MSB  
Deep Power-Down Mode  
Standby Mode  
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9. Power-up and Power-down  
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied  
on V , and must not be driven low to select the device until V reaches the allowable values as follows  
CC  
CC  
(see Figure 9.1 and Table 9.1 on page 27):  
„ At power-up, V (min.) plus a period of t  
CC  
PU  
„ At power-down, GND  
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.  
At power-up, the device is in standby mode (not Deep Power-Down mode) and the WEL bit is reset (0).  
Each device in the host system should have the V rail decoupled by a suitable capacitor close to the  
CC  
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the V feed.  
CC  
When V drops from the operating voltage to below the minimum V threshold at power-down, all  
CC  
CC  
operations are disabled and the device does not respond to any commands.  
Figure 9.1 Power-Up Timing Diagram  
Vcc  
(max)  
cc  
V
(min)  
cc  
V
tPU  
Full Device Access  
Time  
Figure 9.2 Power-down and Voltage Drop  
Vcc  
V
(max)  
CC  
No Device Access Allowed  
V
(min)  
CC  
Device Access  
Allowed  
t
PU  
V
(cut-off)  
CC  
V
(low)  
CC  
t
PD  
Time  
26  
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Table 9.1 Power-Up / Power-Down Voltage and Timing  
Symbol  
VCC(min)  
CC(cut-off)  
Parameter  
VCC (minimum operation voltage)  
Min  
2.7  
2.4  
Max  
Unit  
V
V
VCC (Cut off where re-initialization is needed)  
V
0.2  
2.3  
V
VCC (Low voltage for initialization to occur at read/standby)  
VCC (Low voltage for initialization to occur at embedded)  
V
CC(low)  
tPU  
tPD  
VCC(min.) to device operation  
VCC (low duration time)  
300  
1.0  
µs  
µs  
10. Initial Delivery State  
The Configuration Register contains 00h (all bits are set to 0).  
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11. Electrical Specifications  
11.1 Absolute Maximum Ratings  
Description  
Rating  
-65°C to +150°C  
-0.5V to VCC+0.5V  
200 mA  
Ambient Storage Temperature  
Voltage with Respect to Ground: All Inputs and I/Os  
Output Short Circuit Current (Note 2)  
Note  
1. Minimum DC voltage on input or I/Os is -0.5V. During voltage transitions, inputs or I/Os may undershoot GND to -2.0V for periods of up to  
20 ns. See Figure 11.1. Maximum DC voltage on input or I/Os is VCC + 0.5V. During voltage transitions inputs or I/Os may overshoot to  
VCC + 2.0V for periods up to 20 ns. See Figure 11.2.  
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.  
3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;  
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is  
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.  
Figure 11.1 Maximum Negative Overshoot Waveform  
20 ns  
20 ns  
+0.8V  
–0.5V  
–2.0V  
20 ns  
Figure 11.2 Maximum Positive Overshoot Waveform  
20 ns  
VCC  
+2.0V  
VCC  
+0.5V  
2.0V  
20 ns  
20 ns  
12. Operating Ranges  
Table 12.1 Operating Ranges  
Description  
Rating  
Ambient Operating Temperature (TA)  
Industrial  
–40°C to +85°C  
2.7V to 3.6V  
Positive Power Supply  
Voltage Range  
Note  
Operating ranges define those limits between which functionality of the device is guaranteed.  
28  
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13. DC Characteristics  
This section summarizes the DC Characteristics of the device. Designers should check that the operating  
conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 14.1  
on page 30, when relying on the quoted parameters.  
Table 13.1 DC Characteristics (CMOS Compatible)  
Limits  
Symbol  
Parameter  
Supply Voltage  
Test Conditions  
Unit  
Min.  
2.7  
Typ*  
Max  
3.6  
VCC  
VIL  
V
V
Input Low Voltage  
Input High Voltage  
-0.3  
0.3 x VCC  
VIH  
0.7 x VCC  
VCC +0.5  
0.4  
V
VOL  
VOH  
Output Low Voltage  
Output High Voltage  
IOL = 1.6 mA, VCC = VCC min.  
IOH = -0.1 mA  
V
V
VCC-0.6  
VCC = VCC Max,  
ILI  
Input Leakage Current  
Output Leakage Current  
±2  
±2  
38  
µA  
µA  
V
IN = VCC or GND  
VCC = VCC Max,  
VIN = VCC or GND  
ILO  
At 80 MHz  
(Dual or Quad)  
Active Power Supply Current -  
READ  
(SO = Open)  
ICC1  
mA  
At 104 MHz (Serial)  
At 40 MHz (Serial)  
26  
15  
CS# = VCC  
SO + VIN = GND or VCC  
;
ISB1  
IPD  
Standby Current  
80  
3
200  
10  
µA  
µA  
CS# = VCC  
SO + VIN = GND or VCC  
;
Deep Power-down Current  
*Typical values are at TAI = 25°C and VCC = 3V  
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14. Test Conditions  
Figure 14.1 AC Measurements I/O Waveform  
0.8 VCC  
0.7 VCC  
0.5 VCC  
0.3 VCC  
Input Levels  
0.2 VCC  
Input and Output  
Timing Reference levels  
Table 14.1 Test Specifications  
Symbol  
Parameter  
Min  
Max  
Unit  
pF  
ns  
V
CL  
Load Capacitance  
30  
Input Rise and Fall Times  
Input Pulse Voltage  
5
0.2 VCC to 0.8 VCC  
0.3 VCC to 0.7 VCC  
0.5 VCC  
Input Timing Reference Voltage  
Output Timing Reference Voltage  
V
V
15. AC Characteristics  
Figure 15.1 AC Characteristics (Sheet 1 of 2)  
Symbol  
(Notes)  
Parameter  
(Notes)  
Min.  
(Notes)  
Typ  
(Notes)  
Max  
(Notes)  
Unit  
fR  
SCK Clock Frequency for RDID and READ command  
DC  
DC  
40  
SCK Clock Frequency for all others:  
FAST_READ(3)*, DP,  
RES,  
104 (serial)  
80 (dual/quad)  
fC  
MHz  
READ_ID  
t
WH, tCH  
Clock High Time (4)  
4.5  
4.5  
0.1  
0.1  
10  
ns  
ns  
t
WL, tCL  
CRT, tCLCH  
CFT, tCHCL  
tCS  
Clock Low Time (4)  
t
Clock Rise Time (slew rate)  
Clock Fall Time (slew rate)  
CS# High Time (Read Instructions)  
V/ns  
V/ns  
ns  
t
CS# Active Setup Time  
(relative to SCK)  
tCSS  
3
3
ns  
ns  
CS# Active Hold Time  
(relative to SCK)  
tCSH  
tSU:DAT  
tHD:DAT  
Data in Setup Time  
Data in Hold Time  
3
2
ns  
ns  
8 (Serial)Δ  
9.5 (Dual/Quad)Δ  
6.5 (Serial)∞  
tV  
Clock Low to Output Valid  
0
0
ns  
8 (Dual/Quad)∞  
7 (Dual/Quad)Ω  
tHO  
tDIS  
Output Hold Time  
ns  
ns  
Output Disable Time  
8
HOLD# Active Setup Time  
(relative to SCK)  
tHLCH  
tCHHH  
tHHCH  
3
3
3
ns  
ns  
ns  
HOLD# Active Hold Time  
(relative to SCK)  
HOLD# Non Active Setup Time  
(relative to SCK)  
30  
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Figure 15.1 AC Characteristics (Sheet 2 of 2)  
Symbol  
(Notes)  
Parameter  
(Notes)  
Min.  
(Notes)  
Typ  
(Notes)  
Max  
(Notes)  
Unit  
HOLD# Non Active Hold Time  
(relative to SCK)  
tCHHL  
3
ns  
tHZ  
tLZ  
tRES  
tDP  
HOLD# enable to Output Invalid  
HOLD# disable to Output Valid  
Deep Power-down to Standby Mode  
Time to enter Deep Power-down Mode  
8
8
ns  
ns  
µs  
µs  
30  
10  
Notes  
1. Δ Full Vcc range (2.7 – 3.6V) & CL = 30 pF  
2. ∞ Regulated Vcc range (3.0 – 3.6V) & CL = 30 pF  
3. Ω Regulated Vcc range (3.0 – 3.6V) & CL = 15 pF  
4. tWH + tWL must be less than or equal to 1/fC.  
15.1 Capacitance  
Symbol  
Parameter  
Input Capacitance  
Test Conditions  
OUT = 0V  
IN = 0V  
Min  
Max  
Unit  
CIN  
V
6
pF  
pF  
(applies to SCK, PO7-PO0, SI, CS#)  
Output Capacitance  
(applies to PO7-PO0, SO)  
COUT  
V
8
Figure 15.2 SPI Mode 0 (0,0) Input Timing  
tCS  
CS#  
SCK  
SI  
tCSH  
tCSS  
tCSS  
tCSH  
tSU:DAT  
tCRT  
tHD:DAT  
tCFT  
MSB IN  
LSB IN  
Hi-Z  
SO  
Figure 15.3 SPI Mode 0 (0,0) Output Timing  
CS#  
tWH  
SCK  
tV  
tWL  
tDIS  
tV  
tHO  
tHO  
SO  
LSB OUT  
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Figure 15.4 HOLD# Timing  
CS#  
tHHCH  
tHLCH  
tCHHL  
SCK  
SO  
tCHHH  
tHZ  
tLZ  
SI  
HOLD#  
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16. Physical Dimensions  
16.1  
SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width)  
NOTES:  
1.  
2.  
3.  
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.  
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.  
PACKAGE  
SO3 016 (inches)  
MS-013(D)AA  
SO3 016 (mm)  
MS-013(D)AA  
JEDEC  
DIMENSION D DOES NOT INCLUDE MOLD FLASH,  
PROTRUSIONS OR GATE BURRS. MOLD FLASH,  
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm  
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION  
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1  
DIMENSIONS ARE DETERMINED AT DATUM H.  
SYMBOL  
MIN  
MAX  
0.104  
0.012  
0.104  
0.020  
0.019  
0.013  
0.012  
MIN  
MAX  
2.65  
0.30  
2.55  
0.51  
0.48  
0.33  
0.30  
A
A1  
A2  
b
0.093  
0.004  
0.081  
0.012  
0.011  
0.008  
0.008  
2.35  
0.10  
2.05  
0.31  
0.27  
0.20  
0.20  
.
4.  
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE  
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE  
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF  
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD  
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP  
AND BOTTOM OF THE PLASTIC BODY.  
b1  
c
c1  
D
0.406 BSC  
10.30 BSC  
5.  
6.  
DATUMS A AND B TO BE DETERMINED AT DATUM H.  
E
0.406 BSC  
0.295 BSC  
.050 BSC  
10.30 BSC  
7.50 BSC  
1.27 BSC  
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR  
THE SPECIFIED PACKAGE LENGTH.  
E1  
e
7.  
8.  
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD  
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.  
L
0.016  
0.050  
0.40  
1.27  
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.  
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL  
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL  
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE  
LOWER RADIUS OF THE LEAD FOOT.  
L1  
L2  
N
.055 REF  
.010 BSC  
16  
1.40 REF  
0.25 BSC  
16  
h
0.10  
0.30  
0.25  
0.75  
8˚  
9.  
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,  
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX  
AREA INDICATED.  
θ
0˚  
5˚  
8˚  
0˚  
5˚  
θ1  
θ2  
15˚  
15˚  
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED  
FROM THE SEATING PLANE.  
0˚  
0˚  
3601 \ 16-038.03 \ 8.31.6  
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17. Revision History  
Section  
Description  
Revision 01 (July 29, 2009)  
Initial release.  
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D a t a S h e e t ( P r e l i m i n a r y )  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without  
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as  
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to  
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal  
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under  
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,  
the prior authorization by the respective government entity will be required for export of those products.  
Trademarks and Notice  
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under  
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this  
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,  
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any  
damages of any kind arising out of the use of the information in this document.  
Copyright © 2009 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™  
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names  
used are for informational purposes only and may be trademarks of their respective owners.  
July 29, 2009 S19FL064P_00_01  
S19FL064P MirrorBit® ROM  
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