S19FL128PMF0101--Datasheet/数据表在线中文翻译

S19FL128P MirrorBit^®ROM

128-Megabit CMOS 3.0 Volt MirrorBit ROM

with 104-MHz SPI (Serial Peripheral Interface) Bus

Data Sheet

S19FL128P MirrorBit^®ROM Cover Sheet

Notice to Readers: This document states the current technical specifications regarding the Spansion

product(s) described herein. Each product described herein may be designated as Advance Information,

Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.

Publication Number S19FL128P_00

Revision 03

Issue Date June 13, 2008

D a t a S h e e t

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of

product information or intended specifications throughout the product life cycle, including development,

qualification, initial production, and full production. In all cases, however, readers are encouraged to verify

that they have the latest information before finalizing their design. The following descriptions of Spansion data

sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more specific

products, but has not committed any design to production. Information presented in a document with this

designation is likely to change, and in some cases, development on the product may discontinue. Spansion

Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion Inc.

The information is intended to help you evaluate this product. Do not design in this product without

contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment

to production has taken place. This designation covers several aspects of the product life cycle, including

product qualification, initial production, and the subsequent phases in the manufacturing process that occur

before full production is achieved. Changes to the technical specifications presented in a Preliminary

document should be expected while keeping these aspects of production under consideration. Spansion

places the following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. The Preliminary status of this document indicates that product qualification has been

completed, and that initial production has begun. Due to the phases of the manufacturing process that

require maintaining efficiency and quality, this document may be revised by subsequent versions or

modifications due to changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations

wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first

page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes

are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include

those affecting the number of ordering part numbers available, such as the addition or deletion of a speed

option, temperature range, package type, or V_IOrange. Changes may also include those needed to clarify a

description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following

conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. Spansion Inc. deems the products to have been in sufficient production volume such

that subsequent versions of this document are not expected to change. However, typographical or

specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local sales office.

2

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

S19FL128P MirrorBit^®ROM

128 Megabit CMOS 3.0 Volt MirrorBit ROM

with 104 MHz SPI (Serial Peripheral Interface) Bus

Data Sheet

Distinctive Characteristics

Architectural Advantages

Performance Characteristics

Single power supply operation

Speed

– 104 MHz clock rate (maximum)

– Full voltage range: 2.7 to 3.6 V read operations

Device ID

Power Saving Standby Mode

– Standby Mode 200 µA (max)

– RDID (9Fh), READ_ID (90h) and RES (ABh) commands to read

manufacturer and device ID information

– Deep Power Down Mode 3 µA (typical)

– RES command one-byte electronic signature for backward

compatibility

Software Features

Process Technology

– SPI Bus Compatible Serial Interface

– Manufactured on 0.09 µm MirrorBit^®process technology

Package Option

Hardware Features

x8 Parallel Mode (for 16-pin SO package only)

– Industry Standard Pinouts

– 16-pin SO package (300 mils)

– 8-Contact WSON Package (6 x 8 mm)

Publication Number S19FL128P_00

Revision 03

Issue Date June 13, 2008

This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-

duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-

binations offered may occur.

D a t a S h e e t

Table of Contents

Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.

2.

3.

4.

5.

6.

7.

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.1

Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8.

9.

Parallel Mode (for 16-pin SO package only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

Read Data Bytes (READ: 03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Data Bytes at Higher Speed (FAST_READ: 0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Identification (RDID: 9Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Manufacturer and Device ID (READ_ID: 90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Deep Power Down (DP: B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Release from Deep Power Down (RES: ABh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Release from Deep Power Down and Read Electronic Signature (RES: ABh) . . . . . . . . . . . 22

Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

12. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

14. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

15. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

16. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

16.1 SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . . 30

16.2 WSON 8-contact (6 x 8 mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

17. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

Figures

Figure 2.1

Figure 2.2

Figure 6.1

Figure 6.2

Figure 7.1

Figure 9.1

Figure 9.2

Figure 9.3

Figure 9.4

Figure 9.5

Figure 9.6

Figure 9.7

Figure 9.8

Figure 9.9

16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8-Pin WSON Package (6 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Parallel Read Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 15

Read Identification Command Sequence and Data Out Sequence. . . . . . . . . . . . . . . . . . . . 16

Parallel Read_ID Command Sequence and Data Out Sequence . . . . . . . . . . . . . . . . . . . . . 17

Serial READ_ID Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Parallel Read_ID Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Release from Deep Power Down (RES) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9.10 Serial Release from Deep Power Down and

Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9.11 Parallel Release from Deep Power Down and

Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10.1 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15.1 SPI Mode 0 (0,0) Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 15.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 15.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

5

D a t a S h e e t

Tables

Table 5.1

Table 9.1

Table 9.2

Table 9.3

Table 10.1

Table 11.1

Table 12.1

Table 13.1

Table 14.1

Table 15.1

S19FL128P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Manufacturer & Device Identification, RDID (9Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

READ_ID Command and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Test Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

1. Block Diagram

SRAM

PS

X

D

E

C

Array - L

Array - R

Logic

RD

DATA PATH

IO

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

7

D a t a S h e e t

2. Connection Diagrams

Figure 2.1 16-pin Plastic Small Outline Package (SO)

16

15

14

SCK

1

2

3

HOLD#

VCC

SI

PO6

NC

PO2

PO1

PO0

13

4

5

PO5

PO4

12

6

11

PO3

GND

NC

CS#

7

10

9

SO/PO7

8

Figure 2.2 8-Pin WSON Package (6 x 8 mm)

CS#

SO

VCC

8

7

6

1

2

HOLD#

WSON

NC

3

4

SCK

SI

GND

5

8

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

3. Input/Output Descriptions

Signal Name

I/O

Description

SO (Signal Data Output)

Output

Transfers data serially out of the device on the falling edge of SCK.

Transfers parallel data into the device on the rising edge of SCK or out of the

device on the falling edge of SCK.

PO[7–0] (Parallel Data Input/Output)

SI (Serial Data Input)

Input/Output

Input

Transfers data serially into the device. Device latches commands, and addresses,

data on SI on the rising edge of SCK.

Provides serial interface timing. Latches commands, addresses, and data on SI on

rising edge of SCK. Triggers output on SO after the falling edge of SCK.

SCK (Serial Clock)

Input

Places device in active power mode when driven low. Deselects device and places

SO at high impedance when high. After power-up, device requires a falling edge on

CS# before any command is written.

CS# (Chip Select)

HOLD# (Hold)

Input

Pauses any serial communication with the device without deselecting it. When

driven low, SO is at high impedance, and all input at SI and SCK are ignored.

Requires that CS# also be driven low.

V

Input

Supply Voltage

Ground

CC

GND

4. Logic Symbol

V

CC

SO

SI

SCK

PO[7-0] (For 16-pin SO package)

CS#

HOLD#

GND

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

9

D a t a S h e e t

5. Ordering Information

The ordering part number is formed by a valid combination of the following:

S19FL

128

P

M

F

0

001

0

PACKING TYPE

0

1

3

=

Rserved for future use

Tube

13” Tape and Reel

OPTION

0

=

Reserved for Future Use

UNIQUE ROM ID

001 Unique ROM ID Code (Note 3)

=

MODEL NUMBER

No additional ordering options

0

=

PACKAGE MATERIALS

Lead (Pb)-free

F

=

PACKAGE TYPE

M

N

=

16-pin SO package

8-pin WSON package

DEVICE TECHNOLOGY

P

=

0.09 µm MirrorBit Process Technology

DENSITY

128

=

128 Mbit

DEVICE FAMILY

S19FL

3.0 Volt-only, Serial Peripheral Interface (SPI) MirrorBit ROM

Valid Combinations

Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device.

Table 5.1 S19FL128P Valid Combinations Table

S19FL128P Valid Combinations

Base Ordering

Package & Material

Model Number

Unique ROM ID

Option

Packing Type

Marking Spec

Part Number

S19FL128P

Notes

(FL128P) +

(Unique ROM ID)

MF, NF (Note 2)

0

XXX

0

1, 3

1. All S19FL-A devices are offered over the industrial temperature (-40°C to 85°C) range .

2. Contact your local sales office for availability.

3. Unique ROM ID is assigned by the factory.

10

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

6. Spansion SPI Modes

A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:

CPOL = 0, CPHA = 0 (Mode 0)

CPOL = 1, CPHA = 1 (Mode 3)

Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for

both modes.

When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:

SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)

SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)

Figure 6.1 Bus Master and Memory Devices on the SPI Bus

SO

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SI

SCK

SCK SO SI

Bus Master

SPI Memory

Device

CS3 CS2 CS1

HOLD#

CS#

HOLD#

CS#

HOLD#

CS#

Note

The Hold (HOLD#) signal should be driven high (logic level 1) or low (logic level 0) as appropriate.

Figure 6.2 SPI Modes Supported

CS#

CPOL CPHA

Mode 0

SCK

0

1

Mode 3

SCK

SI

MSB

SO

MSB

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

11

D a t a S h e e t

7. Device Operations

All Spansion SPI devices (S19FL-P) accept and output data in bytes (8 bits at a time).

7.1

Hold Mode (HOLD#)

The Hold input (HOLD#) stops any serial communication with the device.

The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, standard use). If the

falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of

SCK (non-standard use).

The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge

of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-

standard use) See Figure 7.1.

The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the

Hold mode.

CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains

unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the

device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,

followed by driving CS# low.

Figure 7.1 Hold Mode Operation

SCK

HOLD#

Hold

Condition

(standard use)

(non-standard use)

8. Parallel Mode (for 16-pin SO package only)

The parallel mode provides 8 bits of input/output. Entering Parallel mode requires issuing the Enter Parallel

Mode command (55h). After writing the Parallel Mode Entry command and pulling CS# high, the available

commands are Read, Release from Deep Power Down/Release from Deep Power Down and Read

Electronic Signature (RES), Deep Power Down (DP), Read Identification (RDID) and Read ID (READ_ID).

The flash memory will remain in Parallel mode until either the Parallel Mode Exit command (45h) is issued, or

until a power-down / power-up sequence has been completed, after which the flash memory will exit parallel

mode automatically and switch back to serial mode (no power-down will be necessary to switch back to serial

mode if the Parallel Mode Exit command is issued).

In parallel mode, the maximum SCK clock frequency is limited to 6 MHz for Read Data Bytes and 10 MHz for

other operations. PO[6-0] can be left unconnected if the Parallel Mode functions are not needed.

Fast Read command (0Bh) is not applicable in Parallel Mode.

12

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

9. Command Definitions

The host system must shift all commands, addresses, and data in and out of the device, beginning with the

most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte

command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on

the rising edge of SCK. Table 9.3 on page 23 lists the complete set of commands.

Every command sequence begins with a one-byte command code. The command may be followed by

address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the

command sequence has been written.

The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ) and Read Identification

(RDID) command sequences are followed by a data output sequence on SO. CS# can be driven high after

any bit of the sequence is output to terminate the operation.

9.1

9.1.1

Read Data Bytes (READ: 03h)

Serial Mode

The Read Data Bytes (READ-Serial Mode) command reads data from the memory array at the frequency

(f_SCK) presented at the SCK input, with a maximum speed of 40 MHz. The host system must first select the

device by driving CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0).

Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on

SO at a frequency f_SCK, on the falling edge of SCK.

Figure 9.1 and Table 9.3 on page 23 detail the READ command sequence. The first byte specified can be at

any location. The device automatically increments to the next higher address after each byte of data is output.

The entire memory array can therefore be read with a single READ command. When the highest address is

reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.

The READ command is terminated by driving CS# high at any time during data output.

Figure 9.1 Read Data Bytes (READ) Command Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10

28 29 30 31 32 33 34 35 36 37 38 39

Mode 3

SCK

Mode 0

Command

24-Bit Address

23 22 21

2

0

1

3

SI

MSB

Data Out 1

Data Out 2

Hi-Z

SO

6

4

2

7

1 0

7

5

3

MSB

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

13

D a t a S h e e t

9.1.2

Parallel Mode

In parallel mode, the maximum SCK clock frequency is 6 MHz. The device requires a single clock cycle

instead of eight clock cycles to access the next data byte. The memory array output will be the same as in the

serial mode. The only difference is that a byte of data is output per clock cycle instead of a single bit. This

means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles

instead of in 2,048 clock cycles.

Figure 9.2 Parallel Read Instruction Sequence

CS#

SCK

24-Bit

Instruction

Address

SI

Data Out

High Impedance

PO[7-0]

Notes

1. 1st Byte = “03h”.

2. 2nd Byte = Address 1, MSB first (bits 23 through 16).

3. 3rd Byte = Address 2, MSB first (bits 15 through 8).

4. 4th Byte = Address 3, MSB first (bits 7 through 0).

5. From the 5th Byte, SO will output the array data.

6. In parallel mode, the maximum clock frequency (Fsck) is 6 MHz.

7. For parallel mode operation, the device requires an Enter Parallel Mode command (55h) before the READ command. An Exit Parallel

Mode (45h) command or a power-down / power-up sequence is required to exit the parallel mode.

14

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

9.2

Read Data Bytes at Higher Speed (FAST_READ: 0Bh)

The FAST_READ command reads data from the memory array at the frequency (f_SCK) presented at the SCK

input, with a maximum speed of 104 MHz. The host system must first select the device by driving CS# low.

The FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte.

Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on

SO at a frequency f_SCK, on the falling edge of SCK.

The FAST_READ command sequence is shown in Figure 9.3 and Table 9.3. The first byte specified can be

at any location. The device automatically increments to the next higher address after each byte of data is

output. The entire memory array can therefore be read with a single FAST_READ command. When the

highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue

indefinitely.

The FAST_READ command is terminated by driving CS# high at any time during data output.

Figure 9.3 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence

CS#

33

0

1

2

5

6

7

8

9

29 30

32

38 39 40 41

44 45 46

42 43

Mode 3

31

34 35 36 37

3

4

10

28

47

SCK

Mode 0

24-Bit Address

Dummy Byte

Command

23

3

2

22 21

1

0

6

5

4

2

0

1

7

3

SI

Hi-Z

3

7

6

4

2

1

0

5

7

SO

MSB

DATA OUT 1

DATA OUT 2

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

15

D a t a S h e e t

9.3

9.3.1

Read Identification (RDID: 9Fh)

Serial Mode

The Read Identification (RDID) instruction opcode allows the 8-bit manufacturer identification to be read,

follow by two bytes of device identification. The manufacturer identification is assigned by JEDEC. The device

identification is assigned by the device manufacturer.

The device is first selected by driving the CS# chip select input pin to the logic low state. After this, the RDID

8-bit instruction opcode is shifted in onto the SI serial input pin. After the last bit of the RDID instruction

opcode is shifted into the device, a byte of manufacturer identification, two bytes of device identification and

two bytes of extended device identification will be shifted sequentially out of the SO serial output pin. Each bit

is shifted out during the falling edge of the SCK serial clock signal. The maximum clock frequency for the

RDID (9Fh) command is at 40 MHz (Normal Read).

The Read Identification (RDID) instruction sequence is terminated by driving the CS# chip select input pin to

the logic high state anytime during data output. After issuing any Read ID instruction opcodes (90h, 9Fh,

ABh), driving the CS# chip select input pin to the logic high state will automatically send the device into the

standby mode. Driving the CS# chip select input pin to the logic low state again will automatically send the

device out of the standby mode and into the active mode.

Figure 9.4 Read Identification Command Sequence and Data Out Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34

44 45 46 47

SCK

Instruction

SI

Extended Device Identification

Manufacturer / Device Identification

High Impedance

SO

23 22 21

MSB

3

2

1

0

15 14 13

MSB

3

2

1

0

16

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

9.3.2

Parallel Mode

In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle

instead of eight clock cycles to access the next data byte. The method of memory content output will be the

same compared to the serial mode. The only difference is that a byte of data is output per clock cycle instead

of a single bit. In this case, the manufacturer identification will be output during the first byte cycle and the

device identification during the second and third byte cycles out of the PO7-PO0 serial output pins. To read ID

in parallel mode requires a Parallel Mode Entry command (55h) to be issued before the RDID command.

Once in the parallel mode, the flash memory will not exit parallel mode until a Parallel Mode Exit (45h)

command is given to the flash device, or upon power down/power up sequence.

Figure 9.5 Parallel Read_ID Command Sequence and Data Out Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

11 12

SCK

Instruction

SI

Manufacturer/Device Identification

High Impedance

Byte

0

Byte

1

Byte Byte

Byte

4

2

3

PO[7-0]

Table 9.1 Manufacturer & Device Identification, RDID (9Fh)

Manufacturer Identification

Device Identification

Extended Device Identification

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

01h

20h

18h

03h

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

17

D a t a S h e e t

9.4

9.4.1

Read Manufacturer and Device ID (READ_ID: 90h)

Serial Mode

The READ_ID (90h) instruction identifies the Device Manufacturer ID and the Device ID. The instruction is

initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code “90h” followed by

a 24-bit address of XXXXX0h. (X: High or Low) Following this, the Manufacturer ID and the Device ID are

shifted out on SO output pin starting after the falling edge of the SCK serial clock input signal. The

Manufacturer ID and the Device ID are always shifted out on the SO output pin with the MSB first, as shown

in Figure 9.6. If the 24-bit address is set to XXXXX1h, then the Device ID is read out first followed by the

Manufacturer ID. Note that the upper 23 bits of the address do not have to be 0’s and can be don’t cares.

Once the device is in READ_ID mode, the Manufacturer ID and Device ID output data toggles between

address 000000H and 000001H until terminated by a low to high transition on the CS# input pin. After the first

24-bit address is provided, the user must wait 16 clock cycles for both the Manufacturer ID and Device ID to

be output on the SO output pin. The maximum clock frequency for the READ_ID (90h) command is at

104 MHz (Fast Read). Parallel Mode the maximum clock frequency is 10 Mhz.

The Manufacturer ID & Device ID is output continuously until terminated by a low to high transition on CS#

chip select input pin.

After issuing READ_ID instruction, driving the CS# chip select input pin to the logic high state will

automatically send the device into the standby mode. Driving the CS# chip select input pin to the logic low

state again will automatically sent the device out of the standby mode and into the active mode.

Figure 9.6 Serial READ_ID Instruction Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Instruction

24-Bit Address

SI

23 22 21 20 19 18 17 16

High Impedance

15 14 13 12 11 10

9

8

90h

High Impedance

SO

CS#

SCK

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

24-Bit Address

SI

7

6

5

4

3

2

1

0

Manufacturer ID

Device ID

High Impedance

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SO

MSB

18

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

9.4.2

Parallel Mode

The maximum clock frequency allowed on the SCK input pin in parallel mode is 10 MHz. The Parallel Mode

Entry command (55h) must be issued before writing the READ_ID command. Once in the parallel mode, the

flash memory will not exit parallel mode until a Parallel Mode Exit (45h) command is given to the flash device,

or upon power-down/power-up sequence.

Figure 9.7 Parallel Read_ID Instruction Sequence

CS#

20 21 22 23 24 25 26

33 34

27 28 29 30 31 32

0

1

2

3

4

5

6

7

8

9

10

SCK

2 Dummy

Bytes

Instruction

ADD (1)

15 14 13

MSB

3

2

1

0

7

6

5

4

3

2

1

0

SI

90h

High Impedance

Byte

1

Byte

2

PO[7-0]

Manufacture ID

Device ID

Table 9.2 READ_ID Command and Data

Description

Address

Data

01h

Manufacturer Identification

00000h

00001h

Device Identification (Memory Capacity)

17h

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

19

D a t a S h e e t

9.5

Deep Power Down (DP: B9h)

The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is

intended for periods when the device is not in active use, and ignores all commands except for the Release

from Deep Power Down (RES) command. The standard standby mode, which the device goes into

automatically when CS# is high (and all operations in progress are complete), should generally be used for

the lowest power consumption when the quickest return to device activity is required.

The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the

entire duration of the DP sequence. The command sequence is shown in Figure 9.8 and Table 9.3.

The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise

the device does not execute the command. After a delay of t_DP,the device enters the DP mode and current

reduces from I_SBto I_DP(see Table 13.1 on page 26).

Once the device has entered the DP mode, all commands are ignored except the RES command (which

releases the device from the DP mode). The RES command also provides the Electronic Signature of the

device to be output on SO, if desired (see sections 9.6 and 9.7).

DP mode automatically terminates when power is removed, and the device always powers up in the standard

standby mode.

Figure 9.8 Deep Power Down (DP) Command Sequence

CS#

t

DP

0

1

2

3

4

5

6

7

Mode 3

SCK

Mode 0

Command

SI

Hi-Z

SO/PO[7-0]

Standby Mode

Deep Power-down Mode

20

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

9.6

Release from Deep Power Down (RES: ABh)

The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down

mode. When the device is in the Deep Power Down mode, all commands except RES are ignored.

The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire

duration of the sequence. The command sequence is shown in Figure 9.9 and Table 9.3 on page 23.

The host system must drive CS# high t_RES(max)after the 8-bit RES command byte. The device transitions

from DP mode to the standby mode after a delay of t_RES(see Table 15.1 on page 27). In the standby mode,

the device can execute any read command.

Figure 9.9 Release from Deep Power Down (RES) Command Sequence

CS#

7

0

2

3

5

1

4

6

Mode 3

SCK

Mode 0

t_RES

Command

SI

Hi-Z

SO/PO[7-0]

Deep Power-down Mode

Standby Mode

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

21

D a t a S h e e t

9.7

9.7.1

Release from Deep Power Down and Read Electronic Signature (RES: ABh)

Serial Mode

This command reads the old-style Electronic Signature from the SO serial output pin. See Figure 9.10 and

Table 9.3 for the command sequence and signature value. Please note that the Electronic Signature only

consists of the Device ID portion of the 16-bit JEDEC ID that is read by the Read Identifier (RDID) instruction.

The old style Electronic Signature is supported for backward compatibility, and should not be used for new

software designs, which should instead use the JEDEC 16-bit Electronic Signature by issuing the Read

Identifier (RDID) command.

The device is first selected by driving the CS# chip select input pin to the logic low state. The RES command

is shifted in followed by three dummy bytes onto the SI serial input pin. After the last bit of the three dummy

bytes is shifted into the device, a byte of Electronic Signature will be shifted out of the SO serial output pin.

Each bit is shifted out during the falling edge of the SCK serial clock signal. The maximum clock frequency for

the RES (ABh) command is at 104 MHz.

The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles.

The RES instruction sequence is terminated by driving the CS# chip select input pin to the logic high state

anytime during data output. After issuing any Read ID commands (90h, 9Fh, ABh), driving the CS# chip

select input pin to the logic high state will automatically send the device into the standby mode. Driving the

CS# chip select input pin to the logic low state again will automatically sent the device out of the standby

mode and into the active mode.

Figure 9.10 Serial Release from Deep Power Down and

Read Electronic Signature (RES) Command Sequence

CS#

SCK

2

28 29 30

31 32 33 34

1

8

36 37

9

35

38

0

3

4

5

6

7

10

t

RES

3 Dummy Bytes

Command

SI

3

1

0

2

23 22

MSB

21

Hi-Z

7

6

5

4

3

2

1

SO

0

MSB

Electronic ID out

Standby Mode

Deep Power-down Mode

22

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

9.7.2

Parallel Mode

When the device is in parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a

single clock cycle instead of eight clock cycles to access the next data byte. The method of memory content

output will be the same compared to outside of parallel mode. The only difference is that a byte of data is

output per clock cycle instead of a single bit. In this case, the Electronic Signature will be output onto the

P0[7–0] serial output pins.

Figure 9.11 Parallel Release from Deep Power Down and

Read Electronic Signature (RES) Command Sequence

CS#

2

28 29 30

31 32 33 34

1

8

36 37

35

9

38

0

3

4

5

6

7

10

SCK

t

RES

3 Dummy Bytes

Command

SI

3

1

0

2

23 22

MSB

21

Hi-Z

PO[7-0]

Byte

1

Electronic ID

Standby Mode

Deep Power-down Mode

Notes

1. In parallel mode, the maximum access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).

2. To release the device from Deep Power Down and read Electronic ID in parallel mode, a Parallel Mode Enter command (55h) must be issued before the RES

command. The device will not exit parallel mode until a Parallel Mode Exit command (45h) is written, or upon power-down or power-up sequence.

3. Byte 1 will output the Electronic Signature.

9.8

Command Definitions

Table 9.3 Command Definitions

One-Byte

Address

Bytes

Dummy

Byte

Operation

Command

Description

Read Data Bytes

Command Code

03h (0000 0011)

0Bh (0000 1011)

9Fh (1001 1111)

90h (1001 0000)

55h (0101 0101)

45h (0100 0101)

B9h (1011 1001)

ABh (1010 1011)

Data Bytes

READ

3

0

3

0

1

0

1 to ∞

FAST_READ Read Data Bytes at Higher Speed

1 to ∞

Read

RDID

READ_ID

Entry

Read Identification

1 to 3

Read Manufacturer ID and Device ID

Enter x8 Parallel Mode

1 to ∞

0

Parallel Mode

Power Saving

Exit

Exit x8 Parallel Mode

DP

Deep Power Down

Release from Deep Power Down

RES

Release from Deep Power Down and

Read Electronic Signature

ABh (1010 1011)

0

3

1 to ∞

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

23

D a t a S h e e t

10. Power-up and Power-down

During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied

on V_CC, and must not be driven low to select the device until V_CCreaches the allowable values as follows

(see Figure 10.1 and Table 10.1):

At power-up, V_CC(min.) plus a period of t_PU

At power-down, V_SS

A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.

At power-up, the device is in standby mode (not Deep Power Down mode) and the WEL bit is reset (0).

Each device in the host system should have the V_CCrail decoupled by a suitable capacitor close to the

package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the V_CCfeed.

When V_CCdrops from the operating voltage to below the minimum V_CCthreshold at power-down, all

operations are disabled and the device does not respond to any commands.

Figure 10.1 Power-Up Timing Diagram

Vcc

(max)

cc

V

(min)

cc

V

t_PU

Full Device Access

Time

Table 10.1 Power-Up Timing Characteristics

Symbol

Parameter

Min

2.7

15

Max

Unit

V

(minimum)

CC(min)

CC

t

V

(min) to device operation

CC

ms

PU

24

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

11. Absolute Maximum Ratings

Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device

may result. These are stress ratings only and device operation at these or any other conditions beyond those

indicated in this section and in the Operating Ranges on page 25 section of this document is not implied.

Device operation for extended periods at the limits listed in this section may affect device reliability.

Table 11.1 Absolute Maximum Ratings

Description

Ambient Storage Temperature

Rating

–65°C to +150°C

Voltage with Respect to Ground: All Inputs and I/Os

–0.5 V to V +0.5 V

CC

Notes

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot V to –2.0 V for periods of

SS

up to 20 ns. See Figure 11.2. Maximum DC voltage on output and I/O pins is 3.6 V. During voltage transitions output pins may overshoot

to V + 2.0 V for periods up to 20 ns. See Figure 11.2.

CC

2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not

implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 11.1 Maximum Negative Overshoot Waveform

20 ns

+0.8 V

–0.5 V

–2 V

20 ns

Figure 11.2 Maximum Positive Overshoot Waveform

20 ns

V

_CC+2.0 V

_CC+0.5 V

2.0 V

V

20 ns

12. Operating Ranges

Table 12.1 Operating Ranges

Description

Rating

Ambient Operating Temperature (T )

A

Industrial

–40°C to +85°C

2.7 V to 3.6 V

Positive Power Supply

Voltage Range

Note

Operating ranges define those limits between which functionality of the device is guaranteed.

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

25

D a t a S h e e t

13. DC Characteristics

This section summarizes the DC Characteristics of the device. Designers should check that the operating

conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 14.1

on page 26, when relying on the quoted parameters.

Table 13.1 DC Characteristics (CMOS Compatible)

Parameter

Description

Supply Voltage

Test Conditions (See Note)

Min

Typ.

Max

Unit

V

2.7

3.6

V

CC

SCK = 0.1 V

/

CC

0.9V

104 MHz (Serial)

22

mA

CC

I

Active Read Current

CC1

40 MHz (Serial: Fast

Read Mode)

10

mA

SCK = 0.1 V

/

CC

0.9V

CC

3 MHz (Parallel Mode)

10

200

20

2

mA

µA

V

I

Standby Current

V

= GND or V , CS# = V

CC

SB

IN

CC

I

Deep Power Down Current

Input Leakage Current

Output Leakage Current

Input Low Voltage

= GND or V , CS# = V

3

DP

CC

I

= GND or V , V = V max

CC CC CC

LI

I

= GND to V , V = V max

2

LO

CC CC

CC

V

–0.3

0.3 V

CC

IL

V

Input High Voltage

0.7 V

V

+ 0.5

V

IH

CC

V

Output Low Voltage

Output High Voltage

I

= 1.6 mA, V = V

CC CC min

0.4

V

OL

OH

OL

V

= –0.1 mA

V

– 0.6

CC

V

OH

Note

Typical values are at T = 25°C and 3.0 V.

A

14. Test Conditions

Figure 14.1 AC Measurements I/O Waveform

0.8 V_CC

Input Levels

0.2 V_CC

0.7 V_CC

0.5 V_CC

0.3 V_CC

Input and Output

Table 14.1 Test Specifications

Symbol

Parameter

Min

Max

Unit

C

Load Capacitance

30

pF

ns

V

L

Input Rise and Fall Times

Input Pulse Voltage

5

0.2 V to 0.8 V

CC

Input Timing Reference Voltage

Output Timing Reference Voltage

0.3 V to 0.7 V

V

CC

0.5 V

V

CC

26

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

15. AC Characteristics

Table 15.1 AC Characteristics

Typ

Max

Symbol

Parameter

Min

(Notes)

Unit

40 (Serial)

6 (Parallel)

F

SCK Clock Frequency READ command

D.C.

MHz

SCK

CRT

SCK Clock Frequency for:

FAST_READ, RDID, READ_ID, DP, RES (Note 2)

104 (Serial)

10 (Parallel)

F

D.C.

MHz

V/ns

ns

0.1 (Serial)

0.25 (Parallel)

t

Clock Rise Time (Slew Rate)

Clock Fall Time (Slew Rate)

SCK High Time

0.1 (Serial)

0.25 (Parallel)

t

CFT

4.5 (Serial)

50 (Parallel)

t

WH

4.5 (Serial)

50 (Parallel)

t

SCK Low Time

ns

WL

100 (Serial)

20 (Parallel)

t

CS# High Time

ns

CS

t

CS# Setup Time (Note 1)

3

ns

CSS

t

CS# HOLD Time (Note 1)

CSH

t

HOLD# Setup Time (relative to SCK) (Note 1)

HOLD# Non-Active Hold Time (relative to SCK) (Note 1)

HOLD# Non-Active Setup Time (relative to SCK)

HOLD# Hold Time (relative to SCK)

HD

CD

HC

CH

8 (Serial)

20 (Parallel)

t

Output Valid

0

ns

V

t

Output Hold Time

Data in Hold Time

HO

2 (Serial)

10 (Parallel)

t

HD:DAT

3 (Serial)

10 (Parallel)

t

Data in Setup Time

ns

SU:DAT

t

Input Rise Time

Input Fall Time

5

ns

R

t

F

8 (Serial)

20 (Parallel)

t

HOLD# to Output Low Z (Note 1)

HOLD# to Output High Z (Note 1)

Output Disable Time (Note 1)

ns

LZ

8 (Serial)

20 (Parallel)

t

HZ

8 (Serial)

20 (Parallel)

t

DIS

t

CS# High to Deep Power Down Mode

Release DP Mode

3

µs

DP

t

30

RES

Notes

1. Not 100% tested.

2. FAST_READ is not valid in parallel mode.

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

27

D a t a S h e e t

Figure 15.1 SPI Mode 0 (0,0) Input Timing

t_CS

CS#

SCK

SI

t_CSH

t_CSS

t_CSH

t_SU:DAT

t_CRT

t_HD:DAT

t_CFT

MSB IN

LSB IN

Hi-Z

SO

Figure 15.2 SPI Mode 0 (0,0) Output Timing

CS#

t_WH

SCK

t_V

t_WL

t_DIS

t_V

t_HO

SO

LSB OUT

28

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

Figure 15.3 HOLD# Timing

CS#

t_HC

t_HD

t_CH

SCK

SO

t_CD

t_HZ

t_LZ

SI

HOLD#

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

29

D a t a S h e e t

16. Physical Dimensions

16.1 SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width)

NOTES:

1.

2.

3.

ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.

DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.

PACKAGE

SO3 016 (inches)

MS-013(D)AA

SO3 016 (mm)

MS-013(D)AA

JEDEC

DIMENSION D DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm

PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1

DIMENSIONS ARE DETERMINED AT DATUM H.

SYMBOL

MIN

MAX

0.104

0.012

0.104

0.020

0.019

0.013

0.012

MIN

MAX

2.65

0.30

2.55

0.51

0.48

0.33

0.30

A

A1

A2

b

0.093

0.004

0.081

0.012

0.011

0.008

2.35

0.10

2.05

0.31

0.27

0.20

.

4.

THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE

BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE

OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF

MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD

FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP

AND BOTTOM OF THE PLASTIC BODY.

b1

c

c1

D

0.406 BSC

10.30 BSC

5.

6.

DATUMS A AND B TO BE DETERMINED AT DATUM H.

E

0.406 BSC

0.295 BSC

.050 BSC

10.30 BSC

7.50 BSC

1.27 BSC

"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR

THE SPECIFIED PACKAGE LENGTH.

E1

e

7.

8.

THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD

BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.

L

0.016

0.050

0.40

1.27

DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL

IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL

CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OF THE LEAD FOOT.

L1

L2

N

.055 REF

.010 BSC

16

1.40 REF

0.25 BSC

16

h

0.10

0.30

0.25

0.75

8˚

9.

THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,

THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX

AREA INDICATED.

θ

0˚

5˚

8˚

0˚

5˚

θ1

θ2

15˚

10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED

FROM THE SEATING PLANE.

0˚

3601 \ 16-038.03 \ 8.31.6

30

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

16.2 WSON 8-contact (6 x 8 mm) No-Lead Package

(DATUM A)

D2

D

A

PIN #1 ID

R0.20

B

D2/2

N

NX L

1

2

E2/2

9.

E

E2

0.30 DIA TYP.

8.

2X

0.10 C

2X

1

2

K

N-1

N

TOP VIEW

0.10 C

0.05 C

4.

NX b

e

0.10.

0.05.

M

C A B

C

A

C

(ND-1)

X

e

9.

5.

SEATING PLANE

SEE DETAIL "A"

A1

SIDE VIEW

DATUM A

BOTTOM VIEW

L

L1

10.

e/2

TERMINAL TIP

4.

e

DETAIL "A"

NOTES:

QUAD FLAT NO LEAD PACKAGES (WSNB) - PLASTIC

DIMENSIONS

1. DIMENSIONING AND TOLERANCING CONFORMS TO

ASME Y14.5M-1994.

SYMBOL

MIN

NOM

1.27 BSC

8

MAX

NOTE

2. ALL DIMENSIONS ARE IN MILLIMETERS, SYM θ IS IN DEGREES.

e

N

3. N IS THE TOTAL NUMBER OF TERMINALS.

3

5

4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS

MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.

IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER

END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE

MEASURED IN THAT RADIUS AREA.

ND

L

4

0.45

0.35

4.70

6.30

0.50

0.55

0.45

4.90

6.50

b

0.40

4

D2

E2

D

4.80

5. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE.

6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm.

6.40

6.00 BSC

8.00 BSC

0.75

7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.

8. PIN #1 ID ON TOP WILL BE LASER MARKED.

E

A

0.70

0.00

0.80

0.05

9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED

HEAT SINK SLUG AS WELL AS THE TERMINALS.

A1

L1

θ

0.02

10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT.

0.15 MAX.

---

10

2

0

12

K

0.20 MIN.

3408\ 16-038.28a

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

31

D a t a S h e e t

17. Revision History

Section

Description

Revision 01 (June 28, 2007)

Initial release.

Revision 02 (July 2, 2007)

Global

Changed document status from Advance Information to Preliminary

Changed document status from Preliminary to Full Production

Revision 03 (June 13, 2008)

Global

32

S19FL128P MirrorBit^®ROM

S19FL128P_00_03 June 13, 2008

D a t a S h e e t

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as

contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal

operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,

the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under

development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this

document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,

merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any

damages of any kind arising out of the use of the information in this document.

ORNAND2^™, HD-SIM^™and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for

informational purposes only and may be trademarks of their respective owners.

June 13, 2008 S19FL128P_00_03

S19FL128P MirrorBit^®ROM

33