August 2005
rev 0.2
ASM3P1819N
Low Power Mobile VGA EMI Reduction IC
Features
The ASM3P1819N reduces electromagnetic interference
(EMI) at the clock source, allowing a system wide EMI
reduction for all the down stream clocks and data
dependent signals. The ASM3P1819N allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads, shielding, and other passive
components that are traditionally required to pass EMI
regulations.
FCC approved method of EMI attenuation
Provides up to 15dB EMI reduction
Generates low EMI spread spectrum clock
a
and a non-spread Reference Clock of the input
frequency
Optimized for frequency range from 20MHz to
40MHz
Internal loop filter minimizes external components
and board space
The ASM3P1819N modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
thereby decreasing the peak amplitude of its harmonics.
This result in significantly lower system EMI compared to
the typical narrow band signal produced by oscillators and
most clock generators.
Down Spread Deviation: -1.25%
Low inherent Cycle-to-Cycle jitter
3.3V Operating Voltage
CMOS/TTL compatible inputs and outputs
Low power CMOS design
Lowering EMI by increasing a signal’s bandwidth is called
“spread spectrum clock generation”. The ASM3P1819N
uses the most efficient and optimized modulation profile
approved by the FCC and is implemented by using a
proprietary all digital method
Supports notebook VGA and other LCD timing
controller applications
Power Down function for mobile application
Products are available for industrial temperature
range.
Available in 8 pin SOIC and TSSOP Packages
Applications
The ASM3P1819N is targeted towards EMI management
for memory and LVDS interfaces in mobile graphic chipsets
and high-speed digital applications such as PC peripheral
devices, consumer electronics and embedded controller
system.
Functional Description
The ASM3P1819N is
a
versatile spread spectrum
frequency modulator designed specifically for a wide range
of input clock frequencies from 20 to 40MHz. The
ASM3P1819N can generate an EMI reduced clock from
crystal, ceramic resonator, or system clock.
PD#
VDD
Block Diagram
PLL
Modulation
XIN
Frequency
Divider
Crystal
Oscillator
Output
Loop
Filter
Phase
VCO
Divider
Detector
Feedback
Divider
XOUT
REF
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
