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February 2005  
rev 0.4  
ASM3P2508SP  
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
Features  
The ASM3P2508SP uses the most efficient and  
optimized modulation profile approved by the FCC.  
ASM3P2508SP modulates the output of a PLL in order to  
“spread” the bandwidth of a synthesized clock, and more  
importantly, decreases the peak amplitudes of its  
harmonics. This results in a significantly lower system  
EMI compared to the typical narrow band signal produced  
by oscillators and most frequency generators. Lowering  
EMI by increasing a signal’s bandwidth is called ‘spread  
spectrum clock generation’ (SSCG).  
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Dual PLL based Architecture  
Operates with a 3.3V ±0.3V supply.  
Generates an EMI optimized Spread Spectrum  
PCI Clock output  
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Generates a high accuracy non Spread T1 clock of  
±25ppm accuracy.  
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Generates a non spread system reference clock  
Low power CMOS design.  
Input frequency: 25 MHz.  
Outputs:  
In addition to the SSCG output, ASM3P2508SP  
generates two high accuracy clock signals -  
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a  
20MHz Sys_ REF_CLK.  
Sys_ REF_CLK: 20 MHz  
T1 Clock: 25 MHz (±25 ppm)  
PCI_CLK: 33.33MHz Spread Spectrum  
Frequency deviation: -0.5% (Typ).  
Available in 8L SOIC Package.  
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Applications  
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The ASM3P2508SP is targeted towards Consumer,  
Industrial, Data and Telecommunications applications.  
Product Description  
The ASM3P2508SP is a versatile Dual PLL based Clock  
Synthesizer and Frequency Generator optimised and  
designed specifically for three clock frequencies. The  
Key Specifications  
Description  
Supply voltages  
Input Frequency  
Cycle-to-Cycle Jitter  
Output Duty Cycle  
Output Rise and Fall Time  
SSC Modulation Rate  
SSC Frequency Deviation  
Specification  
VDD = 3.3V ±0.3V  
25 MHz  
175 pS ( Max)  
45/55%  
1.1 nS (Max)  
30KHz (Typ)  
-0.5% (Typ)  
PCI_CLK  
output  
from  
ASM3P2508SP  
reduces  
electromagnetic interference (EMI) at the clock source,  
allowing system wide reduction of EMI of all clock  
dependent signals. ASM3P2508SP allows significant  
system cost savings by reducing the number of circuit  
board layers, ferrite beads  
traditionally required to pass EMI regulations.  
&
shielding that are  
Block Diagram  
PWRDNB  
VDD  
Output  
Divider  
T1_CLK  
Input  
PLL 1  
Sys_REF_CLK  
Divider  
XIN/CLKIN  
XOUT  
Osc  
PCI_CLK  
PLL 2  
Output  
Divider  
Modulation  
VSS  
Alliance Semiconductor  
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com  
Notice: The information in this document is subject to change without notice.  
February 2005  
ASM3P2508SP  
rev 0.4  
Pin Configuration  
1
2
3
4
8
7
6
5
T1_CLK  
VSS  
XIN/CLKIN  
XOUT  
ASM3P2508SP  
VDD  
PCI_CLK  
PWRDNB  
Sys_REF_CLK  
Pin Description  
Pin#  
Pin Name  
Type  
Description  
Crystal connection or external reference frequency input. This pin has dual functions.  
1
XIN/CLKIN  
I
It can be connected either to an external crystal or an external reference clock.  
2
3
4
XOUT  
VDD  
O
P
Crystal connection. If using an external reference, this pin must be left unconnected.  
Power supply for the entire chip  
Sys_REF_CLK  
O
PLL 1 output System Reference Clock @ 20MHz  
Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not  
5
PWRDNB  
I
used. Power -down Mode shuts off all the Outputs.  
6
7
8
PCI_CLK  
VSS  
O
P
PLL 2 Spread spectrum clock output @ 33.33MHz  
Ground to entire chip. Connect to system ground  
Reference output T1 Clock @ 25MHz  
T1_CLK  
O
Typical Modulation Profile  
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
-0.5 to +7.0  
-65 to +125  
0 to 70  
Unit  
V
°C  
°C  
°C  
°C  
VDD, VIN  
TSTG  
TA  
Voltage on any pin with respect to Ground  
Storage temperature  
Operating temperature  
Ts  
TJ  
Max. Soldering Temperature (10 sec)  
Junction Temperature  
260  
150  
Static Discharge Voltage  
TDV  
2
KV  
(As per JEDEC STD 22- A114-B)  
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect  
device reliability.  
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
2 of 7  
Notice: The information in this document is subject to change without notice.  
February 2005  
rev 0.4  
ASM3P2508SP  
DC Electrical Characteristics  
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)  
Symbol  
VIL  
Parameter  
Min  
VSS - 0.3  
Typ  
–
–
–
–
3
3
–
–
Max  
0.8  
VDD + 0.3  
Unit  
V
V
µA  
µA  
mA  
mA  
V
Input low voltage  
Input high voltage  
Input low current  
Input high current  
VIH  
IIL  
IIH  
IXOL  
IXOH  
VOL  
VOH  
IDD  
2.0  
–
–
–
–
–
2.5  
–
-35  
35  
–
–
0.4  
–
XOUT output low current (@0.4V, VDD=3.3V)  
XOUT output high current (@2.5V, VDD=3.3V)  
Output low voltage (VDD = 3.3 V, IOL = 20 mA)  
Output high voltage (VDD = 3.3 V, IOH = 20 mA)  
Static supply current *  
V
µA  
–
10  
Dynamic supply current  
ICC  
–
20  
_
mA  
(3.3V, 33.33MHz, 25MHz , 20MHz and 15pF loading)  
VDD  
tON  
ZOUT  
Operating voltage  
Power-up time (first locked cycle after power up)**  
Clock output impedance  
3.0  
–
–
3.3  
–
50  
3.6  
5
–
V
mS  
Ω
* PWRDNB pin is pulled low  
** VDD and XIN/CLKIN input are stable, PWRDNB pin is made high from low.  
AC Electrical Characteristics  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
XIN  
Input frequency  
–
25  
33.33  
25  
–
MHz  
MHz  
PCI_CLK  
T1_CLK  
–
24.999375  
–
–
25.000625  
–
Output frequency  
MHz  
Sys_REF_CLK  
20  
Modulation Rate  
–
–
30  
-0.5  
0.9  
0.8  
150  
50  
–
–
KHz  
%
PCI_CLK (SSCG)  
Deviation  
tLH*  
tHL*  
Output rise time (measured at 0.8V to 2.0V)  
Output fall time (measured at 2.0V to 0.8V)  
0.7  
1.0  
nS  
0.6  
1.0  
175  
55  
nS  
pS  
%
tJC  
tD  
Jitter (cycle to cycle)  
–
Output duty cycle  
45  
* tLH and tHL are measured into a capacitive load of 15pF  
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
3 of 7  
Notice: The information in this document is subject to change without notice.  
February 2005  
ASM3P2508SP  
rev 0.4  
Typical Crystal Oscillator Circuit  
R1 = 510Ω  
Crystal  
C1 = 27 pF  
C2 = 27 pF  
Typical Crystal Specifications  
Fundamental AT cut parallel resonant crystal  
Nominal frequency  
25 MHz  
Frequency tolerance  
Operating temperature range  
Storage temperature  
Load capacitance  
± 25 ppm or better at 25°C  
-25°C to +85°C  
-40°C to +85°C  
18pF  
Shunt capacitance  
ESR  
7pF maximum  
25 Ω  
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
4 of 7  
Notice: The information in this document is subject to change without notice.  
February 2005  
ASM3P2508SP  
rev 0.4  
Package Information  
8-lead (150-mil) SOIC Package  
H
E
D
A2  
A
C
θ
e
A1  
L
B
Dimensions  
Symbol  
Inches  
Millimeters  
Min  
Max  
0.010  
0.069  
0.059  
0.020  
0.010  
Min  
0.10  
1.35  
1.25  
0.31  
0.18  
Max  
0.25  
1.75  
1.50  
0.51  
0.25  
A1  
A
0.004  
0.053  
0.049  
0.012  
0.007  
A2  
B
C
D
E
0.193 BSC  
0.154 BSC  
0.050 BSC  
0.236 BSC  
4.90 BSC  
3.91 BSC  
1.27 BSC  
6.00 BSC  
e
H
L
0.016  
0°  
0.050  
8°  
0.41  
0°  
1.27  
8°  
θ
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
5 of 7  
Notice: The information in this document is subject to change without notice.  
February 2005  
ASM3P2508SP  
rev 0.4  
Ordering Information  
Part Number  
Marking  
3P2508SP  
3P2508SP  
3P2508SPF  
3P2508SPF  
3I2508SP  
Package Type  
8-Pin SOIC, TUBE  
Temperature  
Commercial  
Commercial  
Commercial  
Commercial  
ASM3P2508SP-08ST  
ASM3P2508SP-08SR  
ASM3P2508SPF-08ST  
ASM3P2508SPF-08SR  
ASM3I2508SP-08ST  
ASM3I2508SP-08SR  
ASM3I2508SPF-08ST  
ASM3I2508SPF-08SR  
8-Pin SOIC, TAPE & REEL  
8-Pin SOIC, TUBE, Pb free  
8-Pin SOIC, TAPE & REEL, Pb free  
8-Pin SOIC, TUBE  
Industrial  
Industrial  
3I2508SP  
8-Pin SOIC, TAPE & REEL  
8-Pin SOIC, TUBE, Pb free  
8-Pin SOIC, TAPE & REEL, Pb free  
Industrial  
Industrial  
3I2508SPF  
3I2508SPF  
Device Ordering Information  
A S M 3 P 2 5 0 8 S P F - 0 8 T R  
OR - TSOT23 -6, T/R  
TT – TSSOP, TUBE  
TR - TSSOP, T/R  
VT – TVSOP, TUBE  
VR – TVSOP, T/R  
ST – SOIC, TUBE  
AR - SSOP, T/R  
SR - SOIC, T/R  
QR – QFN, T/R  
QT - QFN, TRAY  
BT - BGA, TRAY  
BR – BGA, T/R  
UR - SOT-23,T/R  
DR - QSOP, T/R  
DT – QSOP, TUBE  
AT – SSOP, TUBE  
PIN COUNT  
LEAD FREE PART  
PART NUMBER  
X = Automotive  
(-40C to +125C)  
I = Industrial P or n/c = Commercial  
(-40C to +85C)  
(0C to +70C)  
1 – reserved  
6 – power management  
7 – power management  
8 – power management  
9 – Hi performance  
0 - reserved  
2- Non PLL based  
3 – EMI Reduction  
4 – DDR support products  
5 – STD Zero Delay Buffer  
Alliance Semiconductor Mixed Signal Product  
Licensed under U.S Patent #s 5,488,627 and 5,631,921  
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
6 of 7  
Notice: The information in this document is subject to change without notice.  
February 2005  
rev 0.4  
ASM3P2508SP  
Alliance Semiconductor Corporation  
2595, Augustine Drive,  
Santa Clara, CA 95054  
Tel# 408-855-4900  
Copyright © Alliance Semiconductor  
All Rights Reserved  
Preliminary Information  
Part Number: ASM3P2508SP  
Document Version: v0.4  
Fax: 408-855-4999  
www.alsc.com  
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003  
© Copyright 2004 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are  
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective  
companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance  
assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's  
best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time,  
without notice. If the product described herein is under development, significant changes to these specifications are possible.  
The information in this product data sheet is intended to be general descriptive information for potential customers and users,  
and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume  
any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or  
implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a  
particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's  
Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively  
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under  
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parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction  
or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such  
life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all  
claims arising from such use.  
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
7 of 7  
Notice: The information in this document is subject to change without notice.