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HS-26C32RH  
TM  
Data Sheet  
August 2000  
File Number 3402.3  
Radiation Hardened Quad Differential Line  
Receiver  
Features  
• Electrically Screened to SMD # 5962-95689  
The Intersil HS-26C32RH is a differential line receiver  
designed for digital data transmission over balanced lines  
and meets the requirements of EIA Standard RS-422.  
Radiation hardened CMOS processing assures low power  
consumption, high speed, and reliable operation in the most  
severe radiation environments.  
• QML Qualified per MIL-PRF-38535 Requirements  
• 1.2 Micron Radiation Hardened CMOS  
- Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max)  
• Latchup Free  
• EIA RS-422 Compatible Inputs  
• CMOS Compatible Outputs  
The HS-26C32RH has an input sensitivity typically of 200mV  
over the common mode input voltage range of ±7V. The  
receivers are also equipped with input fail safe circuitry,  
which causes the outputs to go to a logic “1” when the inputs  
are open. Enable and Disable functions are common to all  
four receivers.  
• Input Fail Safe Circuitry  
• High Impedance Inputs when Disabled or Powered Down  
• Low Power Dissipation 138mW Standby (Max)  
• Single 5V Supply  
Specifications for Rad Hard QML devices are controlled  
by the Defense Supply Center in Columbus (DSCC). The  
SMD numbers listed here must be used when ordering.  
o
o
• Full -55 C to 125 C Military Temperature Range  
Pinouts  
Detailed Electrical Specifications for these devices are  
contained in SMD 5962-95689. A “hot-link” is provided  
on our homepage for downloading.  
HS1-26C32RH 16 LEAD CERAMIC SIDEBRAZE DIP  
MIL-STD-1835: CDIP2-T16  
TOP VIEW  
www.intersil.com/spacedefense/space.asp  
AIN  
AIN  
1
2
3
4
5
6
7
8
16 VDD  
15 BIN  
Ordering Information  
AOUT  
ENABLE  
COUT  
CIN  
14 BIN  
TEMP. RANGE  
o
ORDERING NO.  
5962F9568901QEC  
5962F9568901QXC  
5962F9568901V9A  
5962F9568901VEC  
5962F9568901VXC  
INTERNAL MKT. NO.  
HS1-26C32RH-8  
HS9-26C32RH-8  
HS0-26C32RH-Q  
HS1-26C32RH-Q  
HS9-26C32RH-Q  
( C)  
13 BOUT  
12 ENABLE  
11 DOUT  
10 DIN  
-55 to 125  
-55 to 125  
25  
CIN  
9
DIN  
GND  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
HS9-26C32RH 16 LEAD FLATPACK  
MIL-STD-1835: CDFP4-F16  
TOP VIEW  
HS1-26C32RH/PROTO HS1-26C32RH/PROTO  
HS9-26C32RH/PROTO HS9-26C32RH/PROTO  
AIN  
AIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
BIN  
Logic Diagram  
AOUT  
ENABLE  
COUT  
CIN  
BIN  
BOUT  
ENABLE  
DOUT  
DIN  
ENABLE ENABLE DIN DIN  
CIN CIN  
BIN BIN  
AIN AIN  
CIN  
+
-
+
-
+
-
+
-
GND  
DIN  
DOUT  
COUT  
BOUT  
AOUT  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
1
HS-26C32RH  
Propagation Delay Load Circuit  
Propagation Delay Timing Diagram  
TEST  
POINT  
DUT  
-V  
IN  
+2.5V  
-2.5V  
INPUT  
0V  
C
R
L
L
+V = 0V  
IN  
t
t
PHL  
PLH  
V
OH  
C
R
= 50pF  
L
L
V
= 50%  
S
OUTPUT  
= 1000Ω  
V
OL  
Three-State Low Timing Diagram  
Three-State High Timing Diagrams  
V
V
IH  
IH  
INPUT  
INPUT  
V
V
S
S
V
V
SS  
SS  
T
t
PZH  
PZL  
T
t
PHZ  
PLZ  
V
V
OH  
OZ  
V
V
V
V
W
OUTPUT  
OUTPUT  
T
W
T
V
V
OZ  
OL  
THREE-STATE LOW VOLTAGE LEVELS  
THREE-STATE HIGH VOLTAGE LEVELS  
PARAMETER  
HS-26C32RH  
UNITS  
PARAMETER  
HS-26C32RH  
UNITS  
V
4.50  
4.50  
2.25  
50  
V
V
V
%
V
V
V
4.50  
4.50  
2.25  
50  
V
V
V
%
V
V
DD  
DD  
V
V
V
V
V
V
V
V
IH  
S
IH  
S
T
T
V
+ 0.5  
V
- 0.5  
W
OL  
W
OH  
GND  
0
GND  
0
Three-State Low Load Circuit  
Three-State High Load Circuit  
V
DD  
TEST  
POINT  
DUT  
R
L
C
R
L
TEST  
POINT  
L
DUT  
C
L
C
R
= 50pF  
L
L
C
R
= 50pF  
L
= 1000Ω  
= 1000Ω  
L
2
HS-26C32RH  
Die Characteristics  
DIE DIMENSIONS:  
Top Metallization:  
84 mils x 130 mils  
M1: Mo/Tiw  
(2140µm x 3290µm)  
Thickness: 5800Å  
M2: Al/Si/Cu  
Thickness: 5800Å  
INTERFACE MATERIALS:  
Glassivation:  
Worst Case Current Density:  
Type: SiO  
2
5
2
<2.0 x 10 A/cm  
Thickness: 10kÅ ± 1kÅ  
Bond Pad Size:  
110µm x 100µm  
Metallization Mask Layout  
HS-26C32RH  
AIN  
(1)  
V
(16)  
BIN  
(15)  
DD  
(14) B  
IN  
AIN (2)  
(13) B  
OUT  
A
(3)  
OUT  
ENAB (4)  
(12) ENAB  
(11) D  
OUT  
C
(5)  
(6)  
OUT  
(10) D  
IN  
C
IN  
(7)  
(8)  
(9)  
GND  
CIN  
DIN  
3
HS-26C32RH  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Intersil Ltd.  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
Mercure Center  
8F-2, 96, Sec. 1, Chien-kuo North,  
Taipei, Taiwan 104  
Republic of China  
TEL: 886-2-2515-8508  
FAX: 886-2-2515-8369  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
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