UPC8158K-E1--Datasheet/数据表在线中文翻译

PRELIMINARY DATA SHEET

BIPOLAR ANALOG INTEGRATED CIRCUIT

µPC8158K

RF UP-CONVERTER WITH AGC FUNCTION + IF QUADRATURE MODULATOR IC

FOR DIGITAL MOBILE COMMUNICATION SYSTEMS

DESCRIPTION

The µPC8158K is a silicon microwave monolithic integrated circuit designed as quadrature modulator for digital

mobile communication systems. This MMIC consists of 0.8 GHz to 1.5 GHz up-converter and 100 MHz to 300 MHz

quadrature modulator which are equipped with AGC and power save functions. This configuration suits to IF

modulation system. The package is 28-pin QFN suitable for high density mounting. The chip is manufactured using

NEC’s. 20 GHz f^Tsilicon bipolar process NESAT^TMIII to realize low power consumption. Consequently the

µPC8158K can contribute to make RF blocks smaller size, higher performance and lower power consumption.

FEATURES

•

Supply voltage: V^CC= 2.7 to 4.0 V, I^CC= 28 mA @ V^CC= 3.0 V

Built-in LPF suppresses spurious multipled by TX local (LO1)

AGC amplifier is installed in local port of up converter: GCR = 35 dB MIN. @ fout = 1.5 GHz

Excellent performance: P^adj= –65 dBc TYP. @ ∆f = ±50 kHz, EVM = 1.2 % rms TYP.

External IF filter can be applied between modulator output and up converter input terminal.

APPLICATIONS

Digital cellular phones (PDC800M, PDC1.5G and so on)

•

ORDERING INFORMATION

Part Number

Package

Supplying Form

µPC8158K-E1

28-pin plastic QFN

Embossed tape 12 mm wide.

Pin 1 is in pull-out direction.

QTY 2.5 kp/Reel.

(5.1 × 5.5 × 0.95 mm)

Remark To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:

µPC8158K)

Caution Electro-static sensitive device

The information in this document is subject to change without notice.

Document No. P13831EJ1V1DS00 (1st edition)

Date Published January 1999 N CP(K)

Printed in Japan

©

1998

µPC8158K

INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (TOP View)

22

21

20

19

18

17

16

15

AGCcont

Up-Mix

RF^out

N.C.

23

24

25

14

13

12

LO2inb

LO2in

AGC

REG

V

CC

GND

Output Buffer

QMOD + AGC + Up-Mix

LPF

V

CC

REG

26

27

28

11

10

9

Fil1

Fil2

QMOD + AGC + Up-Mix

LO1in

φ

GND

I/Q-Mix

QMOD + AGC + Up-Mix

LO1inb

Phase

Shifter

1

2

3

4

5

6

7

8

2

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

QUADRATURE MODULATOR SERIES

f^LO1in

f^MODout

(MHz)

Up-Converter Phase

^RFout(MHz) Shifter

Part Number

Functions

I^CC(mA)

Package

20-pin

Application

CT-2, etc.

(MHz)

f

µPC8101GR

µPC8104GR

150 MHz Quad. Mod

15/@ 2.7 V 100 to 300

50 to 150

External

F/F

SSOP (225 mil)

RF Up-Converter + IF

Quad. Mod

28/@ 3.0 V

100 to 400

900 to 1 900 Doubler

+ F/F

Digital

Comm.

µPC8105GR

µPC8110GR

µPC8125GR

400 MHz Quad. Mod

16/@ 3.0 V

100 to 400

External

16-pin

SSOP (225 mil)

1GHz Direct Quad. Mod 24/@ 3.0 V

800 to 1 000

220 to 270

Direct

20-pin

PDC800 MHz,

SSOP (225 mil) etc.

RF Up-Converter + IF

Quad. Mod + AGC

36/@ 3.0 V

35/@ 3.0 V

1 800 to 2 000

PHS

µPC8126GR

µPC8126K

900 MHz Direct Quad.

Mod with Offset-Mixer

915 to 960

889 to 960

915 to 960

(LO pre-mixer)

PDC800 MHz

28-pin QFN

20-pin

µPC8129GR

×2LO IF Quad. Mod +

28/@ 3.0 V 200 to 800 100 to 400 800 to 1900

F/F

CR

GSM,

RF Up-Converter

SSOP (225 mil) DCS1800, etc.

µPC8139GR-7JH Transceiver IC

TX: 32.5

220 to 270

100 to 300

1 800 to 2 000

800 to 1 500

30-pin

PHS

(1.9 GHz Indirect Quad. RX: 4.8

Mod + RX-IF + IF VCO) /@ 3.0 V

TSSOP

(225 mil)

µPC8158K

RF Up-Converter + IF

Quad. Mod + AGC

28/@ 3.0 V

28-pin QFN

PDC800 M/

1.5 G

For outline of the quadrature modulator series, please refer to the application note ‘Usage of µPC8101, 8104,

8105, 8125, 8129’ (Document No. P13251E) and so on.

SYSTEM APPLICATION EXAMPLE

[PDC800 MHz/1.5 GHz]

SUB ANT

LNA

1st MIX

2nd MIX

SW

MAIN ANT

To DEMOD

RSSI OUT

RSSI

1st LO

LO2

2nd LO

PLL1

PLL2

SW

LO1

AGC

I

0°

φ (CR)

PA

90°

Q

PC8158K

µ

Filter

3

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

V^CC

Conditions

Rating

5.0

Unit

V

Supply Voltage

Pin11, 20 and 25,

T^A= +25°C

Power Save and AGC Control Pin

Applied Voltage

V^PS/V^AGC

Pin17, T^A= +25°C

5.0

V

Power Dissipation

P^D

T^A

T

^A= +85°C^Note

430

mW

°C

Operating Ambient Temperature

Storage Temperature

–40 to +85

–55 to +150

T^stg

°C

Note Mounted on double sided copper clad 50 × 50 × 1.6 mm epoxy glass PWB.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

V^CC

Test Conditions

Pin11, 20 and 25

MIN.

2.7

0

TYP.

MAX.

Unit

V

Supply Voltage

3.0

–

4.0

0.3

Power Save Voltage

V^PS

Pin17

V

AGC Control Voltage

V^AGCPS

T^A

1.0

–30

800

600

DC

–

2.5

V

Operating Ambient Temperature

Up-converter RF Output Frequency

LO2 Input Frequency

+25

–

+80

1500

1750

10

°C

f^RFout

f^LO2in

f^I/Qin

MHz

P^LO2in= –15 dBm

–

I/Q Input Frequency

V^I/Qin= 500 mV^P-PMAX.

(Differential input)

–

LO1 Input Level

P^LO1in

P^LO2in

V^I/Qin

–18

–

–15

420

–

–12

500

300

dBm

mV^P-P

MHz

LO2 Input Level

I/Q Input Amplitude

I, Ib, Q, Qb each

P^LO1in= –15 dBm

Up-converter Input Frequency

Modulator Output Frequency

LO1 Input Frequency

f^UPCONin

f^MODout

f^LO1in

100

4

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

ELECTRICAL CHARACTERISTICS

Conditions (Unless otherwise specified):

T^A= +25 °C, V^CC1 = V^CC2 = V^CC3 = 3.0 V, V^PS/V^AGC= 2.5 V,

I/Q (DC) = Ib/Qb (DC) = V^CC/2 = 1.5 V, V^I/Ibin= V^Q/Qbin= 500 mV^P-P(each), f^I/Qin= 2.625 kHz,

π/4DQPSK wave input, transmission rate 42 kbps, filter roll-off α = 0.5,

Modulation Pattern: <0000>

f^LO1in= 178.05 MHz, P^LO1in= –15 dBm

f^LO2in= 1619.05 MHz, P^LO2in= –15 dBm

f^RFout= 1441 MHz – f^I/Qin

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

UP-CONVERTER + QUADRATURE MODULATOR TOTAL

Total Circuit Current

I^{CC (TOTAL)}

No input signal

23.7

–

28

37.6

10

mA

V^PS≤ 0.5 V (Low),

Total Circuit Current at Power Save Mode

I^{CC (PS) TOTAL}

0.3

µA

No input signal

Total Output Power 1

P^RFout1

P^RFout2

LOL

V^AGC= 2.5 V

V^AGC= 1.0 V

f^LOL= f^LO1+ f^LO2

–15

–11.5

–52

–40

–50

40

–8

–46.5

–30

–

dBm

dBc

dB

Total Output Power 2

–56.5

LO Carrier Leak

–

Image Rejection (Side Band Leak)

I/Q 3rd order distortion

AGC Gain Control Range

Error Vector Magnitude

Adjacent channel interference

ImR

IM^{3 (I/Q)}

GCR

EVM

P^adj

–

V^AGC= 2 V → 1 V

35

–

MOD Pattern: PN9

1.2

3.0

%rms

dBc

∆f = ±50 kHz,

–

–65

–60

MOD Pattern: PN9

Spurious suppression

Power Save Rise Time

Power Save Fall Time

I/Q input impedance

I/Q input bias current

LO1 input VSWR

P^out(8fLO1)

T^{PS (Rise)}

T^{PS (Fall)}

Z^I/Q

fLO1 × 8, fLO1 × 8 (image)^Note

–

–70

2

–65

5

dBc

µs

kΩ

µA

–

V^{PS (Low)}→ V^{PS (High)}

V^{PS (High)}→ V^{PS (Low)}

–

2

5

Between pin I/Ib, Q/Qb

f^LO1= 100 M to 300 MHz

80

–

200

5

–

I^I/Q

13

–

Z^LO1

–

1.5:1

Note Without external LC between Fil1 and Fil2 pin on this frequency conditions.

Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.

Remark Electrical characteristics in this document is described for 1.5 GHz system.

5

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

PIN EXPLANATIONS

Supply

Voltage

(V)^Note

Symbol

Voltage

(V)

Function and Application

Internal Equivalent Circuit

No.

1

Iin

V^CC/2

–

Input for I signal. This input

impedance is 200 kΩ. In the case of

that I/Q input signals are single

ended, amplitude of the signal is

500 m V^P-Pmax.

2

Iinb

V^CC/2

–

Input for I signal. This input

impedance is 200 kΩ. In the case of

that I/Q input signals are single

ended, V^CC/2 biased DC signal

should be input. In the case of the

I/Q input signals are differential,

amplitude of the signal is 500 m V^P-P

max.

1

2

3

4

N.C.

Qinb

–

This pin is not connected to internal

circuit. This pin should be opened

or grounded.

–––––––––––––––––

V^CC/2

Input for Q signal. This input

impedance is 200 kΩ. In the case of

that I/Q input signals are single

ended, amplitude of the signal is

500 m V^P-Pmax.

5

Qin

V^CC/2

–

Input for I signal. This input

impedance is 200 kΩ. In the case of

that I/Q input signals are single

ended, V^CC/2 biased DC signal

should be input. In case of the I/Q

input signals are differential,

amplitude of the signal is 500 m V^P-P

max.

4

5

6

7

8

9

N.C.

–

These pins are not connected to

internal circuit. These pins should

be opened or grounded.

–––––––––––––––––

N.C.

LO1inb

–

2.98

Bypass pin of modulator’s local

input. This pin should be decoupled

with 330 pF capacitor.

9

10

11

LO1in

Local signal input for modulator.

This pin must be coupled with DC

cut capacitor 330 pF and should be

terminated with 51 Ω resistor.

V^CC

2.7 to 4.0

–

Supply voltage pin for modulator,

up-converter and AGC circuits.

–––––––––––––––––

Note Pin Voltages are measured on V^CC= 3.0 V.

6

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

Supply

Voltage

(V)

No.

Voltage

(V)^Note

Symbol

GND

Function and Application

Internal Equivalent Circuit

12

0

–

Ground pin for modulator, up-

converter and AGC circuits. This pin

should be grounded with minimum

inductance. Form the ground

pattern as widely as possible to

minimize ground impedance.

–––––––––––––––––

13

14

LO2in

–

1.8

Local signal input for modulator.

This pin must be coupled with DC

cut capacitor 33 pF and should be

terminated with 51 Ω resistor.

13

14

LO2inb

Bypass pin of up-converter’s local

signal input. This pin should be

decoupled with 33 pF capacitor.

15

16

N.C.

–

0

–

This pin is not connected to internal

circuit. This pin should be opened

or grounded.

–––––––––––––––––

GND

Ground pin for modulator, up-

converter and AGC circuits. This pin

should be grounded with minimum

inductance.

17

V^PS/V^AGC

–

Power save control pin for

modulator, up-converter and AGC

circuits. This pin also assigned as

gain control pin for AGC circuits.

Operation status with applied

voltages are as follows.

REG

17

V^PS/V^AGC(V)

0 to 0.4

STATE

AGC Cont

OFF (Sleep Mode)

On (AGC Mode)

1 to 2.5

18

19

N.C.

–

0

–

This pin is not connected to internal

circuit. This pin should be opened

or grounded.

–––––––––––––––––

GND

Ground pin for modulator, up-

converter and AGC circuits. This pin

should be grounded with minimum

inductance.

–––––––––––––––––

20

21

V^CC

2.7 to 4.0

0

–

Supply voltage pin for modulator,

up-converter and AGC circuits.

–––––––––––––––––

GND

Ground pin for RF output buffer.

This pin should be grounded with

minimum inductance.

Note Pin Voltages are measured on V^CC= 3.0 V.

7

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

Supply

Voltage

(V)

No.

Voltage

(V)^Note

Symbol

N.C.

Function and Application

Internal Equivalent Circuit

22

–

This pin is not connected to internal

circuit. This pin should be opened

or grounded.

–––––––––––––––––

23

RFout

–

1.75

RF output pin. This pin is emitter

follower which is low impedance

output port. This pin can be easily

matched to 50 Ω impedance using

external coupling and decoupling

capacitors.

External

23

24

25

N.C.

V^CC

–

These pins are not connected to

internal circuit. These pins should

be opened or grounded.

–––––––––––––––––

2.7 to 4.0

Supply voltage pin for RF output

buffer.

26

27

Fil1

Fil2

–

2.76

External inductor and capacitor can

supress harmonics spurious of LO1

frequency.

External

26

27

LC value should be determined

according to LO1 input frequency

and suppression level.

28

GND

0

–

Ground pin for modulator, up-

converter and AGC circuits. This pin

should be grounded with minimum

inductance. Form the ground

pattern as widely as possible to

minimize ground impedance.

–––––––––––––––––

Note Pin Voltages are measured on V^CC= 3.0 V.

8

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

TEST CIRCUIT

Voltage

Source

Voltage Source or

Pulse Pattern Generator

µ

Vector Signal

Analyzer or Spectrum

Analyzer

22 21 20 19 18

17 16 15

Signal Generator

Voltage

Source

AGCcont

51 Ω

33 pF

2 pF

RFout

23

µ

UP-CON

LO2b ₁₄

LO2in₁₃

BPF

51

Ω

33 pF

24

Voltage

Source

AGC

LPF

V

CC

GND

25

12

REG

µ

Fil1

Fil2

V

CC

26

27

11

BPF

I/Q Mixer

330 pF

LO1in₁₀

LO1b

Phase

Shifter

₂₈GND

9

51 Ω

Signal Generator

or Network

330 pF

Analyzer

1

2

3

4

5

6

7

8

100 pF

I/Q Signal

Generator

TEST CONDITIONS

f^LO1in= 178.05 MHz, P^LO1in= –15 dBm

f^LO2in= 1619.05 MHz, P^LO2in= –15 dBm

f^RFout= 1441 MHz – f^I/Qin

9

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

PACKAGE DIMENSIONS

28 pin plastic QFN (UNIT: mm)

4 – 0.5

Pin 28

Pin 1

0.22

0.5

7 × 0.5 = 3.5

5.5 ± 0.1

(5.5 ± 0.1)

(5.1)

(0.22)

(4.5)

0.5

Bottom View

10

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

RECOMMENDED SOLDERING CONDITIONS

This product should be soldered under the following recommended conditions. For soldering methods and

conditions other than those recommended below, contact your NEC sales representative.

µPC8158K

Recommended Condition

Soldering Method

Infrared Reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C or below

Time: 30 seconds or less (at 210°C)

Count: 2, Exposure limit^Note: None

IR35-00-2

–

Partial Heating

Pin temperature: 300°C

Time: 3 seconds or less (per side of device)

Exposure limit^Note: None

Note After opening the dry pack, keep it in a place below 25°C and 65% RH for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

For details of recommended soldering conditions for surface mounting, refer to information document

SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).

11

Preliminary Data Sheet P13831EJ1V1DS00

µPC8158K

NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96. 5