EFR32MG24A021F1024IM40--Datasheet/数据表在线中文翻译

EFR32MG24 ワイヤレス SoC ファミリデー

タシート

EFR32MG24 ワイヤレス SoC は Matter、OpenThread、Zigbee を

主な機能

使用したメッシュ IoT ワイヤレス接続に最適です。

• 32 ビット ARM® Cortex®-M33、最大動作

周波数 78.0 MHz

高性能 2.4 GHz RF、低消費電流、AI/ML ハードウェア・アクセラレーター、Secure Vault

などの主要機能により、IoT デバイス・メーカーは、リモートおよびローカルサイバー攻

撃から安全なスマートで堅牢かつエネルギー効率の高い製品を作成できます。最大

78.0 MHz、最大 1536 の Flash、256 kB の RAM で動作する Cortex®-M33 は、将来の成

長のための余地を残しながら、要求の厳しいアプリケーションのためのリソースを提供

します。

• 最大 1536 kB のフラッシュと 256 kB の

RAM

• 最大 +19.5 dBm 出力パワーの高性能無線

• 低アクティブおよびスリープ電流の高エ

ネルギー効率設計

対象アプリケーションには、以下が含まれます。

• セキュア・ボールト™

• AI/ML ハードウェア・アクセラレータ

• スマートホーム - ゲートウェイとハブ、センサー、スイッチ、ドアロック、スマート

プラグ

• 照明 - LED 電球、照明器具

• ビル・オートメーション - ゲートウェイ、センサー、スイッチ、位置情報サービス

• AI/ML - 予知保全、ガラス破損検出、ウェイクワード検出

Core / Memory / Acceleration

Clock Management

Energy Management

Security

Crypto Acceleration

HF Crystal

Oscillator

HF

Voltage

Regulator

DC-DC

Converter

RC Oscillator

ARM Cortex^TMM33 processor

with DSP extensions,

FPU and TrustZone

AI/ML Hardware

Accelerator

(MVP)

True Random

Number Generator

Flash Program

Memory

Fast Startup

RC Oscillator

LF

DPA

RC Oscillator

Countermeasures

Secure Debug

Authentication

Power-On

Reset

Brown-Out

Detector

LDMA

Controller

LF Crystal

Oscillator

Ultra LF RC

Oscillator

ETM

Debug Interface

RAM Memory

Secure Engine

32-bit bus

Peripheral Reflex System

Radio Subsystem

Serial

Interfaces

I/O Ports

Timers and Triggers

Analog I/F

IADC

ARM Cortex^TM

M0+ Radio

Controller

USART

EUSART

Keypad Scanner

Timer/Counter

DEMOD

IFADC

AGC

Protocol Timer

RX/TX Frontend with

Integrated 0dBm,

+10dBm, and +20dBm

PA

External

Interrupts

ACMP

Watchdog Timer

Low Energy Timer

BUFC RAM

FRC

General

Purpose I/O

System Real Time

Counter

Back-Up Real

Time Counter

VDAC

Pin Reset

Frequency Synthesizer

Temperature

Sensor

I²C

MOD

CRC

Pulse Counter

Pin Wakeup

Lowest power mode with peripheral operational:

EM0—Active

EM1—Sleep

EM2—Deep Sleep

EM3—Stop

EM4—Shutoff

silabs.com | Building a more connected world.

Rev. 1.0

EFR32MG24 ワイヤレス SoC ファミリデータシート

機能リスト

第 1 章機能リスト

EFR32MG24 主な特徴は以下のとおりです。

• 低消費電力ワイヤレス・システム・オンチップ

• MCU 周辺機器の幅広い選択

• DSP 命令と浮動小数点演算ユニットを備えた高性能 32 ビ

• AD コンバータ（IADC）

ット 78.0 MHz ARM Cortex^®-M33 により、効率的な信号処

理

• 12 ビット（1 Msps）または 16 ビット（76.9 ksps）

• 一部の OPN は高速モード（最大 2 Msps）および高精度

モード（3.8 ksps で最大 16 ビットの ENOB）に対応

• 最大 1536 kB のフラッシュ・プログラム・メモリ

• 最大 256 kB RAM のデータ・メモリ

• 2.4 GHz 無線操作

• 2 × アナログ・コンパレータ (ACMP)

• 2 x AD コンバータ（VDAC）

• AI/ML アクセラレーション用マトリックス・ベクタプロセッ

サ

• 最大 32 本の汎用 I/O ピン（出力状態保持および非同期割り

込み付き）

• 無線性能

• 8 チャネル DMA コントローラ (LDMA)

• -105.4 dBm 感度 (250 kbps O-QPSK DSSS）

• -105.7 dBm 感度（125 kbps GFSK）

• -97.6 dBm 感度（1 Mbps GFSK）

• -94.8 dBm 感度（2 Mbps GFSK）

• 最大 19.5 dBm の TX 電力

• 16 チャネル・ペリフェラル・リフレックス・システム (PRS)

• 3 x 16 ビットのタイマ/カウンタ、3 つの比較/キャプチ

ャ/PWM チャネル付き（TIMER2/3/4）

• 3 つの比較/キャプチャ/PWM チャネルを備えた 2 x 32 ビ

ットタイマ/カウンタ（TIMER0/1）

• 2 x 32 ビットのリアルタイム・カウンタ（SYSRTC/

BURTC）

• 低システム•エネルギー消費

• 4.4 mA RX 電流（1 Mbps GFSK）

• 5.1 mA RX 電流（250 kbps O-QPSK DSSS）

• 5 mA TX 電流（0 dBm 出力パワー）

• 19.1 mA TX 電流（10 dBm 出力パワー）

• 156.8 mA TX 電流（19.5 dBm 出力パワー）

• 33.4 μA/MHz（アクティブモード（EM0）で 39.0 MHz ）

• 波形生成用 24 ビット低エネルギー・タイマ（LETIMER）

• 16 ビット・パルス・カウンタ、非同期動作（PCNT）

• 2 x ウオッチドッグ・タイマ (WDOG)

• 1 x 汎用同期/非同期レシーバ/トランスミッタ（USART）、

UART/SPI/ SmartCard（ISO 7816）/IrDA/I 対応 ²S

• 2 x 拡張汎用同期/非同期レシーバ/トランスミッタ

（EUSART）、 UART/SPI/ DALI/IrDA 対応

• 1.3μA EM2 ディープ・スリープ電流（16 kB RAM 保持およ

び LFRCO からの RTCC の実行）

2 × I²C インターフェイス、SMBus 対応

•

• サポートされている変調形式

• 2 (G)FSK および完全に構成可能なシェーピング

• OQPSK DSSS

• 32 kHz スリープ水晶（LFRCO）に代わる高精度モードを備

えた低周波数 RC 発振器

• 最大 6 x 8 のマトリックス対応のキーパッドスキャナ

（KEYSCAN）

• (G)MSK

• サポートされているプロトコル

• Matter

• 単一点校正後の精度 +/-1.5°C のダイ温度センサー

• 広範な動作範囲

• OpenThread

• 1.71 V ～ 3.8 V 単一電源

• -40 °C ～ 125 °C

• Zigbee

• Bluetooth Low Energy（BLE 5.3）

• Bluetooth Mesh

• パッケージ

• QFN40 5 mm × 5 mm × 0.85 mm

• QFN48 6 mm × 6 mm × 0.85 mm

• 独自規格 2.4 GHz

• マルチプロトコル

• セキュア・ボールト

• AES128/192/256、ChaCha20-Poly1305、SHA-1,

SHA-2/256/384/512、 ECDSA+ECDH(P-192、P-256、

P-384、P-521)、Ed25519、Curve25519, J-PAKE, PBKDF2

用ハードウェア暗号化アクセラレーション

• 真の乱数発生器 (TRNG)

• ARM® TrustZone®

• セキュアブート（Root of Trust セキュアローダー）

• セキュア・デバッグのロック解除

• DPA 対策

• PUF による安全なキー管理

• 改ざん防止

• 安全な認証

silabs.com | Building a more connected world.

Rev. 1.0 | 2

EFR32MG24 Wireless SoC Family Data Sheet

Ordering Information

2. Ordering Information

Table 2.1. Ordering Information

IADC High-

Multi

Max TX

Power

Flash

(kB)

RAM

(kB)

Secure

Vault

Speed /

High-Accu-

racy

Vector

Ordering Code

GPIO Package / Pinout

Pro-

cessor

EFR32MG24B310F1536IM48-B

10 dBm

1536

1024

1536

1024

1536

1024

1536

1024

1536

1024

256

128

256

128

256

128

192

128

192

128

High

Mid

Yes

No

Yes

No

Yes

No

Yes

No

28 QFN48 / ADC

EFR32MG24B220F1536IM48-B 19.5 dBm

EFR32MG24B210F1536IM48-B 10 dBm

EFR32MG24B120F1536IM48-B 19.5 dBm

EFR32MG24B110F1536IM48-B 10 dBm

32 QFN48 / Standard

28 QFN48 / ADC

EFR32MG24B020F1536IM48-B 19.5 dBm

EFR32MG24B020F1536IM40-B 19.5 dBm

EFR32MG24B020F1024IM48-B 19.5 dBm

32 QFN48 / Standard

26 QFN40 / Standard

32 QFN48 / Standard

26 QFN40 / Standard

32 QFN48 / Standard

26 QFN40 / Standard

32 QFN48 / Standard

26 QFN40 / Standard

28 QFN48 / ADC

EFR32MG24B010F1536IM48-B

EFR32MG24B010F1536IM40-B

EFR32MG24B010F1024IM48-B

10 dBm

EFR32MG24A420F1536IM48-B 19.5 dBm

EFR32MG24A420F1536IM40-B 19.5 dBm

Mid

EFR32MG24A410F1536IM48-B

EFR32MG24A410F1536IM40-B

EFR32MG24A110F1024IM48-B

10 dBm

Mid

EFR32MG24A021F1024IM40-B 19.5 dBm

EFR32MG24A020F1536IM48-B 19.5 dBm

EFR32MG24A020F1536IM40-B 19.5 dBm

EFR32MG24A020F1024IM48-B 19.5 dBm

EFR32MG24A020F1024IM40-B 19.5 dBm

Mid

25 QFN40 / HFCLKOUT

32 QFN48 / Standard

26 QFN40 / Standard

32 QFN48 / Standard

26 QFN40 / Standard

32 QFN48 / Standard

26 QFN40 / Standard

32 QFN48 / Standard

26 QFN40 / Standard

Mid

EFR32MG24A010F1536IM48-B

EFR32MG24A010F1536IM40-B

EFR32MG24A010F1024IM48-B

EFR32MG24A010F1024IM40-B

10 dBm

Mid

silabs.com | Building a more connected world.

Rev. 1.0 | 3

EFR32MG24 Wireless SoC Family Data Sheet

Ordering Information

-

EFR32MG24B 020 F 1536 I M 48 BR

Product Family

Security

Features

Memory

Size

Temperature Grade

Package

Pins

Revision

Tape & Reel

Field

Options

Product Family

• EFR32MG24: Mighty Gecko 24 Family

Security

• A: Secure Vault Mid

• B: Secure Vault High

Features [f1][f2][f3]

• f1

• 0: Base Configuration

• 1: IADC High-Speed / High-Accuracy Available

• 2: Matrix Vector Processor (MVP) Available

• 3: IADC High-Speed / High-Accuracy and Matrix Vector Processor (MVP) Available

• 4: 256K RAM and Secure Vault – Mid

• f2

• 1: 10 dBm PA Transmit Power

• 2: 19.5 dBm PA Transmit Power

• f3

• 0: No feature enabled

• 1: High Quality HFCLKOUT Pin Available

Memory

• F: Flash

Size

• Memory Size in kBytes

Temperature Grade

• G: -40 to +85 °C

• I: -40 to +125 °C

Package

Pins

• M: QFN

• Number of Package Pins

• B: Revision B

Revision

Tape & Reel

• R: Tape & Reel (optional)

Figure 2.1. Ordering Code Key

silabs.com | Building a more connected world.

Rev. 1.0 | 4

Table of Contents

1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2.2 Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . .10

3.2.3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.5 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.6 Data Buffering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.7 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.8 RF Signal Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.3 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . .11

3.4 Keypad Scanner (KEYSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .11

3.5 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.5.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .11

3.5.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . .11

3.6 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.2 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .12

3.6.3 System Real Time Clock with Capture (SYSRTC). . . . . . . . . . . . . . . . .12

3.6.4 Back-Up Real Time Counter (BURTC) . . . . . . . . . . . . . . . . . . . .12

3.6.5 Watchdog Timer (WDOG). . . . . . . . . . . . . . . . . . . . . . . . .12

3.7 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .12

3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .12

3.7.2 Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) . . . . .12

2

3.7.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . . .13

3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .13

3.8 Secure Vault Features . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.8.1 Secure Boot with Root of Trust and Secure Loader (RTSL) . . . . . . . . . . . . .14

3.8.2 Cryptographic Accelerator. . . . . . . . . . . . . . . . . . . . . . . . .14

3.8.3 True Random Number Generator . . . . . . . . . . . . . . . . . . . . . .14

3.8.4 Secure Debug with Lock/Unlock. . . . . . . . . . . . . . . . . . . . . . .14

3.8.5 DPA Countermeasures. . . . . . . . . . . . . . . . . . . . . . . . . .14

3.8.6 Secure Key Management with PUF . . . . . . . . . . . . . . . . . . . . .15

3.8.7 Anti-Tamper . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.8.8 Secure Attestation . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9.1 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . .15

3.9.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .16

3.9.3 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .16

silabs.com | Building a more connected world.

Rev. 1.0 | 5

3.10 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.10.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .17

3.10.2 Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.10.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.10.4 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.11 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .18

3.12 Core, Memory, and Accelerators . . . . . . . . . . . . . . . . . . . . . . .19

3.12.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.12.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .19

3.12.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .19

3.12.4 Matrix Vector Processor (MVP) . . . . . . . . . . . . . . . . . . . . . .19

3.13 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.14 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .21

4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .23

4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .24

4.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.6 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.6.1 MCU current consumption using DC-DC at 3.0 V input . . . . . . . . . . . . . . .29

4.6.2 Radio current consumption at 3.0V using DCDC . . . . . . . . . . . . . . . . .32

4.6.3 MCU current consumption at 3.0 V . . . . . . . . . . . . . . . . . . . . . .34

4.6.4 Radio current consumption at 3.0V. . . . . . . . . . . . . . . . . . . . . .37

4.6.5 MCU current consumption at 1.8 V . . . . . . . . . . . . . . . . . . . . . .39

4.6.6 Radio current consumption at 1.8V. . . . . . . . . . . . . . . . . . . . . .42

4.7 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

4.8 Energy Mode Wake-up and Entry Times . . . . . . . . . . . . . . . . . . . . .45

4.9 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . .46

4.9.1 RF Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . .46

4.9.2 RF Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . .54

4.10 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.10.1 High Frequency Crystal Oscillator (HFXO) . . . . . . . . . . . . . . . . . . .60

4.10.2 Low Frequency Crystal Oscillator (LFXO) . . . . . . . . . . . . . . . . . . .61

4.10.3 High Frequency RC Oscillator (HFRCO) . . . . . . . . . . . . . . . . . . .62

4.10.4 Fast Start-Up RC Oscillator (FSRCO) . . . . . . . . . . . . . . . . . . . .63

4.10.5 Precision Low Frequency RC Oscillator (LFRCO) . . . . . . . . . . . . . . . .64

4.10.6 Ultra Low Frequency RC Oscillator (ULFRCO) . . . . . . . . . . . . . . . . .64

4.11 GPIO Pins (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.12 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . . .67

4.13 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . .73

4.14 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . . .75

silabs.com | Building a more connected world.

Rev. 1.0 | 6

4.15 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.16 Brown Out Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.16.1 DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.16.2 Low-Energy DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . .78

4.16.3 AVDD and IOVDD BODs . . . . . . . . . . . . . . . . . . . . . . . .79

4.17 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.18 USART SPI Main Timing . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.18.1 USART SPI Main Timing, Voltage Scaling = VSCALE2 . . . . . . . . . . . . . .81

4.18.2 USART SPI Main Timing, Voltage Scaling = VSCALE1 . . . . . . . . . . . . . .81

4.19 USART SPI Secondary Timing . . . . . . . . . . . . . . . . . . . . . . . .82

4.19.1 USART SPI Secondary Timing, Voltage Scaling = VSCALE2 . . . . . . . . . . . .83

4.19.2 USART SPI Secondary Timing, Voltage Scaling = VSCALE1 . . . . . . . . . . . .83

4.20 EUSART SPI Main Timing. . . . . . . . . . . . . . . . . . . . . . . . . .84

4.20.1 EUSART SPI Main Timing, Voltage Scaling = VSCALE2 . . . . . . . . . . . . . .84

4.20.2 EUSART SPI Main Timing, Voltage Scaling = VSCALE1 . . . . . . . . . . . . . .85

4.21 EUSART SPI Secondary Timing . . . . . . . . . . . . . . . . . . . . . . .86

4.21.1 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE2 . . . . . . . . . . . .86

4.21.2 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE1 . . . . . . . . . . . .87

4.21.3 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE0 . . . . . . . . . . . .87

4.22 I2C Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .88

4.22.1 I2C Standard-mode (Sm) . . . . . . . . . . . . . . . . . . . . . . . .88

4.22.2 I2C Fast-mode (Fm) . . . . . . . . . . . . . . . . . . . . . . . . . .89

4.22.3 I2C Fast-mode Plus (Fm+) . . . . . . . . . . . . . . . . . . . . . . . .90

4.23 Boot Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

4.24 Crypto Operation Timing for SE Manager API . . . . . . . . . . . . . . . . . . .92

4.25 Crypto Operation Average Current for SE Manager API. . . . . . . . . . . . . . . .94

4.26 Matrix Vector Processor (MVP) . . . . . . . . . . . . . . . . . . . . . . . .96

4.27 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .97

4.27.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

4.27.2 RF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.27.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . .102

4.27.4 IADC

4.27.5 GPIO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5. Typical Connections

. . . . . . . . . . . . . . . . . . . . . . . . . . 1.05

5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.2 Other Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.1 QFN48 / Standard Device Pinout . . . . . . . . . . . . . . . . . . . . . . . 107

6.2 QFN48 / ADC Device Pinout

. . . . . . . . . . . . . . . . . . . . . . . .109

6.3 QFN40 / Standard Device Pinout . . . . . . . . . . . . . . . . . . . . . . . 111

6.4 QFN40 / HFCLKOUT Device Pinout . . . . . . . . . . . . . . . . . . . . . . 113

6.5 Alternate Function Table. . . . . . . . . . . . . . . . . . . . . . . . . . 115

silabs.com | Building a more connected world.

Rev. 1.0 | 7

6.6 Analog Peripheral Connectivity

. . . . . . . . . . . . . . . . . . . . . . 1. 16

6.7 Digital Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . . . 117

7. QFN40 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 121

7.1 QFN40 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .121

7.2 QFN40 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .123

7.3 QFN40 Package Marking

. . . . . . . . . . . . . . . . . . . . . . . . .124

8. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 125

8.1 QFN48 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .125

8.2 QFN48 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .127

8.3 QFN48 Package Marking

. . . . . . . . . . . . . . . . . . . . . . . . .128

9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

silabs.com | Building a more connected world.

Rev. 1.0 | 8

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3. System Overview

3.1 Introduction

The EFR32 product family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited for

secure connected IoT multi-protocol devices requiring high performance and low energy consumption. This section gives a short intro-

duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG24 Reference Manual.

A block diagram of the EFR32MG24 family is shown in Figure 3.1 Detailed EFR32MG24 Block Diagram on page 9. The diagram

shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult

Ordering Information.

Radio Subsystem

Port I/O Configuration

Digital Peripherals

IOVDD

ARM Cortex^TMM0+

Radio Controller

DEMOD

IFADC

AGC

USART

EUSART

I2C

RX/TX Frontend

with Integrated PA

BUFC RAM

FRC

Port A

Drivers

RF2G4_IO

PAn

Frequency

Synthesizer

MOD

Port B

CRC

PBn

PCn

PDn

Drivers

LETIMER

DBUS

Port

Mappers

TIMER

SYSRTC

KEYSCAN

TRNG

Core and Memory

Port C

Drivers

Reset Management Unit,

Brown Out and POR

RESETn

ARM Cortex-M33 Core

with Floating Point Unit

Serial Wire and ETM

Debug / Programming

with Debug Challenge I/F

Port D

Drivers

Debug Signals

(shared w/GPIO)

Up to 1536 KB ISP Flash

Program Memory

A

H

B

A

P

B

CRYPTOACC

CRC

Up to 256 KB RAM

Trust Zone

Energy Management

PAVDD

RFVDD

IOVDD

AVDD

LDMA Controller

Analog Peripherals

Voltage

Monitor

Watchdog

Timer

Internal

Reference

Temperature

Sensor

DVDD

bypass

VREGVDD

VREGSW

DC-DC

Converter

Voltage

Regulator

Clock Management

ULFRCO

VDD

12-20 bit

ADC

DECOUPLE

FSRCO

LFRCO

LFXO

LFXTAL_I

LFXTAL_O

HFXTAL_I

HFXTAL_O

ACMP

VDAC

HFRCO

HFXO

Security

Accelerators

Crypto

Acceleration

Secure Debug

Authentication

True Random

Number Generator

DPA

Countermeasures

Matrix Vector

Processor

Secure Engine

Figure 3.1. Detailed EFR32MG24 Block Diagram

3.2 Radio

The EFR32MG24 Wireless SoC features a highly configurable radio transceiver supporting Zigbee, Bluetooth Low Energy and Blue-

tooth Mesh wireless protocols.

3.2.1 Antenna Interface

The 2.4 GHz antenna interface consists of a single-ended pin (RF2G4_IO). The external components for the antenna interface in typi-

cal applications are shown in the RF Matching Networks section.

silabs.com | Building a more connected world.

Rev. 1.0 | 9

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.2.2 Fractional-N Frequency Synthesizer

The EFR32MG24 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is

used in receive mode to generate the LO frequency for the down-conversion mixer. It is also used in transmit mode to directly generate

the modulated RF carrier.

The fractional-N architecture provides excellent phase noise performance, frequency resolution better than 100 Hz, and low energy

consumption. The synthesizer’s fast frequency settling allows for very short receiver and transmitter wake up times to reduce system

energy consumption.

3.2.3 Receiver Architecture

The EFR32MG24 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion

mixer. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC).

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-

ing flexibility with respect to known interferers at the image frequency.

The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-

tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance.

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received

frame and the dynamic RSSI measurement can be monitored throughout reception.

3.2.4 Transmitter Architecture

The EFR32MG24 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping

filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-

ing.

Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by

the EFR32MG24. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-

tween devices that otherwise lack synchronized RF channel access.

3.2.5 Packet and State Trace

The EFR32MG24 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.

It features:

• Non-intrusive trace of transmit data, receive data and state information

• Data observability on a single-pin UART data output, or on a two-pin SPI data output

• Configurable data output bitrate / baudrate

• Multiplexed transmitted data, received data and state / meta information in a single serial data stream

3.2.6 Data Buffering

The EFR32MG24 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.

3.2.7 Radio Controller (RAC)

The Radio Controller controls the top level state of the radio subsystem in the EFR32MG24. It performs the following tasks:

• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry

• Run-time calibration of receiver, transmitter and frequency synthesizer

• Detailed frame transmission timing, including optional LBT or CSMA-CA

silabs.com | Building a more connected world.

Rev. 1.0 | 10

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.2.8 RF Signal Identifier

When an IoT radio is placed next to a high duty-cycle co-located Wi-Fi radio transmission, IoT radios are blocked from receiving weak

signals. The RF Signal Identifier feature available on EFR32MG24 devices enables the IoT radio to detect partial 802.15.4 or BLE/BT

Mesh packets. When a partial packet is detected, the IoT radio can communicate this information to the corresponding Wi-Fi device

(through serial interface or GPIO asserts), which can consequently halt transmission while the IoT radio waits for a packet retry to be

received. This helps provide a higher success rate of receiving packets from other devices on the network, when co-located with an

interfering Wi-Fi radio.

3.3 General Purpose Input/Output (GPIO)

EFR32MG24 has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or

input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO

pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to

several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-

als. The GPIO subsystem supports asynchronous external pin interrupts.

All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be

used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon

which internal peripherals could once again drive those pads.

A few GPIOs also have EM4 wake functionality. These pins are listed in the Alternate Function Table.

3.4 Keypad Scanner (KEYSCAN)

A low-energy keypad scanner (KEYSCAN) is included, which can scan up to a 6 x 8 matrix of keyboard switches. The KEYSCAN pe-

ripheral contains logic for debounce and settling time, allowing it to scan through the switch matrix autonomously in EM0 and EM1, and

interrupt the processor when a key press is detected. A wake-on-keypress feature is also supported, allowing for the detection of any

key press down to EM3.

3.5 Clocking

3.5.1 Clock Management Unit (CMU)

The Clock Management Unit controls oscillators and clocks in the EFR32MG24. Individual enabling and disabling of clocks to all periph-

eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility

allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and

oscillators.

3.5.2 Internal and External Oscillators

The EFR32MG24 supports two crystal oscillators and fully integrates four RC oscillators, listed below.

• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-

ence for the MCU. The HFXO provides excellent RF clocking performance using a 39.0 MHz crystal. The HFXO can also support an

external clock source such as a TCXO for applications that require an extremely accurate clock frequency over temperature.

• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.

• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The

HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 78 MHz.

• An integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz

• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation without an external crystal. Precision mode

enables periodic recalibration against the 39.0 MHz HFXO crystal to improve accuracy to +/- 500 ppm, suitable for BLE sleep inter-

val timing.

• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-

sumption in low energy modes.

silabs.com | Building a more connected world.

Rev. 1.0 | 11

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.6 Counters/Timers and PWM

3.6.1 Timer/Counter (TIMER)

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the

Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each

channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In

compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER

supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the

compare registers. In addition some timers offer dead-time insertion.

See 3.14 Configuration Summary for information on the feature set of each timer.

3.6.2 Low Energy Timer (LETIMER)

The unique LETIMER is a 24-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-

forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to

start counting on compare matches from other peripherals such as the Real Time Clock.

3.6.3 System Real Time Clock with Capture (SYSRTC)

The System Real Time Clock (SYSRTC) is a 32-bit counter providing timekeeping down to EM3. The SYSRTC can be clocked by any

of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.

3.6.4 Back-Up Real Time Counter (BURTC)

The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC

can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user-defined inter-

vals.

3.6.5 Watchdog Timer (WDOG)

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can

also monitor autonomous systems driven by the Peripheral Reflex System (PRS).

3.7 Communications and Other Digital Peripherals

3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-

porting:

• ISO7816 SmartCards

• IrDA

I²S

•

3.7.2 Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)

The Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter supports full duplex asynchronous UART communication

with hardware flow control, RS-485, and IrDA support. The EUSART also supports high-speed SPI. In EM0 and EM1 the EUSART pro-

vides a high-speed, buffered communication interface.

When routed to GPIO ports A or B, the EUSART0 may also be used in a low-energy mode and operate in EM2. A 32.768 kHz clock

source allows full duplex UART communication up to 9600 baud. EUSART0 can also act as a SPI secondary device in EM2 and EM3,

and wake the system when data is received from an external bus controller.

silabs.com | Building a more connected world.

Rev. 1.0 | 12

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.7.3 Inter-Integrated Circuit Interface (I²C)

The I²C module provides an interface between the MCU and a serial I²C bus. It is capable of acting as a main or secondary interface

and supports multi-drop buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from

10 kbit/s up to 1 Mbit/s. Bus arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The

interface provided to software by the I²C module allows precise timing control of the transmission process and highly automated trans-

fers. Automatic recognition of addresses is provided in active and low energy modes. Note that not all instances of I²C are available in

all energy modes.

3.7.4 Peripheral Reflex System (PRS)

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.

Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-

erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)

can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving pow-

er.

3.8 Secure Vault Features

A dedicated hardware secure engine containing its own CPU enables the Secure Vault functions. It isolates cryptographic functions and

data from the host Cortex-M33 core, and provides several additional security features. The EFR32MG24 family includes devices with

Secure Vault High and Secure Vault Mid capabilities, which are summarized in the table below.

Table 3.1. Secure Vault Features

Feature

Secure Vault Mid

Secure Vault High

True Random Number Generator (TRNG) Yes

Yes

Secure Boot with Root of Trust and Secure Yes

Loader (RTSL)

Secure Debug with Lock/Unlock

DPA Countermeasures

Anti-Tamper

Yes

Secure Attestation

Yes

Secure Key Management

Symmetric Encryption

Yes

• AES 128 / 192 / 256 bit

• ECB, CTR, CBC, CFB, CCM, GCM,

CBC-MAC, and GMAC

• ECB, CTR, CBC, CFB, CCM, GCM,

CBC-MAC, and GMAC

• ChaCha20

Public Key Encryption - ECDSA / ECDH /

EdDSA

• p192 and p256

• p192, p256, p384 and p521

• Curve25519 (ECDH)

• Ed25519 (EdDSA)

Key Derivation

Hashes

• ECJ-PAKE p192 and p256

• ECJ-PAKE p192, p256, p384, and p521

• PBKDF2

• HKDF

• SHA-1

• SHA-2/256

• SHA-2 256, 384, and 512

• Poly1305

silabs.com | Building a more connected world.

Rev. 1.0 | 13

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.8.1 Secure Boot with Root of Trust and Secure Loader (RTSL)

The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).

It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed, and protects Over The Air updates.

For more information about this feature, see AN1218: Series 2 Secure Boot with RTSL.

3.8.2 Cryptographic Accelerator

The Cryptographic Accelerator is an autonomous hardware accelerator with Differential Power Analysis (DPA) countermeasures to pro-

tect keys.

It supports AES encryption and decryption with 128/192/256-bit keys, ChaCha20 encryption, and Elliptic Curve Cryptography (ECC) to

support public key operations, and hashes.

Supported block cipher modes of operation for AES include:

• ECB (Electronic Code Book)

• CTR (Counter Mode)

• CBC (Cipher Block Chaining)

• CFB (Cipher Feedback)

• GCM (Galois Counter Mode)

• CCM (Counter with CBC-MAC)

• CBC-MAC (Cipher Block Chaining Message Authentication Code)

• GMAC (Galois Message Authentication Code)

The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and

Technology) recommended curves including P-192, P-256, P-384, and P-521 for ECDH (Elliptic Curve Diffie-Hellman) key derivation,

and ECDSA (Elliptic Curve Digital Signature Algorithm) sign and verify operations. Also supported is the non-NIST Curve25519 for

ECDH and Ed25519 for EdDSA (Edwards-curve Digital Signature Algorithm) sign and verify operations.

Secure Vault also supports ECJ-PAKE (Elliptic Curve variant of Password Authenticated Key Exchange by Juggling) and PBKDF2

(Password-Based Key Derivation Function 2).

Supported hashes include SHA-1, SHA-2/256/384/512 and Poly1305.

This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.

3.8.3 True Random Number Generator

The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal

energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online

health tests required for NIST SP800-90C.

The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.

3.8.4 Secure Debug with Lock/Unlock

For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.

In addition, Secure Vault High also provides a secure debug unlock function that allows authenticated access based on public key cryp-

tography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive end-

user data.

For more information about this feature, see AN1190: Series 2 Secure Debug.

3.8.5 DPA Countermeasures

The AES and ECC accelerators have Differential Power Analysis (DPA) countermeasures support. This makes it very expensive from a

time and effort standpoint to use DPA to recover secret keys.

silabs.com | Building a more connected world.

Rev. 1.0 | 14

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.8.6 Secure Key Management with PUF

Key material in Secure Vault High products is protected by "key wrapping" with a standardized symmetric encryption mechanism. This

method has the advantage of protecting a virtually unlimited number of keys, limited only by the storage that is accessible by the

Cortex-M33, which includes off-chip storage as well. The symmetric key used for this wrapping and unwrapping must be highly secure

because it can expose all other key materials in the system. The Secure Vault Key Management system uses a Physically Unclonable

Function (PUF) to generate a persistent device-unique seed key on power up to dynamically generate this critical wrapping/unwrapping

key which is only visible to the AES encryption engine and is not retained when the device loses power.

3.8.7 Anti-Tamper

Secure Vault High devices provide internal tamper protection which monitors parameters such as voltage, temperature, and electro-

magnetic pulses as well as detecting tamper of the security sub-system itself. Additionally, 8 external configurable tamper pins support

external tamper sources, such as enclosure tamper switches.

For each tamper event, the user is able to select the severity of the tamper response ranging from an interrupt, to a reset, to destroying

the PUF reconstruction data which will make all protected key materials un-recoverable and effectively render the device inoperable.

The tamper system also has an internal resettable event counter with programmable trigger threshold and refresh periods to mitigate

false positive tamper events.

For more information about this feature, see AN1247: Anti-Tamper Protection Configuration and Use.

3.8.8 Secure Attestation

Secure Vault High products support Secure Attestation, which begins with a secure identity that is created during the Silicon Labs man-

ufacturing process. During device production, each device generates its own public/private keypair and securely stores the wrapped

private key into immutable OTP memory and this key never leaves the device. The corresponding public key is extracted from the de-

vice and inserted into a binary DER-encoded X.509 device certificate, which is signed into a Silicon Labs CA chain and then program-

med back into the chip into an immutable OTP memory.

The secure identity can be used to authenticate the chip at any time in the life of the product. The production certification chain can be

requested remotely from the product. This certification chain can be used to verify that the device was authentically produced by Silicon

Labs. The device unique public key is also bound to the device certificate in the certification chain. A challenge can be sent to the chip

at any point in time to be signed by the device private key. The public key in the device certificate can then be used to verify the chal-

lenge response, proving that the device has access to the securely-stored private key, which prevents counterfeit products or imperso-

nation attacks.

For more information about this feature, see AN1268: Authenticating Silicon Labs Devices Using Device Certificates.

3.9 Analog

3.9.1 Analog to Digital Converter (IADC)

The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. Flexible controls allow fine-

tuned performance and speed to meet the needs of a wide variety of applications. Hardware oversampling reduces system-level noise

over multiple front-end samples. The IADC includes integrated voltage reference options. Inputs are selectable from a wide range of

sources, including pins configurable as either single-ended or differential.

The IADC supports three operational modes:

• Normal Mode (all devices): Flexible speed and performance, 12-16 bits output resolution

• 11.7 bits ENOB performance at 1 Msps (OSR = 2)

• 14.3 bits ENOB performance at 76.9 ksps (OSR = 32)

• High Speed Mode (select devices): Doubles output speed of Normal mode with similar performance, 12-16 bits output resolution

• 11.7 bits ENOB performance at 2 Msps (OSR = 2)

• 14.3 bits ENOB performance at 153.8 ksps (OSR = 32)

• High Accuracy Mode (select devices): Optimized for low-rate, high performance applications, with 20 bit output resolution

• 16 bits ENOB performance at 3.8 ksps (OSR = 256)

• 15 bits ENOB performance at 15.3 ksps (OSR = 64)

silabs.com | Building a more connected world.

Rev. 1.0 | 15

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.9.2 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the

programmable threshold.

3.9.3 Digital to Analog Converter (VDAC)

The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500

ksps, 12-bit converter. The VDAC may be used for a number of different applications such as sensor interfaces or sound output. The

VDAC can generate high-resolution analog signals while the MCU is operating at low frequencies and with low total power consump-

tion. Using DMA and a timer, the VDAC can be used to generate waveforms without any CPU intervention. The VDAC is available in all

energy modes down to and including EM3.

silabs.com | Building a more connected world.

Rev. 1.0 | 16

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.10 Power

The EFR32MG24 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only

a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator

can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-

tor.

The EFR32MG24 device family includes support for internal supply voltage scaling, as well as two different power domains groups for

peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.

3.10.1 Energy Management Unit (EMU)

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and

features are available and the amount of current the device consumes. The EMU can also be used to implement system-wide voltage

scaling and turn off the power to unused RAM blocks to optimize the energy consumption in the target application. The DC-DC regula-

tor operation is tightly integrated with the EMU.

3.10.2 Voltage Scaling

The EFR32MG24 supports supply voltage scaling for the LDO powering DECOUPLE, with independent selections for EM0 / EM1 and

EM2 / EM3. Voltage scaling helps to optimize the energy efficiency of the system by operating at lower voltages when possible. The

EM0 / EM1 voltage scaling level defaults to VSCALE2, which allows the core to operate in active mode at full speed. The intermediate

level, VSCALE1, allows operation in EM0 and EM1 at up to 40 MHz. The lowest level, VSCALE0, can be used to conserve power fur-

ther in EM2 and EM3. The EMU will automatically switch the target voltage scaling level when transitioning between energy modes.

3.10.3 DC-DC Converter

The DC-DC buck converter covers a wide range of load currents, providing high efficiency in energy modes EM0, EM1, EM2 and EM3.

RF noise mitigation allows operation of the DC-DC converter without significantly degrading sensitivity of radio components. An on-chip

supply-monitor signals when the supply voltage is low to allow bypass of the regulator via programmable software interrupt. It employs

soft switching at boot and DCDC regulating-to-bypass transitions to limit the max supply slew-rate and mitigate inrush current.

silabs.com | Building a more connected world.

Rev. 1.0 | 17

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.10.4 Power Domains

Peripherals may exist on one of several independent power domains which are powered down to minimize supply current when not in

use. Power domains are managed automatically by the EMU.

The lowest-energy power domain is the "high-voltage" power domain (PDHV), which supports extremely low-energy infrastructure and

peripherals. Circuits powered from PDHV are always on and available in all energy modes down to EM4.

The next power domain is the low power domain (PD0), which is further divided to power subsets of peripherals. All PD0 power do-

mains are shut down in EM4. Circuits powered from PD0 power domains may be available in EM0, EM1, EM2, and EM3.

Low power domain A (PD0A) is the base power domain for EM2 and EM3 and will always remain on in EM0-EM3. It powers the most

commonly-used EM2 and EM3-capable peripherals and infrastructure required to operate in EM2 and EM3. Auxiliary PD0 power do-

mains (PD0B, PD0C, PD0D, PD0E) power additional EM2 and EM3-capable peripherals on demand. If any peripherals on one of the

auxiliary power domains is enabled, that power domain will be active in EM2 and EM3. Otherwise, the auxiliary PD0 power domains will

be shut down to reduce current.

Note: Power domain PD0E is also turned on when peripherals on PD0B, PD0C, or PD0D are used.

The active power domain (PD1) powers the rest of the device circuitry, including the CPU core and EM0 / EM1 peripherals. PD1 is

always powered on in EM0 and EM1. PD1 is always shut down in EM2, EM3, and EM4.

Table 3.2 Peripheral Power Subdomains on page 18 shows the peripherals on the PDHV and PD0x domains. Any peripheral not lis-

ted is on PD1.

Table 3.2. Peripheral Power Subdomains

Always On in EM2/EM3

Selectively On in EM2/3

PDHV¹

PD0B²

PD0C²

PD0D²

PD0A

PD0E

LFRCO (Non-preci- SYSRTC

sion Mode)

LETIMER0

LFRCO (Precision

Calibration Mode)

DEBUG

GPIO

LFXO

FSRCO

IADC0

HFRCOEM23

HFXO

WDOG0/1

EUSART0

I2C0

KEYSCAN

PRS

BURTC

ULFRCO

PCNT0

ACMP0/1

VDAC0/1

Note:

1. Peripherals on PDHV are also available in EM4.

2. If any of PD0B, PD0C, or PD0D are enabled, PD0E will also be automatically enabled.

3.11 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the EFR32MG24. A wide range of reset sources are available, including several power

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

silabs.com | Building a more connected world.

Rev. 1.0 | 18

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.12 Core, Memory, and Accelerators

3.12.1 Processor Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz

• ARM TrustZone security technology

• Embedded Trace Macrocell (ETM) for real-time trace and debug

• Up to 1536 kB flash program memory

• Up to 256 kB RAM data memory

• Configuration and event handling of all modules

• 2-pin Serial-Wire debug interface

3.12.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable

from both the Cortex-M33 and LDMA. In addition to the main flash array where Program code is normally written the MSC also provides

an Information block where additional information such as special user information or flash-lock bits are stored. There is also a read-

only page in the information block containing system and device calibration data. Read and write operations are supported in energy

modes EM0 Active and EM1 Sleep.

3.12.3 Linked Direct Memory Access Controller (LDMA)

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This

reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-

phisticated operations to be implemented.

3.12.4 Matrix Vector Processor (MVP)

The Matrix Vector Processor (MVP) is designed to offload the major computationally intensive floating point operations, particularly ma-

trixed complex floating point multiplications and additions. The MVP supports the acceleration of the key Angle-of-Arrival (AoA) MUSIC

(MUltiple SIgnal Classification) algorithm computations, as well as other heavily floating-point computational problems such as Machine

Learning (ML) or linear algebra.

silabs.com | Building a more connected world.

Rev. 1.0 | 19

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.13 Memory Map

The EFR32MG24 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

Figure 3.2. EFR32MG24 Memory Map — Core Peripherals and Code Space

silabs.com | Building a more connected world.

Rev. 1.0 | 20

EFR32MG24 Wireless SoC Family Data Sheet

System Overview

3.14 Configuration Summary

The features of the EFR32MG24 are a subset of the feature set described in the device reference manual. The table below describes

device specific implementation of the features. Remaining modules support full configuration. Refer to the Energy Modes table in the

Reference Manual EMU Chapter for a more comprehensive list of energy mode support for all device peripherals.

Table 3.3. Configuration Summary

Module

Lowest Energy Mode

Configuration

I2C0

EM1 - Full functionality

EM2/3¹- Functionality limited to receive address recog-

nition

I2C1

EM1 - Full functionality

EM2/3¹

LETIMER0

24-bit, 2-channels

TIMER0

TIMER1

TIMER2

TIMER3

TIMER4

EUSART0

EM1

32-bit, 3-channels, +DTI

16-bit, 3-channels, +DTI

UART, SPI, IrDA, DALI

EM1

EM1 - Full high-speed operation, all modes

EM2¹- Low-energy UART operation, 9600 Baud

EM2/3¹- Low-energy SPI secondary receiver

EUSART1

USART0

Note:

EM1

UART, SPI, IrDA, DALI

UART, SPI, IrDA, I2S, SmartCard

1. EM2 and EM3 operation is only supported for digital peripheral I/O on Port A and Port B. All GPIO ports support digital peripheral

operation in EM0 and EM1.

silabs.com | Building a more connected world.

Rev. 1.0 | 21

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4. Electrical Specifications

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T_A=25 °C and all supplies at 3.0 V, by production test and/or technology characterization.

• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.

• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,

unless stated otherwise.

Due to on-chip circuitry (e.g., diodes), some EFR32MG24 power supply pins have a dependent relationship with one or more other

power supply pins. These internal relationships between the external voltages applied to the various EFR32MG24 supply pins are de-

fined below. Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD and DVDD

• In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the

buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD)

• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD)

• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered

with power applied to these supplies.

• DVDD ≥ DECOUPLE

• PAVDD ≥ RFVDD

silabs.com | Building a more connected world.

Rev. 1.0 | 22

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.2 Absolute Maximum Ratings

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of

the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter

Symbol

T_STG

Test Condition

Min

-50

Typ

—

Max

+150

3.8

Unit

°C

Storage temperature range

Voltage on any supply pin¹

Junction temperature

V_DDMAX

-0.3

—

V

T_JMAX

-I grade

—

+125

1.0

°C

Voltage ramp rate on any

supply pin

V_DDRAMPMAX

V / µs

Voltage on HFXO pins

V_HFXOPIN

-0.3

—

1.2

V

DC voltage on any GPIO pin V_DIGPIN

V_IOVDD

0.3

+

DC voltage on RESETn pin²

V_RESETn

V_MAX2G4

-0.3

—

3.8

1.2

V

DC voltage on RF pin

RF2G4_IO

Total current into VDD power I_VDDMAX

lines

Source

Sink

—

200

mA

Total current into VSS

ground lines

I_VSSMAX

Current per I/O pin

Current for all I/O pins

Note:

I_IOMAX

Sink

—

50

mA

Source

Sink

I_IOALLMAX

200

Source

1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-

tions for more details.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at

DVDD.

silabs.com | Building a more connected world.

Rev. 1.0 | 23

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.3 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

-I temperature grade ¹

Operating ambient tempera- T_A

ture range

-40

—

+125

° C

DVDD supply voltage

V_DVDD

EM0/1

1.71

3.0

3.8

V

EM2/3/4²

AVDDBODEN=0³

IOVDDxBODEN=0³

AVDD supply voltage

V_AVDD

1.71

3.0

3.8

V

IOVDDx operating supply

voltage (All IOVDD pins)

V_IOVDDx

RFVDD operating supply

voltage

V_RFVDD

1.71

2.2

3.0

V_PAVDD

V

DC-DC in regulation⁴

VREGVDD operating supply V_VREGVDD

voltage

3.8

DC-DC in bypass 60 mA load

1.8

3.0

3.8

V

DC-DC not in use. DVDD exter-

nally shorted to VREGVDD

1.71

PAVDD operating supply

voltage

V_PAVDD

1.71

1.0

3.0

—

3.8

V

DECOUPLE output capaci-

tor⁵

C_DECOUPLE

1.0 µF ± 10% X8L capacitor used

for performance characterization.

2.75

µF

HCLK and SYSCLK frequen- f_HCLK

cy

VSCALE2, MODE = WS1

VSCALE2, MODE = WS0

VSCALE2 or VSCALE1

VSCALE2

—

78

40

78

40

78

40

—

MHz

PCLK frequency

f_PCLK

—

EM01 Group A clock fre-

quency

f_EM01GRPACLK

—

VSCALE1

—

EM01 Group C clock fre-

quency

f_EM01GRPCCLK

VSCALE2

—

VSCALE1

—

Radio HCLK frequency⁶

External Clock Input

f_RHCLK

VSCALE2 or VSCALE1

39.0

f_CLKIN

VSCALE2 or VSCALE1

—

40

MHz

DPLL Reference Clock

f_DPLLREFCLK

silabs.com | Building a more connected world.

Rev. 1.0 | 24

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. The device may operate continuously at the maximum allowable ambient T_Arating as long as the absolute maximum T_JMAXis not

exceeded. For an application with significant power dissipation, the allowable T_Amay be lower than the maximum T_Arating. T_A=

T_JMAX- (THETA_JAx PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for

T_JMAXand THETA_JA

.

2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.

3. The AVDD and IOVDD enable bits are in the EMU_BOD3SENSE register. These BODs are disabled on reset.

4. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-

tions for more details.

5. Murata GCM21BL81C105KA58L used for performance characterization. Actual capacitor values can be significantly de-rated

from their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The

minimum capacitance counting all error sources should be no less than 0.6 µF.

6. The recommended radio crystal frequency for the 2.4GHz radio is 39 MHz. The minimum and maximum RHCLK frequency in this

table represent the design timing limits, which are much wider than the typical crystal tolerance.

silabs.com | Building a more connected world.

Rev. 1.0 | 25

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.4 DC-DC Converter

Test conditions: L_DCDC= 2.2 µH (Murata DFE2HCAH2R2MJ0), C_DCDC= 4.7 µF (TDK CGA5L3X8R1C475K160AB), V_VREGVDD= 3.0 V,

V_OUT= 1.8 V, IPKVAL in EM0/1 modes is set to 150 mA, and in EM2/3 modes is set to 90 mA, unless otherwise indicated.

Table 4.3. DC-DC Converter

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input voltage range at

VREGVDD pin

V_VREGVDD

DCDC in regulation, I_LOAD= I_LOAD

MAX¹, EM0/EM1 mode

2.2

—

3.8

V

DCDC in regulation, I_LOAD= 5

1.8

—

3.8

V

mA, EM0/EM1 or EM2/EM3 mode

Bypass Mode, I_LOAD≤ 60 mA

Bypass Mode, I_LOAD≤ 120 mA

1.8

1.9

—

3.8

—

V

Regulated output voltage

Regulation DC accuracy

V_OUT

1.8

—

V

ACC_DC

V_VREGVDD≥ 2.2 V, Steady state in

EM0/EM1 mode or EM2/EM3

mode

-2.5

4.0

%

Regulation total accuracy

ACC_TOT

All error sources (including DC er-

rors, overshoot, undershoot)

-5

—

7

%

Steady-state output ripple

DC line regulation

V_R

I_LOAD= 20 mA in EM0/EM1 mode

—

12

—

mVpp

mV/V

V_REG

I_LOAD= I_LOADMAX in EM0/EM1

mode, V_VREGVDD≥ 2.2 V

-2.6

Efficiency

EFF

Load current between 100 µA and

60 mA in EM0/EM1 mode

—

90

89

—

60

%

Load current between 10 µA and

5 mA in EM2/EM3 mode

DC load regulation

Output load current

I_REG

Load current between 100 µA and

I_LOADMAX in EM0/EM1 mode

-0.08

—

mV/mA

mA

I_LOAD

EM0/EM1 mode, DCDC in regula-

tion, DCDC_EM01CTRL0.IPKVAL

= 9, Radio not transmitting

EM0/EM1 mode, DCDC in regula-

tion, Radio in receive mode

—

36

mA

EM0/EM1 mode, DCDC in regula-

tion, Radio transmitting¹

120

EM2/EM3 mode, DCDC in regula-

tion

—

5

mA

µF

Bypass mode, 1.8 V ≤ V_VREGVDD

≤ 3.8 V

60

Bypass mode, 1.9 V ≤ V_VREGVDD

≤ 3.8 V

—

120

10

Nominal output capacitor

C_DCDC

4.7 µF ± 10% X7R capacitor used

for performance characterization²

4.7

Nominal inductor

L_DCDC

C_IN

± 20% tolerance

—

2.2

—

µH

µF

Nominal input capacitor

C_DCDC

silabs.com | Building a more connected world.

Rev. 1.0 | 26

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Resistance in bypass mode R_BYP

Bypass switch from VREGVDD to

DVDD, V_VREGVDD= 1.8 V

—

0.45

0.69

Ω

Powertrain PFET switch from

VREGVDD to VREGSW,

V_VREGVDD= 1.8 V

—

0.6

0.9

Ω

Supply monitor threshold

programming range

V_{CMP_RNG}

Programmable in 0.1 V steps

Supply falling edge trip point

2

—

4

2.3

5

V

%

Supply monitor threshold ac- V_{CMP_ACC}

curacy

-5

—

Supply monitor threshold

hysteresis

V_{CMP_HYST}

Positive hysteresis on the supply

rising edge referred to the falling

edge trip point

—

Supply monitor response

time

t_{CMP_DELAY}

Supply falling edge at -100 mV /

µs

—

0.6

—

µs

Note:

1. During radio transmit operations, the RAIL library will place the DCDC into a mode that increases the maximum load current, to

support higher TX output power supplied from the DCDC converter.

2. Actual capacitor values can be significantly de-rated from their specified nominal value by the rated tolerance, as well as the ap-

plication's AC voltage, DC bias, and temperature. The minimum capacitance counting all error sources should be no less than 3.6

µF.

silabs.com | Building a more connected world.

Rev. 1.0 | 27

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.5 Thermal Characteristics

Table 4.4. Thermal Characteristics

Package

Board

Parameter

Symbol Test Condition

Θ_JAStill Air

Value

Unit

40QFN

(5x5mm)

JEDEC - High

Thermal Cond.

(2s2p)¹

Thermal Resistance, Junction

to Ambient

29.2

°C/W

Thermal Resistance, Junction

to Board

Θ_JB

Ѱ_JT

Ѱ_JB

Θ_JC

15.2

0.3

°C/W

Thermal Resistance, Junction

to Top Center

Thermal Resistance, Junction

to Board

11.2

24.6

No Board

Thermal Resistance, Junction

to Case

Temperature controlled heat sink on

top of package, all other sides of

package insulated to prevent heat

flow.

48QFN

(6x6mm)

JEDEC - High

Thermal Cond.

Thermal Resistance, Junction

to Ambient

Θ_JA

Θ_JB

Ѱ_JT

Ѱ_JB

Θ_JC

Still Air

27.7

14.6

0.69

11.85

23.0

°C/W

(2s2p)¹

Thermal Resistance, Junction

to Board

Thermal Resistance, Junction

to Top Center

Thermal Resistance, Junction

to Board

No Board

Thermal Resistance, Junction

to Case

Temperature controlled heat sink on

top of package, all other sides of

package insulated to prevent heat

flow.

Note:

1. Based on 4 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 9 Via to top inter-

nal plane of PCB.

silabs.com | Building a more connected world.

Rev. 1.0 | 28

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.6 Current Consumption

4.6.1 MCU current consumption using DC-DC at 3.0 V input

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.0 V. DVDD = RFVDD = PAVDD = 1.8 V from DC-

DC. Voltage scaling level = VSCALE1. T_A= 25 °C. Minimum and maximum values in this table represent the worst conditions across

process variation at T_A= 25 °C.

Table 4.5. MCU current consumption using DC-DC at 3.0 V input

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM0 I_ACTIVE

mode with all peripherals dis-

abled

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running Prime from flash,

VSCALE2

—

33.3

—

µA/MHz

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running while loop from flash,

VSCALE2

—

32.8

49.1

—

µA/MHz

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running CoreMark loop from flash,

VSCALE2

39 MHz crystal, CPU running

Prime from flash

—

33.9

33.4

49.4

28.1

31.0

37.6

281.8

22.6

—

µA/MHz

39 MHz crystal, CPU running

while loop from flash

39 MHz crystal, CPU running

CoreMark loop from flash

38 MHz HFRCO, CPU running

while loop from flash

26 MHz HFRCO, CPU running

while loop from flash

16 MHz HFRCO, CPU running

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

Current consumption in EM1 I_EM1

mode with all peripherals dis-

abled

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal,

VSCALE2

39 MHz crystal

38 MHz HFRCO

26 MHz HFRCO

16 MHz HFRCO

1 MHz HFRCO

—

24.4

19.0

22.0

28.5

272.1

—

µA/MHz

silabs.com | Building a more connected world.

Rev. 1.0 | 29

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM2 I_{EM2_VS}

mode, VSCALE0

256 kB RAM and full Radio RAM

retention, RTC running from

LFXO¹

—

2.9

—

µA

256 kB RAM and full Radio RAM

retention, RTC running from

—

2.9

1.3

1.9

2.7

1.1

—

µA

LFRCO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFXO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFRCO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFRCO in precision mode¹

Current consumption in EM3 I_{EM3_VS}

mode, VSCALE0

256 kB RAM and full Radio RAM

retention, RTC running from

ULFRCO¹

16 kB RAM and full Radio RAM

retention, RTC running from

ULFRCO¹

Change in current consump- I_{EM23_CPUCACHE}

tion if CPU cached unre-

tained in EM2 or EM3

—

-0.06

-0.01

—

µA

Change in current consump- I_{EM23_STATERET}

tion if EM0/1 peripheral

states unretained in EM2 or

EM3

Change in current consump- I_{EM23_RAM}

tion for retained RAM bank in

EM2 or EM3

Per 16 kB RAM bank

—

0.11

0.93

—

µA

Additional current in EM2 or I_{PD0B_VS}

EM3 when any peripheral in

PD0B is enabled²

Additional current in EM2 or I_{PD0C_VS}

EM3 when any peripheral in

—

0.26

1.1

—

µA

PD0C is enabled²

Additional current in EM2 or I_{PD0D_VS}

EM3 when any peripheral in

PD0D is enabled²

Additional current in EM2 or I_{PD0E_VS}

EM3 when any peripheral in

PD0E is enabled²

0.09

Current consumption in EM4 I_EM4

mode

No BURTC, no LF oscillator

BURTC with LFXO

—

0.25

0.64

—

µA

silabs.com | Building a more connected world.

Rev. 1.0 | 30

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. CPU cache retained, EM0/1 peripheral states retained

2. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.10.4 Power

Domains for a list of the peripherals in each power domain. Note that if the PD0B, PD0C, or PD0D domains are enabled, PD0E

will also automatically be enabled.

silabs.com | Building a more connected world.

Rev. 1.0 | 31

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.6.2 Radio current consumption at 3.0V using DCDC

RF current consumption measured with MCU in EM1, HCLK = 39.0 MHz, and all MCU peripherals disabled. Unless otherwise indica-

ted, typical conditions are: VREGVDD = IOVDD = 3.0 V. AVDD = DVDD = RFVDD = PAVDD = 1.8 V powered from DCDC. T_A= 25 °C.

Minimum and maximum values in this table represent the worst conditions across process variation at T_A= 25 °C.

Table 4.6. Radio current consumption at 3.0V using DCDC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

System current consumption I_{RX_ACTIVE}

in receive mode, active pack-

et reception

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

—

4.6

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

4.9

5.2

4.7

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

5

—

mA

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

5.2

4.4

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

4.7

4.9

5.1

—

mA

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

5.4

5.6

5.1

—

mA

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

802.15.4 receiving frame, f = 2.4

GHz, VSCALE1, EM1P (Radio

clocks only)

802.15.4 receiving frame, f = 2.4

GHz, VSCALE1

—

5.4

5.7

—

mA

802.15.4 receiving frame, f = 2.4

GHz, VSCALE2

silabs.com | Building a more connected world.

Rev. 1.0 | 32

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

System current consumption I_{RX_LISTEN}

in receive mode, listening for

packet

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

—

4.7

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

4.9

5.2

4.7

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

5

—

mA

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

5.2

4.3

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

4.6

4.9

5.1

—

mA

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

5.4

5.7

5

—

mA

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

802.15.4, f = 2.4 GHz, VSCALE1,

EM1P (Radio clocks only)

802.15.4, f = 2.4 GHz, VSCALE1

802.15.4, f = 2.4 GHz, VSCALE2

—

5.3

5.6

5

—

mA

System current consumption I_TX

in transmit mode

f = 2.4 GHz, CW, 0 dBm PA, 0

dBm output power, VSCALE1

f = 2.4 GHz, CW, 10 dBm PA, 10

dBm output power, VSCALE1

—

19.1

—

mA

f = 2.4 GHz, CW, 20 dBm PA,

19.5 dBm output power,

VSCALE1, VREGVDD = PAVDD

= 3.3 V

156.8

f = 2.4 GHz, CW, 0 dBm PA, 0

dBm output power, VSCALE2

—

5.2

19.2

157.2

—

mA

f = 2.4 GHz, CW, 10 dBm PA, 10

dBm output power, VSCALE2

f = 2.4 GHz, CW, 20 dBm PA,

19.5 dBm output power,

VSCALE2, VREGVDD = PAVDD

= 3.3 V

silabs.com | Building a more connected world.

Rev. 1.0 | 33

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.6.3 MCU current consumption at 3.0 V

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 3.0 V. DC-DC not used. Voltage

scaling level = VSCALE1. T_A= 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-

tion at T_A= 25 °C.

Table 4.7. MCU current consumption at 3.0 V

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM0 I_ACTIVE

mode with all peripherals dis-

abled

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running Prime from flash,

VSCALE2

—

47.3

—

µA/MHz

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running while loop from flash,

VSCALE2

—

46.1

69.5

—

µA/MHz

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running CoreMark loop from flash,

VSCALE2

39 MHz crystal, CPU running

Prime from flash

—

48.4

47.1

69.6

39.4

43.6

52.7

392.4

32.2

—

µA/MHz

39 MHz crystal, CPU running

while loop from flash

39 MHz crystal, CPU running

CoreMark loop from flash

—

38 MHz HFRCO, CPU running

while loop from flash

62

26 MHz HFRCO, CPU running

while loop from flash

—

16 MHz HFRCO, CPU running

while loop from flash

—

1 MHz HFRCO, CPU running

while loop from flash

1170

—

Current consumption in EM1 I_EM1

mode with all peripherals dis-

abled

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal,

VSCALE2

39 MHz crystal

38 MHz HFRCO

26 MHz HFRCO

16 MHz HFRCO

1 MHz HFRCO

—

34.5

26.8

30.9

40.0

380.0

—

49

µA/MHz

—

1160

silabs.com | Building a more connected world.

Rev. 1.0 | 34

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM2 I_{EM2_VS}

mode, VSCALE0

256 kB RAM and full Radio RAM

retention, RTC running from

LFXO¹

—

4.2

—

µA

256 kB RAM and full Radio RAM

retention, RTC running from

—

4.2

1.8

1.9

2.8

3.9

1.5

9.2

—

µA

LFRCO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFXO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFRCO¹

—

16 kB RAM and full Radio RAM

retention, RTC running from

LFRCO in precision mode¹

—

Current consumption in EM3 I_{EM3_VS}

mode, VSCALE0

256 kB RAM and full Radio RAM

retention, RTC running from

ULFRCO¹

—

16 kB RAM and full Radio RAM

retention, RTC running from

ULFRCO¹

2.5

Change in current consump- I_{EM23_CPUCACHE}

tion if CPU cached unre-

tained in EM2 or EM3

—

-0.07

-0.01

—

µA

Change in current consump- I_{EM23_STATERET}

tion if EM0/1 peripheral

states unretained in EM2 or

EM3

Change in current consump- I_{EM23_RAM}

tion for retained RAM bank in

EM2 or EM3

Per 16 kB RAM bank

—

0.16

1.4

—

µA

Additional current in EM2 or I_{PD0B_VS}

EM3 when any peripheral in

PD0B is enabled²

Additional current in EM2 or I_{PD0C_VS}

EM3 when any peripheral in

—

0.39

1.6

—

µA

PD0C is enabled²

Additional current in EM2 or I_{PD0D_VS}

EM3 when any peripheral in

PD0D is enabled²

Additional current in EM2 or I_{PD0E_VS}

EM3 when any peripheral in

PD0E is enabled²

0.11

Current consumption in EM4 I_EM4

mode

No BURTC, no LF oscillator

BURTC with LFXO

—

0.26

0.64

457

0.65

—

µA

Current consumption during I_RST

reset

Hard pin reset held

—

silabs.com | Building a more connected world.

Rev. 1.0 | 35

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. CPU cache retained, EM0/1 peripheral states retained

2. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.10.4 Power

Domains for a list of the peripherals in each power domain. Note that if the PD0B, PD0C, or PD0D domains are enabled, PD0E

will also automatically be enabled.

silabs.com | Building a more connected world.

Rev. 1.0 | 36

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.6.4 Radio current consumption at 3.0V

RF current consumption measured with MCU in EM1, HCLK = 39.0 MHz, and all MCU peripherals disabled. Unless otherwise indica-

ted, typical conditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = 3.0 V. DCDC disabled. T_A= 25 °C. Minimum and maximum

values in this table represent the worst conditions across process variation at T_A= 25 °C.

Table 4.8. Radio current consumption at 3.0V

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in re-

ceive mode, active packet

reception

I_{RX_ACTIVE}

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

—

7.1

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.5

7.9

7.2

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.6

8

—

mA

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

6.7

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.1

7.4

7.7

—

mA

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

8.1

8.6

7.8

—

mA

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

802.15.4 receiving frame, f = 2.4

GHz, VSCALE1, EM1P (Radio

clocks only)

802.15.4 receiving frame, f = 2.4

GHz, VSCALE1

—

8.2

8.6

—

mA

802.15.4 receiving frame, f = 2.4

GHz, VSCALE2

silabs.com | Building a more connected world.

Rev. 1.0 | 37

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in re-

ceive mode, listening for

packet

I_{RX_LISTEN}

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

—

7.1

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.5

7.9

7.1

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.5

7.9

6.6

—

mA

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7

—

mA

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

7.4

7.7

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

8.2

8.6

7.6

—

mA

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

802.15.4, f = 2.4 GHz, VSCALE1,

EM1P (Radio clocks only)

802.15.4, f = 2.4 GHz, VSCALE1

802.15.4, f = 2.4 GHz, VSCALE2

—

8

8.5

8

—

mA

Current consumption in

transmit mode

I_TX

f = 2.4 GHz, CW, 0 dBm PA, 0

dBm output power, VSCALE2

f = 2.4 GHz, CW, 10 dBm PA, 10

dBm output power, VSCALE2

—

28.7

—

mA

f = 2.4 GHz, CW, 20 dBm PA,

19.5 dBm output power,

159.3

VSCALE2, PAVDD = 3.3 V

f = 2.4 GHz, CW, 0 dBm PA, 0

dBm output power, VSCALE1

—

7.8

28.4

160

—

mA

f = 2.4 GHz, CW, 10 dBm PA, 10

dBm output power, VSCALE1

f = 2.4 GHz, CW, 20 dBm PA,

19.5 dBm output power,

VSCALE1, PAVDD = 3.3 V

silabs.com | Building a more connected world.

Rev. 1.0 | 38

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.6.5 MCU current consumption at 1.8 V

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 1.8 V. DC-DC not used. Voltage

scaling level = VSCALE1. T_A= 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-

tion at T_A= 25 °C.

Table 4.9. MCU current consumption at 1.8 V

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM0 I_ACTIVE

mode with all peripherals dis-

abled

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running Prime from flash,

VSCALE2

—

47.8

—

µA/MHz

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running while loop from flash,

VSCALE2

—

46.1

69.4

—

µA/MHz

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal, CPU

running CoreMark loop from flash,

VSCALE2

39 MHz crystal, CPU running

Prime from flash

—

48.1

47.1

69.8

39.4

43.5

52.5

390.0

32.2

—

µA/MHz

39 MHz crystal, CPU running

while loop from flash

39 MHz crystal, CPU running

CoreMark loop from flash

38 MHz HFRCO, CPU running

while loop from flash

26 MHz HFRCO, CPU running

while loop from flash

16 MHz HFRCO, CPU running

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

Current consumption in EM1 I_EM1

mode with all peripherals dis-

abled

78 MHz HFRCO w/ DPLL refer-

enced to 39 MHz crystal,

VSCALE2

39 MHz crystal

38 MHz HFRCO

26 MHz HFRCO

16 MHz HFRCO

1 MHz HFRCO

—

34.5

26.7

30.8

39.8

377.3

—

µA/MHz

silabs.com | Building a more connected world.

Rev. 1.0 | 39

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM2 I_{EM2_VS}

mode, VSCALE0

256 kB RAM and full Radio RAM

retention, RTC running from

LFXO¹

—

4.1

—

µA

256 kB RAM and full Radio RAM

retention, RTC running from

—

4.1

1.8

2.7

3.7

1.4

—

µA

LFRCO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFXO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFRCO¹

16 kB RAM and full Radio RAM

retention, RTC running from

LFRCO in precision mode¹

Current consumption in EM3 I_{EM3_VS}

mode, VSCALE0

256 kB RAM and full Radio RAM

retention, RTC running from

ULFRCO¹

16 kB RAM and full Radio RAM

retention, RTC running from

ULFRCO¹

Change in current consump- I_{EM23_CPUCACHE}

tion if CPU cached unre-

tained in EM2 or EM3

—

-0.07

-0.01

—

µA

Change in current consump- I_{EM23_STATERET}

tion if EM0/1 peripheral

states unretained in EM2 or

EM3

Change in current consump- I_{EM23_RAM}

tion for retained RAM bank in

EM2 or EM3

Per 16 kB RAM bank

—

0.16

1.4

—

µA

Additional current in EM2 or I_{PD0B_VS}

EM3 when any peripheral in

PD0B is enabled²

Additional current in EM2 or I_{PD0C_VS}

EM3 when any peripheral in

—

0.38

1.6

—

µA

PD0C is enabled²

Additional current in EM2 or I_{PD0D_VS}

EM3 when any peripheral in

PD0D is enabled²

Additional current in EM2 or I_{PD0E_VS}

EM3 when any peripheral in

PD0E is enabled²

0.12

Current consumption in EM4 I_EM4

mode

No BURTC, no LF oscillator

BURTC with LFXO

—

0.18

0.53

391

—

µA

Current consumption during I_RST

reset

Hard pin reset held

silabs.com | Building a more connected world.

Rev. 1.0 | 40

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. CPU cache retained, EM0/1 peripheral states retained

2. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.10.4 Power

Domains for a list of the peripherals in each power domain. Note that if the PD0B, PD0C, or PD0D domains are enabled, PD0E

will also automatically be enabled.

silabs.com | Building a more connected world.

Rev. 1.0 | 41

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.6.6 Radio current consumption at 1.8V

RF current consumption measured with MCU in EM1, HCLK = 39.0 MHz, and all MCU peripherals disabled. Unless otherwise indica-

ted, typical conditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V. DCDC disabled. T_A= 25 °C. Minimum and maximum

values in this table represent the worst conditions across process variation at T_A= 25 °C.

Table 4.10. Radio current consumption at 1.8V

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in re-

ceive mode, active packet

reception

I_{RX_ACTIVE}

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

—

7

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.5

7.9

7.1

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.6

8

—

mA

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

6.6

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

7.1

7.4

7.7

—

mA

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1

—

8.1

8.6

7.8

—

mA

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

802.15.4 receiving frame, f = 2.4

GHz, VSCALE1, EM1P (Radio

clocks only)

802.15.4 receiving frame, f = 2.4

GHz, VSCALE1

—

8.2

8.6

—

mA

802.15.4 receiving frame, f = 2.4

GHz, VSCALE2

silabs.com | Building a more connected world.

Rev. 1.0 | 42

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in re-

ceive mode, listening for

packet

I_{RX_LISTEN}

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

—

7.1

—

mA

125 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

—

7.9

7.1

—

mA

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

500 kbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

—

7.9

6.6

—

mA

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

1 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

—

7.4

7.7

—

mA

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE1, EM1P (Radio clocks

only)

2 Mbit/s, 2GFSK, f = 2.4 GHz,

VSCALE2

—

8.6

7.6

—

mA

802.15.4, f = 2.4 GHz, VSCALE1,

EM1P (Radio clocks only)

802.15.4, f = 2.4 GHz, VSCALE2

—

8.4

7.8

—

mA

Current consumption in

transmit mode

I_TX

f = 2.4 GHz, CW, 0 dBm PA, 0

dBm output power, VSCALE2

f = 2.4 GHz, CW, 10 dBm PA, 10

dBm output power, VSCALE2

—

28.5

7.5

—

mA

f = 2.4 GHz, CW, 0 dBm PA, 0

dBm output power, VSCALE1

f = 2.4 GHz, CW, 10 dBm PA, 10

dBm output power, VSCALE1

28.2

silabs.com | Building a more connected world.

Rev. 1.0 | 43

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.7 Flash Characteristics

Table 4.11. Flash Characteristics

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

Flash Supply voltage during V_FLASH

write or erase

1.71

—

3.8

V

Flash data retention¹

RET_FLASH

EC_FLASH

T_A≤ 125 °C

10

—

years

Flash erase cycles before

failure¹

10,000

cycles

Program Time

t_PROG

T_A= 25 °C, one word (32-bits)

41.9

10.6

43.4

10.9

45.0

11.3

µs

T_A= 25 °C, average per word

over 128 words

Page Erase Time ²

t_PERASE

t_MERASE

I_WRITE

T_A= 25 °C

11.6

144.3

—

12.9

150.5

—

14.0

156.8

2.8

ms

mA

Mass Erase Time^{3 4}

Program Current

Page Erase Current

Mass Erase Current

Note:

T_A= 25 °C, 1536kB

I_PERASE

I_MERASE

Page Erase

Mass Erase

—

1.9

—

2.0

1. Flash data retention information is published in the Quarterly Quality and Reliability Report.

2. Page Erase time is measured from setting the ERASEPAGE bit in the MSC_WRITECMD register until the BUSY bit in the MSC-

STATUS register is cleared to 0. Internal set-up and hold times are included.

3. Mass Erase is issued by the CPU and erases all of User space.

4. Mass Erase time is measured from setting the ERASEMAIN0 bit in the MSC_WRITECMD register until the BUSY bit in the MSC-

STATUS register is cleared to 0. Internal set-up and hold times are included.

silabs.com | Building a more connected world.

Rev. 1.0 | 44

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.8 Energy Mode Wake-up and Entry Times

Unless otherwise specified, these times are measured using the HFRCO at 19 MHz.

Table 4.12. Energy Mode Wake-up and Entry Times

Parameter

Symbol

Test Condition

Min

—

Typ

3

Max

—

Unit

HCLKs

µs

Wake-up Time from EM1

t_{EM1_WU}

Code execution from flash

Code execution from RAM

—

1.4

13.7

—

Wake-up Time from EM2

t_{EM2_WU}

Code execution from flash, No

Voltage Scaling

—

µs

Code execution from RAM, No

Voltage Scaling

—

5.1

—

µs

Voltage scaling up one level¹

Voltage scaling up two levels²

—

37.7

50.7

13.7

—

µs

Wake-up Time from EM3

t_{EM3_WU}

Code execution from flash, No

Voltage Scaling

Code execution from RAM, No

Voltage Scaling

—

5.1

—

µs

Voltage scaling up one level¹

—

37.7

50.7

—

µs

Voltage scaling up two levels²

Code execution from flash

Up from VSCALE1 to VSCALE2

Wake-up Time from EM4

Entry time to EM1

Entry time to EM2

Entry time to EM3

Entry time to EM4

t_{EM4_WU}

t_{EM1_ENT}

t_{EM2_ENT}

t_{EM3_ENT}

t_{EM4_ENT}

t_SCALE

—

21.7

1.5

—

µs

6.1

6.0

11.2

32

Voltage scaling time in EM0³

Down from VSCALE2 to

VSCALE1

172

Note:

1. Voltage scaling one level is between VSCALE0 and VSCALE1 or between VSCALE1 and VSCALE2.

2. Voltage scaling two levels is between VSCALE0 and VSCALE2.

3. During voltage scaling in EM0, RAM is inaccessible and processor will be halted until complete.

silabs.com | Building a more connected world.

Rev. 1.0 | 45

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9 2.4 GHz RF Transceiver Characteristics

4.9.1 RF Transmitter Characteristics

4.9.1.1 RF Transmitter General Characteristics for the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T_A= 25 °C, Crystal frequency=39.0 MHz, RF center frequency = 2.45 GHz.

• For 0 dBm / 10 dBm PA: VREGVDD = IOVDD = AVDD = 3.0 V, DVDD = RFVDD = PAVDD = 1.8 V powered from DCDC

• For 20 dBm PA: VREGVDD = IOVDD = AVDD = PAVDD = 3.3 V, DVDD = RFVDD = 1.8 V powered from DCDC

Table 4.13. RF Transmitter General Characteristics for the 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

2400

—

Typ

—

Max

2483.5

—

Unit

MHz

mA

RF tuning frequency range

F_RANGE

Radio-only current consump- I_{TX_RADIO}

tion while transmitting¹

f = 2.4 GHz, CW, 0 dBm PA, 0

dBm output power

3.5

f = 2.4 GHz, CW, 10 dBm PA, 10

dBm output power

—

17.6

—

mA

Maximum TX power²

POUT_MAX

20 dBm PA, PAVDD = 3.3 V

—

19.5

10

—

dBm

10 dBm PA³

0 dBm PA

—

-0.7

-34

—

dBm

dB

Minimum active TX power

POUT_MIN

20 dBm PA, PAVDD = 3.3 V

10 dBm PA

-29.8

-25.2

0.75

0 dBm PA

Output power variation vs

supply voltage variation, fre-

quency = 2450 MHz

POUT_{VAR_V}

20 dBm PA P_out= POUT_MAXout-

put power with PAVDD voltage

swept from 3.0 V to 3.8 V

10 dbm PA output power with

PAVDD voltage swept from 1.8 V

to 3.0 V

—

0.03

0.02

—

dB

0 dBm PA output power with

PAVDD voltage swept from 1.8 V

to 3.0 V

Output power variation vs

temperature, Frequency =

2450 MHz

POUT_{VAR_T}

PAVDD = 3.3 V supply, 20 dBm

PA at POUT_MAX, (-40 to +125 °C)

—

0.7

0.2

—

dB

10 dBm PA at 10 dBm, (-40 to

+125 °C)

0 dBm PA at 0 dBm, (-40 to +125

°C)

1.23

0.17

Output power variation vs RF POUT_{VAR_F}

frequency

20 dBm PA, POUT_MAX, PAVDD =

3.3 V

10 dBm PA, 10 dBm

0 dBm PA, 0 dBm

—

0.11

0.16

-47

—

dB

Spurious emissions of har-

monics in restricted bands

per FCC Part 15.205/15.209

SPUR_{HRM_FCC_}Continuous transmission of CW

dBm

carrier, P_out= POUT_MAX, Test

Frequency = 2450 MHz.

R

silabs.com | Building a more connected world.

Rev. 1.0 | 46

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Spurious emissions of har-

monics in non-restricted

bands per FCC Part

15.247/15.35

SPUR_{HRM_FCC_}Continuous transmission of CW

—

-26

—

dBc

carrier. P_out= POUT_MAX. Test

NRR

Frequency = 2450 MHz.

Spurious emissions out-of-

band (above 2.483 GHz or

below 2.4 GHz) in restricted

bands, per FCC part

SPUR_{OOB_FCC_}Restricted bands 30-88 MHz,

—

-61

-58

-55

-47

-26

—

dBm

dBc

Continuous transmission of CW

R

carrier, P_out= POUT_MAX, Test

Frequency = 2450 MHz

15.205/15.209

Restricted bands 88 - 216 MHz,

Continuous transmission of CW

carrier, P_out= POUT_MAX, Test

Frequency = 2450 MHz

Restricted bands 216 - 960 MHz,

Continuous transmission of CW

carrier, P_out= POUT_MAX, Test

Frequency = 2450 MHz

Restricted bands > 960 MHz,

Continuous transmission of CW

carrier, P_out= POUT_MAX, Test

Frequency = 2450 MHz

Spurious emissions out-of-

band in non-restricted bands

per FCC Part 15.247

SPUR_{OOB_FCC_}Frequencies above 2.483 GHz or

below 2.4 GHz, continuous trans-

NR

mission CW carrier, P_out

=

POUT_MAX, Test Frequency =

2450 MHz

Spurious emissions per ETSI SPUR_ETSI440

EN300.440

47-74 MHz,87.5-108 MHz,

174-230 MHz, 470-862 MHz, P_out

= 10 dBm, Test Frequency = 2450

MHz

—

-60

-42

—

dBm

25-1000 MHz, excluding above

frequencies. P_out= 10 dBm, Test

Frequency = 2450 MHz

1G-14G, P_out= 10 dBm, Test Fre-

quency = 2450 MHz

—

-36

-26

—

dBm

Spurious emissions out-of-

band, per ETSI 300.328

SPUR_ETSI328

[2400-2BW to 2400-BW],

[2483.5+BW to 2483.5+2BW],

P_out= 10 dBm, Test Frequency =

2450 MHz

47-74 MHz, 87.5-118 MHz,

174-230 MHz, 470-862 MHz, P_out

= 10 dBm, Test Frequency = 2450

MHz

—

-60

-42

—

dBm

30-47 MHz, 74-87.5 MHz,

118-174 MHz, 230-470 MHz,

862-1000 MHz , P_out= 10 dBm,

Test Frequency = 2450 MHz

1G-12.75 GHz, excluding bands

listed above, P_out= 10 dBm, Test

Frequency = 2450 MHz

—

-36

-16

—

dBm

[2400-BW to 2400], [2483.5 to

2483.5+BW] P_out= 10 dBm, Test

Frequency = 2450 MHz

silabs.com | Building a more connected world.

Rev. 1.0 | 47

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Supply current to radio, supplied by DC-DC with 3.0 V, measured at VREGVDD.

2. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this data sheet can be found in the Max TX Power column of the Ordering Information Table.

3. The PA is capable of delivering higher than 10 dBm output power (refer to Output Power plots in 4.27.2 RF Characteristics). How-

ever, all transmitter characteristics and recommended application circuits are specified at 10 dBm output. If used with the recom-

mended application circuits above 10 dBm, harmonics may be higher than regulatory limits.

silabs.com | Building a more connected world.

Rev. 1.0 | 48

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.1.2 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T_A= 25 °C, Crystal frequency=39.0 MHz, RF center frequency = 2.45 GHz.

• For 0 dBm / 10 dBm PA: VREGVDD = IOVDD = AVDD = 3.0 V, DVDD = RFVDD = PAVDD = 1.8 V powered from DCDC

• For 20 dBm PA: VREGVDD = IOVDD = AVDD = PAVDD = 3.3 V, DVDD = RFVDD = 1.8 V powered from DCDC

Table 4.14. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Error vector magnitude per

802.15.4-2011

EVM

Average across frequency, signal

is DSSS-OQPSK reference pack-

—

3

—

% rms

et, PAVDD = 3.3 V, P_out

=

POUT_MAX

Average across frequency, signal

is DSSS-OQPSK reference pack-

et, P_out= 10 dBm

—

2.9

—

% rms

Average across frequency, signal

is DSSS-OQPSK reference pack-

et, P_out= 0 dBm

Power spectral density limit

PSD_LIMIT

Relative, at carrier ± 3.5 MHz,

PAVDD = 3.3 V, P_out= POUT_MAX

—

-50.2

-50.1

-50.7

-38.3

-48.7

-59.2

0.5

—

dBc/

100kHz

Relative, at carrier ± 3.5 MHz,

P_out= 10 dBm

dBc/

100kHz

Relative, at carrier ± 3.5 MHz,

P_out= 0 dBm

dBc/

100kHz

Absolute, at carrier ± 3.5 MHz,

PAVDD = 3.3 V, P_out= POUT_MAX

dBm/

100kHz

Absolute, at carrier ± 3.5 MHz,

P_out= 10 dBm

dBm/

100kHz

Absolute, at carrier ± 3.5 MHz,

P_out= 0 dBm

dBm/

100kHz

Per FCC part 15.247, PAVDD =

3.3 V, P_out= POUT_MAX

dBm/

3kHz

Per FCC part 15.247, P_out= 10

dBm

-9.2

dBm/

3kHz

Per FCC part 15.247, P_out= 0

dBm

-19.9

dBm/

3kHz

ETSI 300.328 P_out= 10 dBm

ETSI 300.328 P_out= 0 dbm

—

8

—

dBm

MHz

-2.8

2.2

Occupied channel bandwidth OCP_ETSI328

per ETSI EN300.328

99% BW at highest and lowest

channels in band, P_out= 10 dBm

99% BW at highest and lowest

channels in band, P_out= 0 dBm

—

2.2

—

MHz

silabs.com | Building a more connected world.

Rev. 1.0 | 49

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.1.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, Crystal frequency=39.0 MHz, RF center frequency = 2.45 GHz.

• For 0 dBm / 10 dBm PA: VREGVDD = IOVDD = AVDD = 3.0 V, DVDD = RFVDD = PAVDD = 1.8 V powered from DCDC

• For 20 dBm PA: VREGVDD = IOVDD = AVDD = PAVDD = 3.3 V, DVDD = RFVDD = 1.8 V powered from DCDC

Table 4.15. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

—

Typ

718

714

715

-0.5

Max

—

Unit

kHz

Transmit 6 dB bandwidth

TXBW

PAVDD = 3.3 V, P_out= POUT_MAX

P_out= 10 dBm

—

P_out= 0 dBm

—

Power spectral density limit

PSD_LIMIT

PAVDD = 3.3 V, P_out= POUT_MAX

Per FCC part 15.247

,

—

dBm/

3kHz

P_out= 10 dBm, Per FCC part

15.247 at 10 dBm

—

-10.4

-21.2

9.7

—

dBm/

3kHz

P_out= 0 dBm, Per FCC part

15.247 at 0 dBm

dBm/

3kHz

Per ETSI 300.328 at 10 dBm/1

MHz

dBm

MHz

dBm

Occupied channel bandwidth OCP_ETSI328

per ETSI EN300.328

P_out= 10 dBm 99% BW at highest

and lowest channels in band

1

P_out= 0 dBm 99% BW at highest

and lowest channels in band

1

In-band spurious emissions, SPUR_INB

with allowed exceptions¹

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 2 MHz

,

-26.9

-38.8

-49.8

-33.2

-43.8

-54.6

P_out= 10 dBm, Inband spurs at ±

2 MHz

P_out= 0 dBm, Inband spurs at ± 2

MHz

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 3 MHz

P_out= 10 dBm Inband spurs at ± 3

MHz

P_out= 0 dBm Inband spurs at ± 3

MHz

Note:

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.

silabs.com | Building a more connected world.

Rev. 1.0 | 50

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.1.4 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, Crystal frequency=39.0 MHz, RF center frequency = 2.45 GHz.

• For 0 dBm / 10 dBm PA: VREGVDD = IOVDD = AVDD = 3.0 V, DVDD = RFVDD = PAVDD = 1.8 V powered from DCDC

• For 20 dBm PA: VREGVDD = IOVDD = AVDD = PAVDD = 3.3 V, DVDD = RFVDD = 1.8 V powered from DCDC

Table 4.16. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

—

Typ

1307

1308

1306

1.5

Max

—

Unit

kHz

Transmit 6 dB bandwidth

TXBW

PAVDD = 3.3 V, P_out= POUT_MAX

P_out= 10 dBm

—

P_out= 0 dBm

—

Power spectral density limit

PSD_LIMIT

PAVDD = 3.3 V, P_out= POUT_MAX

Per FCC part 15.247

,

—

dBm/

3kHz

P_out= 10 dBm, Per FCC part

15.247 at 10 dBm

—

-8.5

-19.3

8.7

—

dBm/

3kHz

P_out= 0 dBm, Per FCC part

15.247 at 0 dBm

dBm/

3kHz

Per ETSI 300.328 at 10 dBm/1

MHz

dBm

MHz

dBm

Occupied channel bandwidth OCP_ETSI328

per ETSI EN300.328

P_out= 10 dBm 99% BW at highest

and lowest channels in band

2.1

P_out= 0 dBm 99% BW at highest

and lowest channels in band

2.1

In-band spurious emissions, SPUR_INB

with allowed exceptions¹

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 2 MHz

,

-33.7

-43.7

-54.5

-38.9

-48.8

-59.5

P_out= 10 dBm, Inband spurs at ±

4 MHz

P_out= 0 dBm, Inband spurs at ± 4

MHz

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 6 MHz

P_out= 10 dBm Inband spurs at ± 6

MHz

P_out= 0 dBm Inband spurs at ± 6

MHz

Note:

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.

silabs.com | Building a more connected world.

Rev. 1.0 | 51

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.1.5 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, Crystal frequency=39.0 MHz, RF center frequency = 2.45 GHz.

• For 0 dBm / 10 dBm PA: VREGVDD = IOVDD = AVDD = 3.0 V, DVDD = RFVDD = PAVDD = 1.8 V powered from DCDC

• For 20 dBm PA: VREGVDD = IOVDD = AVDD = PAVDD = 3.3 V, DVDD = RFVDD = 1.8 V powered from DCDC

Table 4.17. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate

Parameter

Symbol

Test Condition

Min

—

Typ

717

718

717

-0.5

Max

—

Unit

kHz

Transmit 6 dB bandwidth

TXBW

PAVDD = 3.3 V, P_out= POUT_MAX

P_out= 10 dBm

—

P_out= 0 dBm

—

Power spectral density limit

PSD_LIMIT

PAVDD = 3.3 V, P_out= POUT_MAX

Per FCC part 15.247

,

—

dBm/

3kHz

P_out= 10 dBm, Per FCC part

15.247 at 10 dBm

—

-10.4

-21.2

9.7

—

dBm/

3kHz

P_out= 0 dBm, Per FCC part

15.247 at 0 dBm

dBm/

3kHz

Per ETSI 300.328 at 10 dBm/1

MHz

dBm

MHz

dBm

Occupied channel bandwidth OCP_ETSI328

per ETSI EN300.328

P_out= 10 dBm 99% BW at highest

and lowest channels in band

1

P_out= 0 dBm 99% BW at highest

and lowest channels in band

1

In-band spurious emissions, SPUR_INB

with allowed exceptions¹

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 2 MHz

,

-26.9

-38.9

-49.8

-33.2

-43.8

-54.6

P_out= 10 dBm, Inband spurs at ±

2 MHz

P_out= 0 dBm, Inband spurs at ± 2

MHz

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 3 MHz

P_out= 10 dBm Inband spurs at ± 3

MHz

P_out= 0 dBm Inband spurs at ± 3

MHz

Note:

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.

silabs.com | Building a more connected world.

Rev. 1.0 | 52

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.1.6 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, Crystal frequency=39.0 MHz, RF center frequency = 2.45 GHz.

• For 0 dBm / 10 dBm PA: VREGVDD = IOVDD = AVDD = 3.0 V, DVDD = RFVDD = PAVDD = 1.8 V powered from DCDC

• For 20 dBm PA: VREGVDD = IOVDD = AVDD = PAVDD = 3.3 V, DVDD = RFVDD = 1.8 V powered from DCDC

Table 4.18. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate

Parameter

Symbol

Test Condition

Min

—

Typ

651

13.7

Max

—

Unit

kHz

Transmit 6 dB bandwidth

TXBW

PAVDD = 3.3 V, P_out= POUT_MAX

P_out= 10 dBm

—

P_out= 0 dBm

—

Power spectral density limit

PSD_LIMIT

PAVDD = 3.3 V, P_out= POUT_MAX

Per FCC part 15.247

,

—

dBm/

3kHz

P_out= 10 dBm, Per FCC part

15.247 at 10 dBm

—

3.8

-7

—

dBm/

3kHz

P_out= 0 dBm, Per FCC part

15.247 at 0 dBm

dBm/

3kHz

Per ETSI 300.328 at 10 dBm/1

MHz

9.7

dBm

MHz

dBm

Occupied channel bandwidth OCP_ETSI328

per ETSI EN300.328

P_out= 10 dBm 99% BW at highest

and lowest channels in band

1

P_out= 0 dBm 99% BW at highest

and lowest channels in band

1

In-band spurious emissions, SPUR_INB

with allowed exceptions¹

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 2 MHz

,

-26.9

-39

P_out= 10 dBm, Inband spurs at ±

2 MHz

P_out= 0 dBm, Inband spurs at ± 2

MHz

-49.7

-33.1

-43.7

-54.5

PAVDD = 3.3 V, P_out= POUT_MAX

Inband spurs at ± 3 MHz

P_out= 10 dBm Inband spurs at ± 3

MHz

P_out= 0 dBm Inband spurs at ± 3

MHz

Note:

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.

silabs.com | Building a more connected world.

Rev. 1.0 | 53

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.2 RF Receiver Characteristics

4.9.2.1 RF Receiver General Characteristics for the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T_A= 25 °C, VREGVDD = IOVDD = AVDD = PAVDD = 3.0V, RFVDD = DVDD = 1.8

V powered from DCDC. Crystal frequency = 39.0 MHz, RF center frequency = 2.45 GHz.

Table 4.19. RF Receiver General Characteristics for the 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

2400

—

Typ

—

Max

2483.5

—

Unit

MHz

mA

RF tuning frequency range

F_RANGE

Radio-only current consump- I_{RX_RADIO}

tion in receive mode¹

2.8

Receive mode maximum

spurious emission

SPUR_RX

30 MHz to 1 GHz

1 GHz to 12 GHz

—

-63

-53

-55

—

dBm

Max spurious emissions dur- SPUR_{RX_FCC}

ing active receive mode, per

FCC Part 15.109(a)

216 MHz to 960 MHz, conducted

measurement

Above 960 MHz, conducted

measurement.

—

-47

—

dBm

2GFSK Sensitivity

SENS_2GFSK

2 Mbps 2GFSK signal, 1% PER

—

-92.5

—

dBm

250 kbps 2GFSK signal, 0.1%

BER

-102.9

Note:

1. Supply current to radio, supplied by DC-DC with 3.0 V, measured at VREGVDD.

silabs.com | Building a more connected world.

Rev. 1.0 | 54

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.2.2 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T_A= 25 °C, VREGVDD = IOVDD = AVDD = PAVDD = 3.0V, RFVDD = DVDD = 1.8

V powered from DCDC. Crystal frequency = 39.0 MHz, RF center frequency = 2.45 GHz.

Table 4.20. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal¹, packet

length is 20 octets

Max usable receiver input

level, 1% PER

SAT

—

10

—

dBm

Sensitivity, 1% PER

SENS

Signal is reference signal, packet

length is 20 octets

—

-105.4

-0.7

—

dBm

dB

Co-channel interferer rejec- CCR

tion, 1% PER

Desired signal 3 dB above sensi-

tivity limit

Adjacent channel rejection,

Interferer is reference signal,

1% PER, desired is refer-

ence signal at 3 dB above

ACR_REF1

Interferer is reference signal at +1

channel spacing

36.8

37.5

dB

Interferer is reference signal at -1

channel spacing

dB

reference sensitivity level²

Alternate channel rejection,

interferer is reference signal,

1% PER, desired is refer-

ence signal at 3 dB above

ACR_REF2

Interferer is reference signal at +2

channel spacing

—

48.9

49.4

—

dB

Interferer is reference signal at -2

channel spacing

reference sensitivity level²

Interferer is CW in image band³

Image rejection, 1% PER,

desired is reference signal at

3 dB above reference sensi-

tivity level²

IR

—

53.5

—

dB

Blocking rejection of all other BLOCK

channels, 1% PER, desired

is reference signal at 3 dB

above reference sensitivity

level², interferer is reference

signal

Interferer frequency < desired fre-

quency -3 channel spacing

—

55.3

55.1

—

dB

Interferer frequency > desired fre-

quency +3 channel spacing

RSSI resolution

RSSI_RES

RSSI_LIN

-100 dBm to +5 dBm

—

0.25

+/-6

—

dB

RSSI accuracy in the linear

region as defined by

802.15.4-2003

Note:

1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-

bols/s.

2. Reference sensitivity level is -85 dBm.

3. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker

tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection

test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.

silabs.com | Building a more connected world.

Rev. 1.0 | 55

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.2.3 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, VREGVDD = IOVDD = AVDD = PAVDD = 3.0V, RFVDD = DVDD = 1.8

V powered from DCDC. Crystal frequency = 39.0 MHz, RF center frequency = 2.45 GHz, Packet length is 255 bytes.

Table 4.21. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal¹

Max usable receiver input

level

SAT

—

10

—

dBm

Sensitivity

SENS

Signal is reference signal, 37 byte

payload²

—

-97.6

-96

—

dBm

Signal is reference signal, 255

byte payload¹

With non-ideal signals^{3 1}

(see notes)^{1 4}

—

-95.7

8.7

—

dBm

dB

Signal to co-channel interfer- C/I_CC

er

N ± 1 Adjacent channel se-

lectivity

C/I₁

C/I₂

C/I₃

Interferer is reference signal at +1

MHz offset^{1 5 4 6}

—

-5.4

-5.3

—

dB

Interferer is reference signal at -1

MHz offset^{1 5 4 6}

N ± 2 Alternate channel se-

lectivity

Interferer is reference signal at +2

MHz offset^{1 5 4 6}

-40.9

-39.7

-45.5

-45.7

-23.3

Interferer is reference signal at -2

MHz offset^{1 5 4 6}

N ± 3 Alternate channel se-

lectivity

Interferer is reference signal at +3

MHz offset^{1 5 4 6}

Interferer is reference signal at -3

MHz offset^{1 5 4 6}

Selectivity to image frequen- C/I_IM

cy

Interferer is reference signal at im-

age frequency with 1 MHz preci-

sion^{1 6}

Selectivity to image frequen- C/I_{IM_1}

cy ± 1 MHz

Interferer is reference signal at im-

age frequency +1 MHz with 1

—

-40.9

-5.4

—

dB

MHz precision^{1 6}

Interferer is reference signal at im-

age frequency -1 MHz with 1 MHz

precision^{1 6}

n = 3 (see note⁷)

Intermodulation performance IM

-17.3

dBm

Note:

1. 0.017% Bit Error Rate.

2. 0.1% Bit Error Rate.

3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1

4. Desired signal -67 dBm.

5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.

6. With allowed exceptions.

7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4

silabs.com | Building a more connected world.

Rev. 1.0 | 56

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.2.4 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, VREGVDD = IOVDD = AVDD = PAVDD = 3.0V, RFVDD = DVDD = 1.8

V powered from DCDC. Crystal frequency = 39.0 MHz, RF center frequency = 2.45 GHz, Packet length is 255 bytes.

Table 4.22. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal¹

Max usable receiver input

level

SAT

—

10

—

dBm

Sensitivity

SENS

Signal is reference signal, 37 byte

payload²

—

-94.8

-93.3

—

dBm

Signal is reference signal, 255

byte payload¹

With non-ideal signals^{3 1}

(see notes)^{1 4}

—

-93.1

8.6

—

dBm

dB

Signal to co-channel interfer- C/I_CC

er

N ± 1 Adjacent channel se-

lectivity

C/I₁

C/I₂

C/I₃

Interferer is reference signal at +2

MHz offset^{1 5 4 6}

—

-5.3

-5.8

—

dB

Interferer is reference signal at -2

MHz offset^{1 5 4 6}

N ± 2 Alternate channel se-

lectivity

Interferer is reference signal at +4

MHz offset^{1 5 4 6}

-42.2

-44.2

-48.1

-50.2

-22.8

Interferer is reference signal at -4

MHz offset^{1 5 4 6}

N ± 3 Alternate channel se-

lectivity

Interferer is reference signal at +6

MHz offset^{1 5 4 6}

Interferer is reference signal at -6

MHz offset^{1 5 4 6}

Selectivity to image frequen- C/I_IM

cy

Interferer is reference signal at im-

age frequency with 1 MHz preci-

sion^{1 6}

Selectivity to image frequen- C/I_{IM_1}

cy ± 2 MHz

Interferer is reference signal at im-

age frequency +2 MHz with 1

—

-42.2

-5.3

—

dB

MHz precision^{1 6}

Interferer is reference signal at im-

age frequency -2 MHz with 1 MHz

precision^{1 6}

n = 3 (see note⁷)

Intermodulation performance IM

-18.3

dBm

Note:

1. 0.017% Bit Error Rate.

2. 0.1% Bit Error Rate.

3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1

4. Desired signal -64 dBm.

5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.

6. With allowed exceptions.

7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4

silabs.com | Building a more connected world.

Rev. 1.0 | 57

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.2.5 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, VREGVDD = IOVDD = AVDD = PAVDD = 3.0V, RFVDD = DVDD = 1.8

V powered from DCDC. Crystal frequency = 39.0 MHz, RF center frequency = 2.45 GHz, Packet length is 255 bytes.

Table 4.23. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal¹

Max usable receiver input

level

SAT

—

10

—

dBm

Sensitivity

SENS

Signal is reference signal, 37 byte

payload²

—

-101.4

-100.1

—

dBm

Signal is reference signal, 255

byte payload¹

With non-ideal signals^{3 1}

(see notes)^{1 4}

—

-99.1

2.7

—

dBm

dB

Signal to co-channel interfer- C/I_CC

er

N ± 1 Adjacent channel se-

lectivity

C/I₁

C/I₂

C/I₃

Interferer is reference signal at +1

MHz offset^{1 5 4 6}

—

-7.1

-7.4

—

dB

Interferer is reference signal at -1

MHz offset^{1 5 4 6}

N ± 2 Alternate channel se-

lectivity

Interferer is reference signal at +2

MHz offset^{1 5 4 6}

-46.8

-49.7

-49.4

-54.5

-49

Interferer is reference signal at -2

MHz offset^{1 5 4 6}

N ± 3 Alternate channel se-

lectivity

Interferer is reference signal at +3

MHz offset^{1 5 4 6}

Interferer is reference signal at -3

MHz offset^{1 5 4 6}

Selectivity to image frequen- C/I_IM

cy

Interferer is reference signal at im-

age frequency with 1 MHz preci-

sion^{1 6}

Selectivity to image frequen- C/I_{IM_1}

cy ± 1 MHz

Interferer is reference signal at im-

age frequency +1 MHz with 1

—

-49.4

-46.8

—

dB

MHz precision^{1 6}

Interferer is reference signal at im-

age frequency -1 MHz with 1 MHz

precision^{1 6}

Note:

1. 0.017% Bit Error Rate.

2. 0.1% Bit Error Rate.

3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1

4. Desired signal -72 dBm.

5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.

6. With allowed exceptions.

silabs.com | Building a more connected world.

Rev. 1.0 | 58

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.9.2.6 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate

Unless otherwise indicated, typical conditions are: T_A= 25 °C, VREGVDD = IOVDD = AVDD = PAVDD = 3.0V, RFVDD = DVDD = 1.8

V powered from DCDC. Crystal frequency = 39.0 MHz, RF center frequency = 2.45 GHz, Packet length is 255 bytes.

Table 4.24. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal¹

Max usable receiver input

level

SAT

—

10

—

dBm

Sensitivity

SENS

Signal is reference signal, 37 byte

payload²

—

-105.7

-105.3

—

dBm

Signal is reference signal, 255

byte payload¹

With non-ideal signals^{3 1}

(see notes)^{1 4}

—

-104.8

0.9

—

dBm

dB

Signal to co-channel interfer- C/I_CC

er

N ± 1 Adjacent channel se-

lectivity

C/I₁

C/I₂

C/I₃

Interferer is reference signal at +1

MHz offset^{1 5 4 6}

—

-12.4

-12.8

-52.6

-55.5

-53.8

-60

—

dB

Interferer is reference signal at -1

MHz offset^{1 5 4 6}

N ± 2 Alternate channel se-

lectivity

Interferer is reference signal at +2

MHz offset^{1 5 4 6}

Interferer is reference signal at -2

MHz offset^{1 5 4 6}

N ± 3 Alternate channel se-

lectivity

Interferer is reference signal at +3

MHz offset^{1 5 4 6}

Interferer is reference signal at -3

MHz offset^{1 5 4 6}

Selectivity to image frequen- C/I_IM

cy

Interferer is reference signal at im-

age frequency with 1 MHz preci-

sion^{1 6}

-53

Selectivity to image frequen- C/I_{IM_1}

cy ± 1 MHz

Interferer is reference signal at im-

age frequency +1 MHz with 1

—

-53.8

-52.6

—

dB

MHz precision^{1 6}

Interferer is reference signal at im-

age frequency -1 MHz with 1 MHz

precision^{1 6}

Note:

1. 0.017% Bit Error Rate.

2. 0.1% Bit Error Rate.

3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1

4. Desired signal -79 dBm.

5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.

6. With allowed exceptions.

silabs.com | Building a more connected world.

Rev. 1.0 | 59

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.10 Oscillators

4.10.1 High Frequency Crystal Oscillator (HFXO)

Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. T_A= 25 °C. Minimum and maximum values in this table

represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.

Table 4.25. High Frequency Crystal Oscillator (HFXO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

see note^{1 2}

Crystal Frequency

F_HFXO

38.0

39.0

40.0

MHz

Supported crystal maximum ESR_HFXO

equivalent series resistance

(ESR)

Crystal Frequency = 39.0 MHz

—

60

—

Ω

39.0 MHz, ESR = 40 Ω ⁴

39.0 MHz

Supported range of crystal

load capacitance³

C_{L_HFXO}

10

pF

Supply Current

Startup Time⁵

I_HFXO

—

565

188

—

µA

µs

T_STARTUP

39.0 MHz, ESR = 40 Ω, C_L= 10

pF

On-chip tuning cap step

size⁶

SS_HFXO

—

0.04

20

—

pF

HFCLKOUT load capaci-

tance

C_HFCLKOUT

30

HFCLKOUT output voltage

V_HFCLKOUT

0

—

1.2

—

V

HFCLKOUT AC output am-

plitude, XOUTBIASANA = 5,

C_HFCLKOUT= 20 pF

VAC_HFCLKOUT

XOUTCFANA = 0

XOUTCFANA = 1

XOUTCFANA = 2

XOUTCFANA = 3

—

470

510

560

615

3.1

mVpp

mA

HFCLKOUT current con-

sumption

I_HFCLKOUT

C_HFCLKOUT≤ 10 pF, XOUTBIA-

SANA = 3

10 pF < C_HFCLKOUT≤ 20 pF,

XOUTBIASANA = 5

—

3.9

6.3

—

mA

ppm

Ω

20 pF < C_HFCLKOUT≤ 30 pF,

XOUTBIASANA = 15

Frequency shift of HFXTAL

when HFCLKOUT is active

FS_HFCLKOUT

Assuming crystal pullability of 13

ppm/pF

-1.5

—

4.5

—

HFCLKOUT shorting output RS_HFCLKOUT

resistance

When output is disabled

150

Total harmonic distortion,

XOUTBIASANA = 5,

C_HFCLKOUT= 20 pF

THD_HFCLKOUT

XOUTCFANA = 0

XOUTCFANA = 1

XOUTCFANA = 2

XOUTCFANA = 3

—

8.53

10.05

11.98

14.39

—

%

silabs.com | Building a more connected world.

Rev. 1.0 | 60

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. The BLE radio requires a 39.0 MHz crystal with a tolerance of ± 50 ppm over temperature and aging. Please use a crystal with

the recommended frequency and tolerance.

2. The ZigBee radio requires a 39.0 MHz crystal with a tolerance of ± 40 ppm over temperature and aging. Please use a crystal with

the recommended frequency and tolerance.

3. Total load capacitance as seen by the crystal.

4. RF performance characteristics have been determined using crystals with an ESR of 40 Ω and C_Lof 10 pF.

5. Startup time does not include time implemented by programmable TIMEOUTSTEADY delay.

6. The tuning step size is the effective step size when incrementing both of the tuning capacitors by one count. The step size for the

each of the individual tuning capacitors is twice this value.

4.10.2 Low Frequency Crystal Oscillator (LFXO)

Table 4.26. Low Frequency Crystal Oscillator (LFXO)

Parameter

Symbol

Test Condition

Min

—

4

Typ

32.768

—

Max

—

Unit

kHz

kΩ

pF

Crystal Frequency

F_LFXO

Supported Crystal equivalent ESR_LFXO

series resistance (ESR)

GAIN = 0

80

GAIN = 1 to 3

GAIN = 0

—

100

6

Supported range of crystal

load capacitance ¹

C_{L_LFXO}

—

GAIN = 1

6

—

10

pF

GAIN = 2 (see note²)

GAIN = 3 (see note²)

10

—

12.5

pF

12.5

—

18

—

pF

nA

Current consumption

Startup Time

I_CL12p5

ESR = 70 kΩ, C_L= 12.5 pF,

GAIN³= 2, AGC⁴= 1

294

ESR = 70 kΩ, C_L= 7 pF, GAIN³=

1, AGC⁴= 1

T_STARTUP

—

52

—

ms

On-chip tuning cap step size SS_LFXO

—

0.26

5.2

—

pF

On-chip tuning capacitor val- C_{LFXO_MIN}

ue at minimum setting⁵

CAPTUNE = 0

On-chip tuning capacitor val- C_{LFXO_MAX}

ue at maximum setting⁵

CAPTUNE = 0x4F

—

26.2

—

pF

Note:

1. Total load capacitance seen by the crystal

2. Crystals with a load capacitance of greater than 12 pF require external load capacitors.

3. In LFXO_CAL Register

4. In LFXO_CFG Register

5. The effective load capacitance seen by the crystal will be C_LFXO/2. This is because each XTAL pin has a tuning cap and the two

caps will be seen in series by the crystal

silabs.com | Building a more connected world.

Rev. 1.0 | 61

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.10.3 High Frequency RC Oscillator (HFRCO)

Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. T_A= 25 °C. Minimum and maximum values in this table

represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.

Table 4.27. High Frequency RC Oscillator (HFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Frequency Accuracy

F_{HFRCO_ACC}

For all production calibrated fre-

quencies

-3

—

3

%

Current consumption on all

supplies¹

I_HFRCO

F_HFRCO= 4 MHz

—

28

29

—

µA

F_HFRCO= 5 MHz ²

F_HFRCO= 7 MHz

—

59

63

—

µA

F_HFRCO= 10 MHz ²

F_HFRCO= 13 MHz

F_HFRCO= 16 MHz

F_HFRCO= 19 MHz

—

77

87

—

µA

90

F_HFRCO= 20 MHz ²

F_HFRCO= 26 MHz

F_HFRCO= 32 MHz

107

—

116

139

170

—

µA

F_HFRCO= 38 MHz ³

F_HFRCO= 40 MHz ²

F_HFRCO= 48 MHz ³

F_HFRCO= 56 MHz ³

F_HFRCO= 64 MHz ³

F_HFRCO= 80 MHz ³

—

172

207

228

269

285

4.5

—

µA

Clock Out current for

HFRCODPLL⁴

I_{CLKOUT_HFRCOD}FORCEEN bit of HFRCO0_CTRL

µA/MHz

= 1

PLL

Clock Out current for

HFRCOEM23⁴

I_{CLKOUT_HFRCOE}FORCEEN bit of

—

2.0

—

µA/MHz

HFRCOEM23_CTRL = 1

M23

Startup Time⁵

T_STARTUP

FREQRANGE = 0 to 7

FREQRANGE = 8 to 15

—

1.2

0.6

—

µs

silabs.com | Building a more connected world.

Rev. 1.0 | 62

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

3.71

4.39

5.25

6.22

7.88

9.9

Typ

—

Max

5.24

6.26

7.55

9.01

11.6

14.6

17.0

20.9

24.7

30.4

34.9

44.4

51.0

64.6

74.8

87.4

Unit

MHz

Band Frequency Limits⁶

f_{HFRCO_BAND}

FREQRANGE = 0

FREQRANGE = 1

FREQRANGE = 2

FREQRANGE = 3

FREQRANGE = 4

FREQRANGE = 5

FREQRANGE = 6

FREQRANGE = 7

FREQRANGE = 8

FREQRANGE = 9

FREQRANGE = 10

FREQRANGE = 11

FREQRANGE = 12

FREQRANGE = 13

FREQRANGE = 14

FREQRANGE = 15

11.5

14.1

16.4

19.8

22.7

28.6

33.0

42.2

48.8

57.6

Note:

1. Does not include additional clock tree current. See specifications for additional current when selected as a clock source for a par-

ticular clock multiplexer.

2. This frequency is calibrated for the HFRCOEM23 only.

3. This frequency is calibrated for the HFRCODPLL (HFRCO0) only.

4. When the HFRCO is enabled for characterization using the FORCEEN bit, the total current will be the HFRCO core current plus

the specified CLKOUT current. When the HFRCO is enabled on demand, the clock current may be different.

5. Hardware delay ensures settling to within ± 0.5%. Hardware also enforces this delay on a band change.

6. The frequency band limits represent the lowest and highest frequency which each band can achieve over the operating range.

4.10.4 Fast Start-Up RC Oscillator (FSRCO)

Table 4.28. Fast Start-Up RC Oscillator (FSRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

FSRCO frequency

F_FSRCO

17.2

20

21.2

MHz

silabs.com | Building a more connected world.

Rev. 1.0 | 63

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.10.5 Precision Low Frequency RC Oscillator (LFRCO)

Table 4.29. Precision Low Frequency RC Oscillator (LFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Nominal oscillation frequen- F_LFRCO

cy

—

32.768

—

kHz

Frequency accuracy

F_{LFRCO_ACC}

Normal mode

-3

—

3

%

Precision mode¹, across operat-

ing temperature range²

-500

500

ppm

Startup time

t_STARTUP

Normal mode

—

204

—

µs

Precision mode¹

Normal mode

11.7

ms

Current consumption

I_LFRCO

—

189.9

649.8

—

nA

Precision mode¹, T = stable at 25

°C ³

Note:

1. The LFRCO operates in high-precision mode when CFG_HIGHPRECEN is set to 1. High-precision mode is not available in EM4.

2. Includes ± 40 ppm frequency tolerance of the HFXO crystal.

3. Includes periodic re-calibration against HFXO crystal oscillator.

4.10.6 Ultra Low Frequency RC Oscillator (ULFRCO)

Table 4.30. Ultra Low Frequency RC Oscillator (ULFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Oscillation Frequency

F_ULFRCO

0.944

1.0

1.095

kHz

silabs.com | Building a more connected world.

Rev. 1.0 | 64

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.11 GPIO Pins (GPIO)

Table 4.31. GPIO Pins (GPIO)

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

Leakage current

I_{LEAK_IO}

MODEx = DISABLED, IOVDD =

1.71 V

—

1.9

—

nA

MODEx = DISABLED, IOVDD =

3.0 V

—

2.5

—

nA

MODEx = DISABLED, IOVDD =

3.8 V T_A= 125 °C, PB00-PB03,

PC06-PC09, PA00

250

MODEx = DISABLED, IOVDD =

3.8 V T_A= 125 °C, All Other Pins

—

200

nA

V

Input low voltage¹

V_IL

Any GPIO pin

0.3 *

IOVDD

RESETn

—

0.3 * DVDD

—

V

Input high voltage¹

V_IH

Any GPIO pin

0.7 *

IOVDD

RESETn

0.7 * DVDD

—

V

Hysteresis of input voltage

V_HYS

Any GPIO pin

0.05 *

IOVDD

RESETn

0.05 *

DVDD

—

V

Output high voltage

Output low voltage

GPIO rise time

V_OH

Sourcing 20mA, IOVDD = 3.0 V

Sourcing 8mA, IOVDD = 1.71 V

Sinking 20mA, IOVDD = 3.0 V

Sinking 8mA, IOVDD = 1.71 V

0.8 *

IOVDD

0.6 *

IOVDD

—

V

V_OL

—

35

—

0.2 *

IOVDD

V

—

0.4 *

IOVDD

V

T_{GPIO_RISE}

IOVDD = 3.0 V, C_load= 50pF,

SLEWRATE = 4, 10% to 90%

8.4

13

—

55

ns

kΩ

IOVDD = 1.7 V, C_load= 50pF,

SLEWRATE = 4, 10% to 90%

GPIO fall time

T_{GPIO_FALL}

IOVDD = 3.0 V, C_load= 50pF,

SLEWRATE = 4, 90% to 10%

7.1

11.9

44

IOVDD = 1.7 V, C_load= 50pF,

SLEWRATE = 4, 90% to 10%

Pull up/down resistance²

R_PULL

Any GPIO pin. Pull-up to IOVDD:

MODEn = DISABLE DOUT=1.

Pull-down to VSS: MODEn =

WIREDORPULLDOWN DOUT =

0.

RESETn pin. Pull-up to DVDD

MODE = INPUT, DOUT = 1

35

—

44

27

55

—

kΩ

ns

Maximum filtered glitch width T_GF

silabs.com | Building a more connected world.

Rev. 1.0 | 65

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

RESETn low time to ensure T_RESET

pin reset

100

—

ns

Note:

1. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD.

2. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD.

silabs.com | Building a more connected world.

Rev. 1.0 | 66

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.12 Analog to Digital Converter (IADC)

Specified at 1 Msps, ADCCLK = 10 MHz, OSR=2, unless otherwise indicated.

Table 4.32. Analog to Digital Converter (IADC)

Parameter

Symbol

Test Condition

Min

Typ

—

Max

3.8

Unit

V

Main analog supply

V_AVDD

Normal mode

1.71

0

High-Speed mode

—

3.8

V

High-Accuracy mode

Maximum allowable input voltage

—

3.8

V

Maximum Input Range¹

Full-Scale Voltage

V_{IN_MAX}

V_FS

—

AVDD

V

Voltage required for Full-Scale

measurement

—

-V_FS

0

V_REF/ Gain

—

V

Input Measurement Range

V_IN

Differential Mode - Plus and Mi-

nus inputs

—

+V_FS

V_FS

Single Ended Mode - One input

tied to ground

Input Sampling Capacitance Cs

Analog Gain = 1x

—

1.8

3.6

5.4

7.2

0.9

—

10

5

pF

Analog Gain = 2x

Analog Gain = 3x

pF

Analog Gain = 4x

pF

Analog Gain = 0.5x

pF

ADC clock frequency

f_{ADC_CLK}

Normal mode, Gain = 1x or 0.5x

Normal mode, Gain = 2x

Normal mode, Gain = 3x or 4x

MHz

—

2.5

20

High-Speed mode, Gain = 1x or

0.5x

—

High-Speed mode, Gain = 2x

—

10

5

MHz

High-Speed mode, Gain = 3x or

4x

High-Accuracy mode

Normal Mode

—

5

MHz

Msps

Input sampling frequency

Throughput rate

f_S

f_{ADC_CLK}/4

—

1

High-Speed Mode

High-Accuracy Mode

f_SAMPLE

Normal mode, f_{ADC_CLK}= 10

MHz, OSR = 2

Normal mode, f_{ADC_CLK}= 10

MHz, OSR = 32

—

76.9

2

ksps

Msps

ksps

High-Speed mode, f_{ADC_CLK}= 20

MHz, OSR = 2

High-Accuracy mode, f_{ADC_CLK}

5 MHz, OSR = 92

=

10.7

3.88

High-Accuracy mode, f_{ADC_CLK}

5 MHz, OSR = 256

=

silabs.com | Building a more connected world.

Rev. 1.0 | 67

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current from all supplies,

Continuous operation

I_{ADC_CONT}

Normal Mode, 1 Msps, OSR = 2,

f_{ADC_CLK}= 10 MHz

—

305

385

µA

High-Speed Mode, 2 Msps, OSR

= 2, f_{ADC_CLK}= 20 MHz

—

550

655

µA

Current in Standby mode.

ADC is not functional but can

wake up in 1us.

I_STBY

Normal mode

High-Speed mode

High-Accuracy mode

From power down state

From standby state

OSR = 2

—

17

21

10

5

—

20

µA

ADC Startup Time

t_startup

µs

1

µs

Normal Mode ADC Resolu-

tion²

Resolution

12

16

12

16

bits

OSR = 32

High-Speed Mode ADC Res- Resolution_HS

olution²

OSR = 2

OSR = 32

HIgh-Accuracy Mode ADC

Resolution

Resolution_HA

High Accuracy mode. Typical val-

ue is for default OSR = 92 for 10.7

ksps, max value is limited by code

length.

Differential Nonlinearity

DNL

Normal mode. Differential Input.

OSR = 2 (No missing codes)

-1

+/- 0.25

—

1.5

1

LSB12

LSB16

High Speed mode. Differential In-

put. OSR = 2

High-Accuracy mode³. Differential

Input. 10.7 ksps with OSR = 92

Integral Nonlinearity

INL

Normal mode. Differential Input,

OSR = 2

-2.5

—

+/- 0.65

+/- 0.25

2.5

—

LSB12

LSB16

High-Speed mode. Differential In-

put.

High-Accuracy mode³. Differential

Input. External VREF = 1.25 V.

10.7 ksps with OSR = 92

silabs.com | Building a more connected world.

Rev. 1.0 | 68

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Effective number of bits⁴

ENOB

Normal Mode, Differential Input.

Gain = 1x, OSR = 2, f_IN= 10 kHz,

Internal VREF = 1.21V

10.7

11.7

—

bits

Normal Mode, Differential Input.

Gain = 1x, OSR = 32, f_IN= 2.5

kHz, Internal VREF = 1.21 V.

—

13.5

14.3

11.5

15.3

—

bits

Normal Mode, Differential Input.

Gain = 1x, OSR = 32, f_IN= 2.5

kHz, External VREF = 1.25 V.

High Speed mode. Differential In-

put. Gain = 1x, OSR = 2, f_IN= 10

kHz, Internal VREF = 1.21 V

10.7

14.0

High-Accuracy mode³. Differential

Input. Gain = 1x, f_IN= 100 Hz, Ex-

ternal VREF = 1.25 V. 10.7 ksps

with OSR = 92

High-Accuracy mode³. Differential

Input. Gain = 1x, f_IN= 100 Hz, Ex-

ternal VREF = 1.25 V. 3.88 ksps

with OSR = 256

—

16.1

—

bits

Signal to Noise + Distortion

Ratio Normal Mode⁴

SNDR

Differential Input. Gain=1x, OSR =

2, f_IN= 10 kHz, Internal VREF =

1.21V

66

—

66

—

72.3

68.8

72.5

83.9

72.3

68.8

72.5

—

dB

Differential Input. Gain=2x, OSR =

2, f_IN= 10 kHz, Internal VREF =

1.21V

Differential Input. Gain=4x, OSR =

2, f_IN= 10 kHz, Internal VREF =

1.21V

Differential Input. Gain=0.5x, OSR

= 2, f_IN= 10 kHz, Internal VREF =

1.21V

Differential Input. Gain = 1x, OSR

= 64, f_IN= 1.25 kHz, Internal

VREF = 1.21 V

Signal to Noise + Distortion

Ratio High-Speed mode

SNDR_HS

High Speed mode. Differential In-

put. Gain = 1x, OSR = 2, f_IN= 10

kHz, Internal VREF = 1.21 V

High Speed mode. Differential In-

put. Gain = 2x, OSR = 2, f_IN= 10

kHz, Internal VREF = 1.21 V

High Speed mode. Differential In-

put. Gain = 4x, OSR = 2, f_IN= 10

kHz, Internal VREF = 1.21 V

High Speed mode. Differential In-

put. Gain = 0.5x, OSR = 2, f_IN

=

10 kHz, Internal VREF = 1.21 V

silabs.com | Building a more connected world.

Rev. 1.0 | 69

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal to Noise + Distortion

Ratio High-Accuracy mode³

SNDR_HA

High-Accuracy. Differential Input.

Gain = 1x, f_IN= 100 Hz, External

VREF = 1.25 V. 3.88 ksps with

OSR = 256

—

98.7

—

dB

High-Accuracy. Differential Input.

Gain = 1x, f_IN= 100 Hz, External

VREF = 1.25 V. 10.7 ksps with

OSR = 92

86

—

93.8

93.5

91.0

94.7

—

dB

High-Accuracy. Differential Input.

Gain = 2x, f_IN= 100 Hz, External

VREF = 1.25 V. 10.7 ksps with

OSR = 92

High-Accuracy. Differential Input.

Gain = 4x, f_IN= 100 Hz, External

VREF = 1.25 V. 10.7 ksps with

OSR = 92

High-Accuracy. Differential Input.

Gain = 0.5x, f_IN= 100 Hz, Exter-

nal VREF = 1.25 V. 10.7 ksps with

OSR = 92

Total Harmonic Distortion

THD

Normal mode, Differential Input.

Gain = 1x, OSR = 2, f_IN= 10 kHz,

Internal VREF = 1.21 V

—

-80.8

-84.3

-101

-70

-80

dB

High Speed mode, Differential In-

put. Gain = 1x, OSR = 2, f_IN= 10

kHz, Internal VREF = 1.21 V

High-Accuracy mode³, Differential

Input. f_IN= 100 Hz, External

VREF = 1.25 V. 10.7 ksps with

OSR = 92

Spurious-Free Dynamic

Range

SFDR

Normal mode, Differential Input.

Gain = 1x, OSR = 2, f_IN= 10 kHz,

Internal VREF = 1.21 V

72

—

86.5

84.3

—

dB

High Speed mode, Differential In-

put. Gain = 1x, f_IN= 10 kHz, Inter-

nal VREF = 1.21 V

High-Accuracy mode³, Differential

Input. f_IN= 100 Hz, External

VREF = 1.25 V. 10.7 ksps with

OSR = 92

118.1

Common Mode Rejection

Ratio

CMRR

Normal mode. DC to 100 Hz

—

87.0

68.6

86.3

59.0

—

dB

Normal mode. AC high frequency.

High-Speed mode. DC to 100 Hz

High-Speed mode. AC high fre-

quency.

High-Accuracy mode³. DC to 100

Hz

—

93.8

87.0

—

dB

High Accuracy mode³. AC high

frequency.

silabs.com | Building a more connected world.

Rev. 1.0 | 70

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

80.4

33.4

Max

—

Unit

dB

Power Supply Rejection Ra- PSRR

tio

Normal mode. DC to 100 Hz

Normal mode. AC high frequency,

using internal VBGR

—

dB

Normal mode. AC high frequency,

using VREF pad

—

65.2

—

dB

High Speed modes. DC to 100 Hz

—

79.8

31.0

—

dB

High-Speed mode. AC high fre-

quency, using internal VBGR

High Speed mode. AC high fre-

quency, using VREF pad

—

65.0

124

—

dB

High Accuracy mode³. DC to 100

Hz

High-Accuracy mode³. AC high

frequency, using external VREF

pin.

—

85.0

—

dB

External reference voltage

range¹

V_EVREF

1.0

-3

—

AVDD

3

V

Offset Error, Normal mode

OFFSET

GAIN = 1 and 0.5, Differential In-

put

0.27

LSB12

GAIN = 2, Differential Input

GAIN = 3, Differential Input

GAIN = 4, Differential Input

-4

-3

0.27

0.25

0.29

0.27

4

3

LSB12

Offset Error, High-speed

mode

OFFSET_HS

GAIN = 1 and 0.5, Differential In-

put

GAIN = 2, Differential Input

GAIN = 3, Differential Input

GAIN = 4, Differential Input

GAIN = 1, Differential Input

-4

-7

0.27

0.25

0.29

-2.36

4

7

LSB12

LSB16

Offset Error, High-accuracy

mode³

OFFSET_HA

GE

Gain Error, Normal mode

GAIN = 1 and 0.5, using external

VREF, direct mode, f_{ADC_CLK}= 10

MHz

-0.6

-0.155

0.6

%

GAIN = 2, using external VREF,

direct mode, f_{ADC_CLK}= 5 MHz

-0.6

-0.7

-1.1

-1.5

-0.155

0.186

0.227

0.023

0.6

0.7

1.1

1.5

%

GAIN = 3, using external VREF,

direct mode, f_{ADC_CLK}= 2.5 MHz

GAIN = 4, using external VREF,

direct mode, f_{ADC_CLK}= 2.5 MHz

Internal VREF ⁵, all GAIN settings

silabs.com | Building a more connected world.

Rev. 1.0 | 71

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Gain Error, High-speed

mode

GE_HS

GAIN = 1 and 0.5, using external

VREF, direct mode, f_{ADC_CLK}= 20

MHz

-0.6

-0.155

0.6

%

GAIN = 2, using external VREF,

direct mode, f_{ADC_CLK}= 10 MHz

-0.6

-0.7

-1.1

-0.055

0.186

0.227

0.6

0.7

1.1

%

GAIN = 3, using external VREF,

direct mode, f_{ADC_CLK}= 5 MHz

GAIN = 4, using external VREF,

direct mode, f_{ADC_CLK}= 5 MHz

Internal VREF ⁵, all GAIN settings

-1.5

-0.5

0.023

1.5

0.5

%

Gain Error, High-accuracy

mode³

GE_HA

GAIN = 1, using external VREF,

direct mode.

0.0055

Internal Reference voltage

V_IVREF

—

1.21

—

V

Note:

1. When inputs are routed to external GPIO pins, the maximum pin voltage is limited to the lower of the IOVDD and AVDD supplies.

2. ADC output resolution depends on the OSR and digital averaging settings. With no digital averaging, ADC output resolution is 12

bits at OSR = 2, 13 bits at OSR = 4, 14 bits at OSR = 8, 15 bits at OSR = 16, 16 bits at OSR = 32 and 17 bits at OSR = 64. Digital

averaging has a similar impact on ADC output resolution. See the product reference manual for additional details.

3. High-Accuracy mode performance specifications are tested with inputs applied to the dedicated AIN pins.

4. The relationship between ENOB and SNDR is specified according to the equation: ENOB = (SNDR - 1.76) / 6.02.

5. Includes error from internal VREF drift.

silabs.com | Building a more connected world.

Rev. 1.0 | 72

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.13 Analog Comparator (ACMP)

Table 4.33. Analog Comparator (ACMP)

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

BIAS = 0 ¹, HYST = DISABLED

(100 °C max)

ACMP Supply current

I_ACMP

—

71

—

nA

BIAS = 1 ¹, HYST = DISABLED

BIAS = 2 ¹, HYST = DISABLED

—

270

668

2.5

—

nA

µA

BIAS = 3 ¹, HYST = DISABLED

BIAS = 4, HYST = DISABLED

BIAS = 5, HYST = DISABLED

BIAS = 6, HYST = DISABLED

BIAS = 7, HYST = DISABLED

—

5.4

10.6

27

—

µA

—

50

100

—

BIAS = 3 ¹, HYST = SYM30MV

BIAS = 4, HYST = SYM30MV

BIAS = 5, HYST = SYM30MV

BIAS = 6, HYST = SYM30MV

BIAS = 7, HYST = SYM30MV

NEGSEL = VREFDIVAVDD

NEGSEL = VREFDIV1V25

NEGSEL = VREFDIV2V5

ACMP Supply current with

Hysteresis ²

I_{ACMP_WHYS}

3.4

—

7.3

15

—

µA

nA

µA

38

71

Current consumption from

VREFDIV in continuous

mode

I_VREFDIV

3.2

4.3

7.1

81

Current consumption from

VREFDIV in sample/hold

mode

I_{VREFDIV_SH}

NEGSEL = VREFDIV2V5LP

NEGSEL = VREFDIV1V25LP

NEGSEL = VREFDIVAVDDLP

NEGSEL = VSENSE01DIV4

74

76

Current consumption from

VSENSEDIV in continuous

mode

I_VSENSEDIV

1.7

Hysteresis (BIAS = 4) ²

HYST = SYM10MV³

HYST = SYM20MV³

V_HYST

—

18

33

47

—

mV

HYST = SYM30MV³

Reference Voltage

Input offset voltage

V_ACMPREF

Internal 1.25 V Reference

Internal 2.5 V Reference

1.19

2.34

-25

1.25

2.5

—

1.31

2.75

25

V

V_OFFSET

BIAS = 0, VCM = 0.15 to AVDD -

0.15 V

mV

BIAS = 3, VCM = 0.15 to AVDD -

0.15 V

-25

-30

—

25

30

mV

BIAS = 4, VCM = 0.15 to AVDD -

0.15 V

BIAS = 7, VCM = 0.15 to AVDD -

0.15 V

silabs.com | Building a more connected world.

Rev. 1.0 | 73

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

V_IN

Test Condition

Input Voltage Range

BIAS = 0, (100 °C max)

BIAS = 1

Min

0

Typ

—

Max

AVDD

—

Unit

V

Input Range

Comparator delay with 100

mV overdrive

T_DELAY

—

10

µs

ns

2.7

—

BIAS = 2

1.4

—

BIAS = 3

0.58

224

133

80

—

BIAS = 4

—

BIAS = 5

—

ns

BIAS = 6

—

ns

BIAS = 7

63

—

ns

Capacitive Sense Oscillator R_CSRESSEL

Resistance

CSRESSEL = 0

CSRESSEL = 1

CSRESSEL = 2

CSRESSEL = 3

CSRESSEL = 4

CSRESSEL = 5

CSRESSEL = 6

15.9

25.3

43.6

61.9

80.2

98.6

117

—

kΩ

—

Note:

1. When using the 1.25 V or 2.5 V VREF in continuous mode (VREFDIV1V25 or VREFDIV2V5) and BIAS < 4, an additional 1 µA of

supply current is required.

2. Hysteresis is not supported for BIAS=0/1/2. Software should set HYST=DISABLED if using BIAS=0/1/2.

3. V_CM= 1.25 V

silabs.com | Building a more connected world.

Rev. 1.0 | 74

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.14 Digital to Analog Converter (VDAC)

Table 4.34. Digital to Analog Converter (VDAC)

Parameter

Symbol

V_DACOUT

I_DACOUT

f_DAC

Test Condition

Min

0

Typ

—

Max

VREF

10

Unit

V

Output voltage

Output Current

DAC clock frequency

Sample rate

-10

—

mA

MHz

ksps

bits

pF

—

1

SR_DAC

f_DAC= f_DAC(max)

—

500

—

Resolution

N_RESOLUTION

C_LOAD

—

12

—

Load Capacitance¹

High Power and Lower Power

Modes

—

50

High Capacitance Load Mode

25

5

—

nF

kΩ

µA

Load Resistance

R_LOAD

Current consumption, Dy-

namic, 500 ksps, 1 channel

active²

I_{DAC_1_500}

High Power Mode

Low Power Mode

—

281

179

Current consumption, Dy-

namic, 500 ksps, 2 channels

active²

I_{DAC_2_500}

High Power Mode

Low Power Mode

—

445

242

—

µA

Current consumption, Static, I_{DAC_1_STAT}

1 channel active³

High Power Mode

—

135

31

—

4.9

µA

µs

Low Power Mode

High Capacitance Mode

High Power Mode

43

Current consumption, Static, I_{DAC_2_STAT}

2 channels active³

262

53

Low Power Mode

High Capacitance Mode

78

Startup time

Settling time

t_DACSTARTUP

Enable to 90% full scale output,

settling to 10 LSB

4.5

t_DACSETTLE

High Power Mode, 25% to 75% of

full scale, settling to 10 LSB

—

1.1

2.7

1.6

—

µs

Low Power Mode, 25% to 75% of

full scale, settling to 1%

Output impedance

R_OUT

Main Output, High Power Mode

Main Output, Low Power Mode

Vout = 50% full scale, DC output

—

2.1

3.4

—

Ω

Power supply rejection ratio⁴

PSRR

88.6

dB

Signal to noise and distortion SNDR_DAC

ratio

High Power mode, 500 ksps, in-

ternal 2.5 V reference, 1 kHz sine

wave input, BW limited to 250 kHz

65.8

68.0

—

67.2

70.6

-72.5

—

dB

High Power mode, 500 ksps, in-

ternal 2.5 V reference, 1 kHz sine

wave input, BW limited to 22 kHz

—

Total Harmonic Distortion

THD

High Power Mode, internal 2.5 V

reference, 1 kHz sine wave input

-68.7

silabs.com | Building a more connected world.

Rev. 1.0 | 75

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Integral Non-Linearity

INL_DAC

High Power Mode, Across full

temperature range

-5

—

5

LSB

Differential Non-Linearity⁵

Offset error⁶

DNL_DAC

High Power Mode, Across full

temperature range

-1

—

1.3

LSB

V_OFFSET

High Power mode

-15

-25

-35

-1.5

-2

—

15

25

mV

%

Low Power Mode

High Capacitance Load mode

1.25 V internal reference

2.5 V internal reference

External Reference

35

Gain error⁶

V_GAIN

1.5

2

%

-0.6

1.1

0.6

%

External Reference Voltage⁷

V_EXTREF

V_AVDD

V

Note:

1. Main outputs only.

2. Dynamic current specifications are for VDAC circuitry operating at max clock frequency with the output updated at the specified

sampling rate using DMA transfers. Output is a 1 kHz sine wave from 10% to 90% full scale. Specified current does not include

current required to drive the external load. Measurement includes all current from AVDD and DVDD supplies.

3. Static current specifications are for VDAC circuitry operating after a one-time update to a static output at 50% full scale, with the

VDAC APB clock disabled. Specified current does not include current required to drive the external load. Measurement includes

all current from AVDD and DVDD supplies.

4. PSRR calculated as 20 * log₁₀(ΔVDD / ΔV_OUT).

5. Entire range is monotonic and has no missing codes.

6. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at

10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.

7. External reference voltage on VREFP pin or PA00 when used for VREFP

silabs.com | Building a more connected world.

Rev. 1.0 | 76

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.15 Temperature Sensor

Table 4.35. Temperature Sensor

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

Temperature sensor range¹

T_RANGE

-40

—

125

°C

Temperature sensor resolu- T_RESOLUTION

tion

—

0.25

—

°C

Measurement noise (RMS)

T_NOISE

Single measurement

—

0.6

—

°C

16-sample average (TEMPAVG-

NUM = 0)

0.17

64-sample average (TEMPAVG-

NUM = 1)

—

0.12

3.2

—

°C

Temperature offset

T_OFF

Mean error of uncorrected output

across full temperature range

Temperature sensor accura- T_ACC

cy^{2 3}

Direct output accuracy after mean

error (T_OFF) removed

+/-3

After linearization in software, no

calibration

+/-2

After linearization in software, with

single-temperature calibration at

25 °C⁴

+/-1.5

Measurement interval

t_MEAS

—

250

—

ms

Note:

1. The sensor reports absolute die temperature in Kelvin (K). All specifications are in °C to match the units of the specified product

temperature range.

2. Error is measured as the deviation of the mean temperature reading from the expected die temperature. Accuracy numbers rep-

resent statistical minimum and maximum using ± 4 standard deviations of measured error.

3. The raw output of the temperature sensor is a predictable curve. It can be linearized with a polynomial function for additional ac-

curacy.

4. Assuming calibration accuracy of ± 0.25 °C.

silabs.com | Building a more connected world.

Rev. 1.0 | 77

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.16 Brown Out Detectors

4.16.1 DVDD BOD

BOD thresholds on DVDD in EM0 and EM1 only, unless otherwise noted. Typical conditions are at T_A= 25 °C. Minimum and maximum

values in this table represent the worst conditions across process variation, operating supply voltage range, and operating temperature

range.

Table 4.36. DVDD BOD

Parameter

Symbol

Test Condition

Supply Rising

Supply Falling

Min

—

Typ

1.67

1.65

0.95

Max

1.71

—

Unit

V

BOD threshold

V_{DVDD_BOD}

1.62

—

V

BOD response time

BOD hysteresis

Note:

t_{DVDD_BOD_DE-}

Supply dropping at 100 mV/µs

slew rate¹

—

µs

LAY

V_{DVDD_BOD_HYS}

—

25

—

mV

T

1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum

specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

4.16.2 Low-Energy DVDD BOD

BOD thresholds on DVDD pin for low energy modes EM2 to EM4, unless otherwise noted.

Table 4.37. Low-Energy DVDD BOD

Parameter

Symbol

Test Condition

Min

1.5

—

Typ

—

Max

1.71

—

Unit

V

BOD threshold

BOD response time

V_{DVDD_LE_BOD}

Supply Falling

t_{DVDD_LE_BOD_D}Supply dropping at 2 mV/µs slew

50

µs

rate¹

ELAY

BOD hysteresis

V_{DVDD_LE_BOD_}

—

20

—

mV

HYST

Note:

1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum

specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

silabs.com | Building a more connected world.

Rev. 1.0 | 78

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.16.3 AVDD and IOVDD BODs

BOD thresholds for AVDD BOD and IOVDD BOD. Available in all energy modes.

Table 4.38. AVDD and IOVDD BODs

Parameter

Symbol

V_BOD

Test Condition

Min

1.45

—

Typ

—

Max

1.71

—

Unit

V

BOD threshold

BOD response time

Supply falling

t_{BOD_DELAY}

Supply dropping at 2 mV/µs slew

rate¹

50

µs

BOD hysteresis

V_{BOD_HYST}

—

24

—

mV

Note:

1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum

specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

4.17 Pulse Counter (PCNT)

Table 4.39. Pulse Counter (PCNT)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input frequency

F_IN

Asynchronous Single and Quad-

rature Modes

—

1.0

MHz

Sampled Modes with Debounce

filter set to 0.

—

53

47

—

8

kHz

ns

Setup time in asynchronous t_{SU_S1N_S0N}

external clock mode

S1N (data) to S0N (clock)

—

Hold time in asynchronous

external clock mode

t_{HD_S0N_S1N}

S0N (clock) to S1N (data)

ns

silabs.com | Building a more connected world.

Rev. 1.0 | 79

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.18 USART SPI Main Timing

t_{CS_MO}

CS

t_{SCLK_MO}

SCLK

CLKPOL = 0

t_SCLK

SCLK

CLKPOL = 1

MOSI

MISO

t_{SU_MI}

t_{H_MI}

Figure 4.1. SPI Main Timing (SMSDELAY = 0)

t_{CS_MO}

CS

t_{SCLK_MO}

SCLK

CLKPOL = 0

t_SCLK

SCLK

CLKPOL = 1

MOSI

MISO

t_{SU_MI}

t_{H_MI}

Figure 4.2. SPI Main Timing (SMSDELAY = 1)

silabs.com | Building a more connected world.

Rev. 1.0 | 80

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.18.1 USART SPI Main Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.40. USART SPI Main Timing, Voltage Scaling = VSCALE2

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period^{1 2 3}

CS to MOSI^{1 2}

SCLK to MOSI^{1 2}

MISO setup time^{1 2}

t_SCLK

2*t_PCLK

—

ns

t_{CS_MO}

t_{SCLK_MO}

t_{SU_MI}

-15

-6

—

15

13

ns

IOVDD = 1.62 V

IOVDD = 3.0 V

40

31

-9

—

ns

MISO hold time^{1 2}

t_{H_MI}

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1.

2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply.

3. t_PCLKis one period of the selected PCLK.

4.18.2 USART SPI Main Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.41. USART SPI Main Timing, Voltage Scaling = VSCALE1

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period^{1 2 3}

CS to MOSI^{1 2}

SCLK to MOSI^{1 2}

MISO setup time^{1 2}

t_SCLK

2*t_PCLK

—

ns

t_{CS_MO}

t_{SCLK_MO}

t_{SU_MI}

-26

-7

—

25

24

ns

IOVDD = 1.62 V

IOVDD = 3.0 V

50

42

-9

—

ns

MISO hold time^{1 2}

t_{H_MI}

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1.

2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply.

3. t_PCLKis one period of the selected PCLK.

silabs.com | Building a more connected world.

Rev. 1.0 | 81

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.19 USART SPI Secondary Timing

t_{CS_ACT_MI}

CS

t_{CS_DIS_MI}

SCLK

CLKPOL = 0

t_{SCLK_HI}

t_{SCLK_LO}

SCLK

t_{SU_MO}

CLKPOL = 1

t_SCLK

t_{H_MO}

MOSI

MISO

t_{SCLK_MI}

Figure 4.3. SPI Secondary Timing (SSSEARLY = 0)

t_{CS_ACT_MI}

CS

t_{CS_DIS_MI}

SCLK

CLKPOL = 0

t_{SCLK_HI}

t_{H_MO}

t_{SCLK_LO}

SCLK

CLKPOL = 1

t_SCLK

t_{SU_MO}

MOSI

MISO

t_{SCLK_MI}

Figure 4.4. SPI Secondary Timing (SSSEARLY = 1)

silabs.com | Building a more connected world.

Rev. 1.0 | 82

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.19.1 USART SPI Secondary Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.42. USART SPI Secondary Timing, Voltage Scaling = VSCALE2

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period^{1 2 3}

t_SCLK

6*t_PCLK

—

ns

SCLK high time^{1 2 3}

SCLK low time^{1 2 3}

CS active to MISO^{1 2}

CS disable to MISO^{1 2}

MOSI setup time^{1 2}

MOSI hold time^{1 2 3}

SCLK to MISO^{1 2 3}

t_{SCLK_HI}

t_{SCLK_LO}

t_{CS_ACT_MI}

t_{CS_DIS_MI}

t_{SU_MO}

2.5*t_PCLK

—

67

89

—

ns

2.5*t_PCLK

19

24

12

13

t_{H_MO}

t_{SCLK_MI}

14 +

1.5*t_PCLK

24 +

2.5*t_PCLK

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply (figure shows 50%).

3. t_PCLKis one period of the selected PCLK.

4.19.2 USART SPI Secondary Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.43. USART SPI Secondary Timing, Voltage Scaling = VSCALE1

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period^{1 2 3}

t_SCLK

6*t_PCLK

—

ns

SCLK high time^{1 2 3}

SCLK low time^{1 2 3}

CS active to MISO^{1 2}

CS disable to MISO^{1 2}

MOSI setup time^{1 2}

MOSI hold time^{1 2 3}

SCLK to MISO^{1 2 3}

t_{SCLK_HI}

t_{SCLK_LO}

t_{CS_ACT_MI}

t_{CS_DIS_MI}

t_{SU_MO}

2.5*t_PCLK

—

96

87

—

ns

2.5*t_PCLK

25

24

13

14

t_{H_MO}

t_{SCLK_MI}

17 +

1.5*t_PCLK

33 +

2.5*t_PCLK

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 8 pF output loading at 10% and 90% of the I/O supply (figure shows 50%).

3. t_PCLKis one period of the selected PCLK.

silabs.com | Building a more connected world.

Rev. 1.0 | 83

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.20 EUSART SPI Main Timing

t_{CS_MO}

CS

t_{SCLK_MO}

SCLK

CLKPOL = 0

t_SCLK

SCLK

CLKPOL = 1

MOSI

MISO

t_{SU_MI}

t_{H_MI}

Figure 4.5. SPI Main Timing

4.20.1 EUSART SPI Main Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew

rate = 6.

Table 4.44. EUSART SPI Main Timing, Voltage Scaling = VSCALE2

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period^{1 2 3}

CS to MOSI^{1 2}

SCLK to MOSI^{1 2}

MISO setup time ^{1 2}

t_SCLK

t_CLK

—

ns

t_{CS_MO}

t_{SCLK_MO}

t_{SU_MI}

-10

-3

—

9

8

ns

6

—

MISO hold time^{1 2}

t_{H_MI}

-21

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1.

2. Measurement done with 15 pF output loading at 10% and 90% of V_DD

.

3. t_CLKis one period of the selected peripheral clock: EM01GRPCCLK for EUSART1/2, EUSART0CLK for EUSART0.

silabs.com | Building a more connected world.

Rev. 1.0 | 84

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.20.2 EUSART SPI Main Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew

rate = 6.

Table 4.45. EUSART SPI Main Timing, Voltage Scaling = VSCALE1

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period^{1 2 3}

CS to MOSI^{1 2}

SCLK to MOSI^{1 2}

MISO setup time ^{1 2}

t_SCLK

t_CLK

—

ns

t_{CS_MO}

t_{SCLK_MO}

t_{SU_MI}

-19

-6

—

15

13

—

ns

10

-13

MISO hold time^{1 2}

t_{H_MI}

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1.

2. Measurement done with 15 pF output loading at 10% and 90% of V_DD

.

3. t_CLKis one period of the selected peripheral clock: EM01GRPCCLK for EUSART1/2, EUSART0CLK for EUSART0.

silabs.com | Building a more connected world.

Rev. 1.0 | 85

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.21 EUSART SPI Secondary Timing

t_{CS_ACT_MI}

CS

t_{CS_DIS_MI}

SCLK

CLKPOL = 0

t_{SCLK_HI}

t_{SCLK_LO}

SCLK

t_{SU_MO}

CLKPOL = 1

t_SCLK

t_{H_MO}

MOSI

MISO

t_{SCLK_MI}

Figure 4.6. SPI Secondary Timing

4.21.1 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew

rate = 6.

Table 4.46. EUSART SPI Secondary Timing, Voltage Scaling = VSCALE2

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK high time^{1 2}

SCLK low time^{1 2}

CS active to MISO^{1 2}

CS disable to MISO^{1 2}

MOSI setup time^{1 2}

MOSI hold time^{1 2}

SCLK to MISO^{1 2}

t_{SCLK_HI}

50

—

ns

t_{SCLK_LO}

t_{CS_ACT_MI}

t_{CS_DIS_MI}

t_{SU_MO}

50

4

—

49

34

—

ns

5

t_{H_MO}

6

t_{SCLK_MI}

IOVDD = 1.8 V

IOVDD = 3.0 V

8

—

40

30

ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 15 pF output loading at 10% and 90% of V_DD(figure shows 50% of V_DD).

silabs.com | Building a more connected world.

Rev. 1.0 | 86

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.21.2 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD) on consecutive pins. All GPIO set to slew

rate = 6.

Table 4.47. EUSART SPI Secondary Timing, Voltage Scaling = VSCALE1

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK high time^{1 2}

SCLK low time^{1 2}

CS active to MISO^{1 2}

CS disable to MISO^{1 2}

MOSI setup time^{1 2}

MOSI hold time^{1 2}

SCLK to MISO^{1 2}

t_{SCLK_HI}

50

—

ns

t_{SCLK_LO}

t_{CS_ACT_MI}

t_{CS_DIS_MI}

t_{SU_MO}

50

6

—

75

56

—

ns

5

4

t_{H_MO}

6

t_{SCLK_MI}

IOVDD = 1.8 V

IOVDD = 3.0 V

9

—

49

41

ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 15 pF output loading at 10% and 90% of V_DD(figure shows 50% of V_DD).

4.21.3 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE0

Timing specifications at VSCALE0 apply to EUSART0 only, routed to DBUSAB on consecutive pins. All GPIO set to slew rate = 6.

Table 4.48. EUSART SPI Secondary Timing, Voltage Scaling = VSCALE0

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK high time^{1 2}

SCLK low time^{1 2}

CS active to MISO^{1 2}

CS disable to MISO^{1 2}

MOSI setup time^{1 2}

MOSI hold time^{1 2}

SCLK to MISO^{1 2}

t_{SCLK_HI}

100

—

ns

t_{SCLK_LO}

t_{CS_ACT_MI}

t_{CS_DIS_MI}

t_{SU_MO}

100

8

—

100

70

—

ns

7

9

t_{H_MO}

32

—

t_{SCLK_MI}

IOVDD = 1.8 V

IOVDD = 3.0 V

11

—

86

78

ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 15 pF output loading at 10% and 90% of V_DD(figure shows 50% of V_DD).

silabs.com | Building a more connected world.

Rev. 1.0 | 87

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.22 I2C Electrical Specifications

4.22.1 I2C Standard-mode (Sm)

CLHR set to 0 in the I2Cn_CTRL register.

Table 4.49. I2C Standard-mode (Sm)

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

SCL clock frequency¹

SCL clock low time

SCL clock high time

SDA set-up time

f_SCL

0

—

100

kHz

t_LOW

4.7

4

—

µs

ns

µs

t_HIGH

t_{SU_DAT}

t_{HD_DAT}

250

0

SDA hold time

Repeated START condition t_{SU_STA}

set-up time

4.7

Repeated START condition t_{HD_STA}

hold time

4.0

—

µs

STOP condition set-up time t_{SU_STO}

4.0

4.7

—

µs

Bus free time between a

t_BUF

STOP and START condition

Note:

1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable

SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV

should be set to a value that keeps the SCL clock frequency below the max value listed.

silabs.com | Building a more connected world.

Rev. 1.0 | 88

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.22.2 I2C Fast-mode (Fm)

CLHR set to 1 in the I2Cn_CTRL register.

Table 4.50. I2C Fast-mode (Fm)

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

SCL clock frequency¹

SCL clock low time

SCL clock high time

SDA set-up time

f_SCL

0

—

400

kHz

t_LOW

1.3

0.6

100

0

—

µs

ns

µs

t_HIGH

t_{SU_DAT}

t_{HD_DAT}

SDA hold time

Repeated START condition t_{SU_STA}

set-up time

0.6

Repeated START condition t_{HD_STA}

hold time

0.6

—

µs

STOP condition set-up time t_{SU_STO}

0.6

1.3

—

µs

Bus free time between a

t_BUF

STOP and START condition

Note:

1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable

SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV

should be set to a value that keeps the SCL clock frequency below the max value listed.

silabs.com | Building a more connected world.

Rev. 1.0 | 89

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.22.3 I2C Fast-mode Plus (Fm+)

CLHR set to 1 in the I2Cn_CTRL register.

Table 4.51. I2C Fast-mode Plus (Fm+)

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

SCL clock frequency¹

SCL clock low time

SCL clock high time

SDA set-up time

f_SCL

0

—

1000

kHz

t_LOW

0.5

0.26

50

—

µs

ns

µs

t_HIGH

t_{SU_DAT}

t_{HD_DAT}

SDA hold time

0

Repeated START condition t_{SU_STA}

set-up time

0.26

Repeated START condition t_{HD_STA}

hold time

0.26

—

µs

STOP condition set-up time t_{SU_STO}

0.26

0.5

—

µs

Bus free time between a

t_BUF

STOP and START condition

Note:

1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable

SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV

should be set to a value that keeps the SCL clock frequency below the max value listed.

4.23 Boot Timing

Secure boot impacts the recovery time from all sources of device reset. In addition to the root code authentication process, which can-

not be disabled or bypassed, the root code can authenticate a bootloader, and the bootloader can authenticate the application. In

projects that include only an application and no bootloader, the root code can authenticate the application directly. The duration of each

authentication operation depends on two factors: the computation of the associated image hash, which is proportional to the size of the

image, and the verification of the image signature, which is independent of image size.

The duration for the root code to authenticate the bootloader will depend on the SE firmware version as well as on the size of the boot-

loader.

The duration for the bootloader to authenticate the application can depend on the size of the application.

The configurations below assume that the associated bootloader and application code images do not contain a bootloader certificate or

an application certificate. Authenticating a bootloader certificate or an application certificate will extend the boot time by an additional 6

to 7 ms.

The table below provides the durations from the termination of reset until the completion of the secure boot process (start of main()

function in the application image) under various conditions.

Conditions:

• SE firmware version 2.1.5

• Gecko Bootloader size 24 KB

Timing is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any significant changes.

silabs.com | Building a more connected world.

Rev. 1.0 | 90

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Table 4.52. Boot Timing

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Boot time¹

t_BOOT

Secure boot application check dis-

abled, 50 kB application size

—

37.7

—

ms

Secure boot application check en-

abled, 50 kB application size

—

48.3

51.0

56.4

—

ms

Secure boot application check en-

abled, 150 kB application size

Secure boot application check en-

abled, 350 kB application size

Note:

1. Secure boot check of second stage bootloader enabled for all measurements.

silabs.com | Building a more connected world.

Rev. 1.0 | 91

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.24 Crypto Operation Timing for SE Manager API

Values in this table represent timing from SE Manager API call to return. The Cortex-M33 HCLK frequency is 39.0 MHz. The timing

specifications below are measured at the SE Manager function call API. Each duration in the table contains some portion that is influ-

enced by SE Manager build compilation and Cortex-M33 operating frequency and some portion that is influenced by the Hardware Se-

cure Engine's firmware version and its operating speed (typically 80 MHz). The contributions of the Cortex-M33 properties to the overall

specification timing are most pronounced for the shorter operations such as AES and hash when operating on small payloads. The

overhead of command processing at the mailbox interface can also dominate the timing for shorter operations.

Conditions:

• SE firmware version 2.1.5

• GSDK version 3.2

Timing is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any significant changes.

Table 4.53. Crypto Operation Timing for SE Manager API

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

AES-128 timing

t_AES128

AES-128 CCM encryption, PT 1

kB

—

571

—

µs

AES-128 CCM encryption, PT 32

kB

—

1751

474

—

µs

AES-128 CTR encryption, PT 1

kB

AES-128 CTR encryption, PT 32

kB

1043

522

AES-128 GCM encryption, PT 1

kB

AES-128 GCM encryption, PT 32

kB

1087

585

AES-256 timing

t_AES256

AES-256 CCM encryption, PT 1

kB

AES-256 CCM encryption, PT 32

kB

2184

482

AES-256 CTR encryption, PT 1

kB

AES-256 CTR encryption, PT 32

kB

1255

529

AES-256 GCM encryption, PT 1

kB

AES-256 GCM encryption, PT 32

kB

1306

ECC P-256 timing

ECC P-521 timing¹

t_{ECC_P256}

ECC key generation, P-256

ECC signing, P-256

—

5.5

5.9

—

ms

ECC verification, P-256

ECC key generation, P-521

ECC signing, P-521

6.2

t_{ECC_P521}

30.2

31.0

36.2

ECC verification, P-521

silabs.com | Building a more connected world.

Rev. 1.0 | 92

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

4.5

Max

—

Unit

ms

ECC P-25519 timing²

t_{ECC_P25519}

ECC key generation, P-25519

ECC signing, P-25519

ECC verification, P-25519

—

8.9

—

6.3

—

ECDH compute secret, P-521¹

ECDH compute secret timing t_ECDH

—

30.5

—

ECDH compute secret, P-25519²

ECDH compute secret, P-256

ECJPAKE client write round one

ECJPAKE client read round one

ECJPAKE client write round two

ECJPAKE client read round two

ECJPAKE client derive secret

ECJPAKE server write round one

ECJPAKE server read round one

ECJPAKE server write round two

ECJPAKE server read round two

ECJPAKE server derive secret

POLY-1305, PT 1 kB

—

4.5

—

ms

—

5.6

21.4

11.7

15.2

6.3

—

ms

µs

ECJPAKE client timing

t_{ECJPAKE_C}

8.8

ECJPAKE server timing

t_{ECJPAKE_S}

21.4

11.7

15.3

6.4

8.8

POLY-1305 timing¹

SHA-256 timing

t_POLY1305

t_SHA256

t_SHA512

514

1177

308

737

305

620

POLY-1305, PT 32 kB

µs

SHA-256, PT 1 kB

µs

SHA-256, PT 32 kB

µs

SHA-512 timing¹

SHA-512, PT 1 kB

µs

SHA-512, PT 32 kB

µs

Note:

1. Option is only available on OPNs with Secure Vault High feature set.

2. Option is not available on Secure Vault Mid devices with SE firmware earlier than v2.1.7.

silabs.com | Building a more connected world.

Rev. 1.0 | 93

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.25 Crypto Operation Average Current for SE Manager API

Values in this table represent current consumed by security core during the operation, and represent additions to the current consumed

by the Cortex-M33 application CPU due to the Hardware Secure Engine CPU and its associated crypto accelerators. The current meas-

urements below represent the average value of the current for the duration of the crypto operation. Instantaneous peak currents may be

higher.

Conditions:

• SE firmware version 2.1.5

• GSDK version 3.2

Current consumption is expected to be similar for subsequent SE firmware versions. Refer to SE firmware release notes for any signifi-

cant changes.

Table 4.54. Crypto Operation Average Current for SE Manager API

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

AES-128 current

I_AES128

AES-128 CCM encryption, PT 1

kB

—

0.9

—

mA

AES-128 CCM encryption, PT 32

kB

—

3.9

0.8

3.8

0.8

3.8

1.0

4.0

0.8

4.0

0.8

3.9

—

mA

AES-128 CTR encryption, PT 1

kB

AES-128 CTR encryption, PT 32

kB

AES-128 GCM encryption, PT 1

kB

AES-128 GCM encryption, PT 32

kB

AES-256 current

I_AES256

AES-256 CCM encryption, PT 1

kB

AES-256 CCM encryption, PT 32

kB

AES-256 CTR encryption, PT 1

kB

AES-256 CTR encryption, PT 32

kB

AES-256 GCM encryption, PT 1

kB

AES-256 GCM encryption, PT 32

kB

ECC P-256 current

ECC P-521 current¹

I_ECCP256

ECC key generation, P-256

ECC signing, P-256

—

1.7

1.6

1.7

1.8

—

mA

ECC verification, P-256

ECC key generation, P-521

ECC signing, P-521

I_ECCP521

ECC verification, P-521

silabs.com | Building a more connected world.

Rev. 1.0 | 94

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

1.6

1.8

Max

—

Unit

mA

ECC P-25519 current²

I_ECCP25519

ECC key generation, P-25519

ECC signing, P-25519

ECC verification, P-25519

—

ECDH compute secret, P-521¹

ECDH compute secret cur-

rent

I_ECDH

—

ECDH compute secret, P-25519²

ECDH compute secret, P-256

ECJPAKE client write round one

ECJPAKE client read round one

ECJPAKE client write round two

ECJPAKE client read round two

ECJPAKE client derive secret

ECJPAKE server write round one

ECJPAKE server read round one

ECJPAKE server write round two

ECJPAKE server read round two

ECJPAKE server derive secret

POLY-1305, PT 1 kB

—

1.5

—

mA

—

1.6

1.7

1.6

1.7

0.6

1.6

0.7

2.3

0.7

1.9

—

mA

ECJPAKE client current

I_{ECJPAKE_C}

ECJPAKE server current

I_{ECJPAKE_S}

POLY-1305 current¹

SHA-256 current

I_POLY1305

I_SHA256

I_SHA512

POLY-1305, PT 32 kB

SHA-256, PT 1 kB

SHA-256, PT 32 kB

SHA-512 current¹

SHA-512, PT 1 kB

SHA-512, PT 32 kB

Note:

1. Option is only available on OPNs with Secure Vault High feature set.

2. Option is not available on Secure Vault Mid devices with SE firmware earlier than v2.1.7.

silabs.com | Building a more connected world.

Rev. 1.0 | 95

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.26 Matrix Vector Processor (MVP)

All measurements are in comparison to EM1 baseline current at given VSCALE and Clock settings. Matrix dimensions are X = 24 x 32,

Y = 32 x 24 and Z = 24 x 24.

Table 4.55. Matrix Vector Processor (MVP)

Parameter

Symbol

Test Condition

Min

—

Typ

16.8

41.2

Max

—

Unit

µA

MVP Enable Current

I_EN

VSCALE1, HFXO @ 39 MHz

VSCALE2, HFRCO w/ DPLL @

78 MHz

—

µA

Matrix Multiplication Duration T_{MVP_MULTIPLY}16-bit complex numbers, fully

—

504.0

252.0

596.2

298.2

41.0

20.5

19.7

9.9

—

µs

using MVP Hardware

banked memory, VSCALE1,

HFXO @ 39 MHz

16-bit complex numbers, fully

banked memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

16-bit complex numbers, inter-

leaved memory, VSCALE1, HFXO

@ 39 MHz

µs

16-bit complex numbers, inter-

leaved memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

µs

Matrix Multiplication Duration T_{SW_MULTIPLY}

using Software

16-bit complex numbers, inter-

leaved memory, VSCALE1, HFXO

@ 39 MHz

ms

16-bit complex numbers, inter-

leaved memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

ms

32-bit complex numbers, inter-

leaved memory, VSCALE1, HFXO

@ 39 MHz

ms

32-bit complex numbers, inter-

leaved memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

ms

Matrix Multiplication Current I_{MVP_MULTIPLY}

using MVP Hardware

16-bit complex numbers, fully

banked memory, VSCALE1,

HFXO @ 39 MHz

61.3

62.4

53.2

53.8

µA/MHz

16-bit complex numbers, fully

banked memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

16-bit complex numbers, inter-

leaved memory, VSCALE1, HFXO

@ 39 MHz

16-bit complex numbers, inter-

leaved memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

silabs.com | Building a more connected world.

Rev. 1.0 | 96

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Matrix Multiplication Current I_{SW_MULTIPLY}

using Software

16-bit complex numbers, inter-

leaved memory, VSCALE1, HFXO

@ 39 MHz

—

41.7

—

µA/MHz

16-bit complex numbers, inter-

leaved memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

—

44.7

31.9

33.8

—

µA/MHz

32-bit complex numbers, inter-

leaved memory, VSCALE1, HFXO

@ 39 MHz

32-bit complex numbers, inter-

leaved memory, VSCALE2,

HFRCO w/ DPLL @ 78 MHz

4.27 Typical Performance Curves

Typical performance curves indicate typical characterized performance under the stated conditions.

silabs.com | Building a more connected world.

Rev. 1.0 | 97

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.27.1 Supply Current

Figure 4.7. EM0 and EM1 Typical Supply Current vs. Temperature

silabs.com | Building a more connected world.

Rev. 1.0 | 98

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Figure 4.8. EM2 and EM4 Typical Supply Current vs. Temperature

silabs.com | Building a more connected world.

Rev. 1.0 | 99

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.27.2 RF Characteristics

Figure 4.9. 2.4 GHz 20 dBm PA RF Transmitter Output Power (Pout=19.5 dBm)

Figure 4.10. 2.4 GHz 10 dBm PA RF Transmitter Output Power (Pout=10 dBm)

silabs.com | Building a more connected world.

Rev. 1.0 | 100

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Figure 4.11. 2.4 GHz 0 dBm PA RF Transmitter Output Power (Pout=0 dBm)

Figure 4.12. 2.4 GHz 802.15.4 RF Receiver Sensitivity

silabs.com | Building a more connected world.

Rev. 1.0 | 101

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

Figure 4.13. 2.4 GHz BLE RF Receiver Sensitivity

4.27.3 DC-DC Converter

Performance characterized with Murata DFE2HCAH2R2MJ0 (L_DCDC= 2.2 uH ) and TDK CGA5L3X8R1C475K160AB (C_DCDC= 4.7 uF)

Figure 4.14. DC-DC Efficiency

silabs.com | Building a more connected world.

Rev. 1.0 | 102

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.27.4 IADC

Typical performance is shown using 10 MHz ADC clock for fastest sampling speed and adjusting oversampling ratio (OSR).

Figure 4.15. Typical ENOB vs. Oversampling Ratio

silabs.com | Building a more connected world.

Rev. 1.0 | 103

EFR32MG24 Wireless SoC Family Data Sheet

Electrical Specifications

4.27.5 GPIO

Figure 4.16. VOH and VOL vs. Load Current

silabs.com | Building a more connected world.

Rev. 1.0 | 104

EFR32MG24 Wireless SoC Family Data Sheet

Typical Connections

5. Typical Connections

5.1 Power

Typical power supply connections are shown in the following figures.

Note: PAVDD, RFVDD, AVDD, and IOVDD supply connections are flexible. They may be connected in other configurations or to exter-

nal supplies as long as the supply limits described in 4.1 Electrical Characteristics are met.

V_DD

Main

Supply

+

–

VREGVDD

AVDD

IOVDD

VREGSW

HFXTAL_I

HFXTAL_O

LFXTAL_I

39.0 MHz

VREGVSS

DVDD

32.768 kHz

(optional)

LFXTAL_O

DECOUPLE

V_DD

RFVDD

PAVDD

C_DECOUPLE

Figure 5.1. EFR32MG24 Typical Application Circuit: Direct Supply Configuration without DCDC

V_DD

Main

Supply

+

–

C_IN

VREGVDD

AVDD

IOVDD

L_DCDC

C_DCDC

V_DCDC

VREGSW

VREGVSS

HFXTAL_I

HFXTAL_O

LFXTAL_I

39.0 MHz

DVDD

32.768 kHz

(optional)

LFXTAL_O

DECOUPLE

C_DECOUPLE

RFVDD

PAVDD

Figure 5.2. EFR32MG24 Typical Application Circuit: DCDC Configuration, PAVDD and RFVDD from DCDC output, AVDD and

IOVDD from main supply

silabs.com | Building a more connected world.

Rev. 1.0 | 105

EFR32MG24 Wireless SoC Family Data Sheet

Typical Connections

V_DD

V_DCDC

Main

Supply

+

–

C_IN

VREGVDD

AVDD

IOVDD

L_DCDC

C_DCDC

V_DCDC

VREGSW

VREGVSS

HFXTAL_I

HFXTAL_O

LFXTAL_I

39.0 MHz

DVDD

32.768 kHz

(optional)

LFXTAL_O

DECOUPLE

C_DECOUPLE

RFVDD

PAVDD

Figure 5.3. EFR32MG24 Typical Application Circuit: DCDC Configuration with PAVDD, RFVDD, AVDD, and IOVDD from DCDC

output

5.2 Other Connections

Other components or connections may be required to meet the system-level requirements. Application Note AN0002.2: "EFR32 Wire-

less Gecko Series 2 Hardware Design Considerations" contains detailed information on these connections. Application Notes can be

accessed on the Silicon Labs website (www.silabs.com/32bit-appnotes).

silabs.com | Building a more connected world.

Rev. 1.0 | 106

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

6. Pin Definitions

6.1 QFN48 / Standard Device Pinout

Figure 6.1. QFN48 / Standard Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 6.5 Alternate Function Table, 6.6 Analog Peripheral Connectivity, and 6.7 Digital Peripheral

Connectivity.

Table 6.1. QFN48 / Standard Device Pinout

Pin Name

PC00

Pin(s) Description

Pin Name

PC01

Pin(s) Description

1

3

5

7

9

GPIO

2

4

GPIO

PC02

PC03

PC04

PC05

6

PC06

PC07

8

PC08

PC09

10

silabs.com | Building a more connected world.

Rev. 1.0 | 107

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

HFXTAL_I

11

13

High Frequency Crystal Input

HFXTAL_O

12

14

High Frequency Crystal Output

Radio power supply

Reset Pin. The RESETn pin is internally

pulled up to DVDD.

RESETn

RFVDD

RFVSS

PAVDD

PB04

15

17

19

21

23

25

27

29

31

33

Radio Ground

RF2G4_IO

PB05

16

18

20

22

24

26

28

30

32

34

2.4 GHz RF input/output

Power Amplifier (PA) power supply

GPIO

PB03

GPIO

PB02

GPIO

PB01

GPIO

PB00

GPIO

VREFN

PA00

Dedicated ADC VREF Negative Input

VREFP

PA01

Dedicated ADC VREF Positive Input

GPIO

PA02

PA03

PA04

PA05

PA06

PA07

PA08

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PA09

35

GPIO

DECOUPLE

36

VREGSW

VREGVSS

AVDD

37

39

41

43

45

47

DCDC regulator switching node

VREGVDD

DVDD

IOVDD

PD04

38

40

42

44

46

48

DCDC regulator input supply

Digital power supply

I/O power supply

GPIO

DCDC ground

Analog power supply

GPIO

PD05

PD03

GPIO

PD02

GPIO

PD01

GPIO

PD00

GPIO

silabs.com | Building a more connected world.

Rev. 1.0 | 108

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

6.2 QFN48 / ADC Device Pinout

Figure 6.2. QFN48 / ADC Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 6.5 Alternate Function Table, 6.6 Analog Peripheral Connectivity, and 6.7 Digital Peripheral

Connectivity.

Table 6.2. QFN48 / ADC Device Pinout

Pin Name

PC00

Pin(s) Description

Pin Name

PC01

Pin(s) Description

1

3

GPIO

2

4

GPIO

PC02

GPIO

PC03

GPIO

PC04

5

GPIO

PC05

6

GPIO

PC06

7

GPIO

PC07

8

GPIO

PC08

9

GPIO

PC09

10

12

GPIO

HFXTAL_I

11

High Frequency Crystal Input

HFXTAL_O

High Frequency Crystal Output

silabs.com | Building a more connected world.

Rev. 1.0 | 109

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

Reset Pin. The RESETn pin is internally

pulled up to DVDD.

RESETn

13

RFVDD

14

Radio power supply

RFVSS

PAVDD

PB02

PB00

AIN3

15

17

19

21

23

25

27

29

31

33

Radio Ground

RF2G4_IO

PB03

16

18

20

22

24

26

28

30

32

34

2.4 GHz RF input/output

Power Amplifier (PA) power supply

GPIO

PB01

GPIO

VREFN

AIN2

Dedicated ADC VREF Negative Input

Dedicated ADC Input 3

Dedicated ADC Input 2

AIN1

Dedicated ADC Input 1

AIN0

Dedicated ADC Input 0

VREFP

PA01

PA03

PA05

Dedicated ADC VREF Positive Input

PA00

GPIO

PA02

PA04

PA06

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PA07

35

GPIO

DECOUPLE

36

VREGSW

VREGVSS

AVDD

37

39

41

43

45

47

DCDC regulator switching node

VREGVDD

DVDD

IOVDD

PD04

38

40

42

44

46

48

DCDC regulator input supply

Digital power supply

I/O power supply

GPIO

DCDC ground

Analog power supply

GPIO

PD05

PD03

GPIO

PD02

GPIO

PD01

GPIO

PD00

GPIO

silabs.com | Building a more connected world.

Rev. 1.0 | 110

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

6.3 QFN40 / Standard Device Pinout

Figure 6.3. QFN40 / Standard Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 6.5 Alternate Function Table, 6.6 Analog Peripheral Connectivity, and 6.7 Digital Peripheral

Connectivity.

Table 6.3. QFN40 / Standard Device Pinout

Pin Name

PC00

Pin(s) Description

Pin Name

PC01

Pin(s) Description

1

3

5

7

9

GPIO

2

4

GPIO

PC02

GPIO

PC03

GPIO

PC04

GPIO

PC05

6

GPIO

PC06

GPIO

PC07

8

GPIO

HFXTAL_I

High Frequency Crystal Input

HFXTAL_O

10

High Frequency Crystal Output

Reset Pin. The RESETn pin is internally

pulled up to DVDD.

RESETn

11

RFVDD

12

Radio power supply

silabs.com | Building a more connected world.

Rev. 1.0 | 111

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

Pin Name

RFVSS

PAVDD

PB03

Pin(s) Description

Pin Name

RF2G4_IO

PB04

Pin(s) Description

13

15

17

19

21

23

25

27

Radio Ground

14

16

18

20

22

24

26

28

2.4 GHz RF input/output

Power Amplifier (PA) power supply

GPIO

PB02

PB01

PB00

PA00

PA01

PA02

PA03

PA04

PA05

PA06

PA07

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PA08

29

GPIO

DECOUPLE

30

VREGSW

VREGVSS

AVDD

31

33

35

37

39

DCDC regulator switching node

DCDC ground

VREGVDD

DVDD

32

34

36

38

40

DCDC regulator input supply

Digital power supply

I/O power supply

GPIO

Analog power supply

GPIO

IOVDD

PD02

PD03

PD01

GPIO

PD00

GPIO

silabs.com | Building a more connected world.

Rev. 1.0 | 112

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

6.4 QFN40 / HFCLKOUT Device Pinout

Figure 6.4. QFN40 / HFCLKOUT Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 6.5 Alternate Function Table, 6.6 Analog Peripheral Connectivity, and 6.7 Digital Peripheral

Connectivity.

Table 6.4. QFN40 / HFCLKOUT Device Pinout

Pin Name

PC00

Pin(s) Description

Pin Name

PC01

Pin(s) Description

1

3

5

7

9

GPIO

2

4

GPIO

PC02

GPIO

PC03

GPIO

PC04

GPIO

PC05

6

GPIO

PC06

GPIO

HFCLKOUT

HFXTAL_O

8

High Frequency Clock Output

High Frequency Crystal Output

HFXTAL_I

High Frequency Crystal Input

10

Reset Pin. The RESETn pin is internally

pulled up to DVDD.

RESETn

11

RFVDD

12

Radio power supply

silabs.com | Building a more connected world.

Rev. 1.0 | 113

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

Pin Name

RFVSS

PAVDD

PB03

Pin(s) Description

Pin Name

RF2G4_IO

PB04

Pin(s) Description

13

15

17

19

21

23

25

27

Radio Ground

14

16

18

20

22

24

26

28

2.4 GHz RF input/output

Power Amplifier (PA) power supply

GPIO

PB02

PB01

PB00

PA00

PA01

PA02

PA03

PA04

PA05

PA06

PA07

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PA08

29

GPIO

DECOUPLE

30

VREGSW

VREGVSS

AVDD

31

33

35

37

39

DCDC regulator switching node

DCDC ground

VREGVDD

DVDD

32

34

36

38

40

DCDC regulator input supply

Digital power supply

I/O power supply

GPIO

Analog power supply

GPIO

IOVDD

PD02

PD03

PD01

GPIO

PD00

GPIO

silabs.com | Building a more connected world.

Rev. 1.0 | 114

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

6.5 Alternate Function Table

A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows GPIO pins with support

for dedicated functions across the different package options.

Table 6.5. GPIO Alternate Function Table

QFN48 /

Standard

Package¹

QFN40 /

Standard

QFN40 /

HFCLKOUT

QFN48 / ADC

Package²

GPIO

Alternate Functions

Package³

Yes

Package⁴

Yes

PA00

PA01

PA02

IADC0.VREFP

GPIO.SWCLK

Yes

GPIO.SWDIO

GPIO.SWV

PA03

GPIO.TDO

GPIO.TRACEDATA0

GPIO.TDI

PA04

PA05

GPIO.TRACECLK

GPIO.TRACEDATA1

GPIO.EM4WU0

PA06

PA07

PB00

GPIO.TRACEDATA2

GPIO.TRACEDATA3

VDAC0.VDAC_CH0_MAIN_OUTPUT

GPIO.EM4WU3

PB01

PB02

PB03

VDAC0.VDAC_CH1_MAIN_OUTPUT

VDAC1.VDAC_CH0_MAIN_OUTPUT

GPIO.EM4WU4

VDAC1.VDAC_CH1_MAIN_OUTPUT

GPIO.EM4WU6

PC00

PC01

PC02

GPIO.EFP_TX_SDA

GPIO.EFP_TX_SCL

GPIO.EFP_INT

PC05

PC06

GPIO.EM4WU7

GPIO.THMSW_EN

GPIO.THMSW_HALFSWITCH

GPIO.EM4WU8

Yes

PC07

GPIO.THMSW_EN

GPIO.THMSW_HALFSWITCH

GPIO.THMSW_EN

GPIO.THMSW_HALFSWITCH

LFXO.LFXTAL_O

Yes

PC09

PD00

Yes

silabs.com | Building a more connected world.

Rev. 1.0 | 115

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

QFN48 /

Standard

Package¹

QFN40 /

Standard

Package³

QFN40 /

HFCLKOUT

Package⁴

QFN48 / ADC

Package²

GPIO

Alternate Functions

LFXO.LFXTAL_I

LFXO.LF_EXTCLK

GPIO.EM4WU9

GPIO.EM4WU10

Yes

PD01

Yes

PD02

PD05

Note:

Yes

1. QFN48 / Standard Package includes OPNs EFR32MG24A010F1024IM48-B, EFR32MG24A010F1536IM48-B,

EFR32MG24A020F1024IM48-B, EFR32MG24A020F1536IM48-B, EFR32MG24A410F1536IM48-B,

EFR32MG24A420F1536IM48-B, EFR32MG24B010F1024IM48-B, EFR32MG24B010F1536IM48-B,

EFR32MG24B020F1024IM48-B, EFR32MG24B020F1536IM48-B, EFR32MG24B210F1536IM48-B, and

EFR32MG24B220F1536IM48-B

2. QFN48 / ADC Package includes OPNs EFR32MG24A110F1024IM48-B, EFR32MG24B110F1536IM48-B,

EFR32MG24B120F1536IM48-B, and EFR32MG24B310F1536IM48-B

3. QFN40 / Standard Package includes OPNs EFR32MG24A010F1024IM40-B, EFR32MG24A010F1536IM40-B,

EFR32MG24A020F1024IM40-B, EFR32MG24A020F1536IM40-B, EFR32MG24A410F1536IM40-B,

EFR32MG24A420F1536IM40-B, EFR32MG24B010F1536IM40-B, and EFR32MG24B020F1536IM40-B

4. QFN40 / HFCLKOUT Package includes OPN EFR32MG24A021F1024IM40-B

6.6 Analog Peripheral Connectivity

Many analog resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are avail-

able on each GPIO port. When a differential connection is being used Positive inputs are restricted to the EVEN pins and Negative

inputs are restricted to the ODD pins. When a single ended connection is being used positive input is available on all pins. See the

device Reference Manual for more details on the ABUS and analog peripherals. Note that some functions may not be available on all

device variants.

Table 6.6. ABUS Routing Table

Peripheral

ACMP0

ACMP1

IADC0

Signal

PA

ODD

PB

ODD

PC

ODD

PD

ODD

EVEN

Yes

EVEN

Yes

EVEN

Yes

EVEN

Yes

ANA_NEG

ANA_POS

ANA_NEG

ANA_POS

ANA_NEG

ANA_POS

Yes

VDAC0

VDAC_CH0_ABUS_OUT-

PUT

VDAC_CH1_ABUS_OUT

Yes

VDAC1

VDAC_CH0_ABUS_OUT-

PUT

VDAC_CH1_ABUS_OUT

Yes

silabs.com | Building a more connected world.

Rev. 1.0 | 116

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

6.7 Digital Peripheral Connectivity

Many digital resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are availa-

ble on each GPIO port. Note that some functions may not be available on all device variants.

Table 6.7. DBUS Routing Table

Peripheral.Resource

PORT

PC

PA

PB

PD

ACMP0.DIGOUT

ACMP1.DIGOUT

CMU.CLKIN0

Available

CMU.CLKOUT0

CMU.CLKOUT1

CMU.CLKOUT2

EUSART0.CS

Available

EUSART0.CTS

EUSART0.RTS

EUSART0.RX

EUSART0.SCLK

EUSART0.TX

EUSART1.CS

Available

EUSART1.CTS

EUSART1.RTS

EUSART1.RX

EUSART1.SCLK

EUSART1.TX

FRC.DCLK

FRC.DFRAME

FRC.DOUT

HFXO0.BUFOUT_REQ_IN_ASYNC

I2C0.SCL

Available

I2C0.SDA

I2C1.SCL

I2C1.SDA

KEYSCAN.COL_OUT_0

KEYSCAN.COL_OUT_1

KEYSCAN.COL_OUT_2

KEYSCAN.COL_OUT_3

KEYSCAN.COL_OUT_4

Available

silabs.com | Building a more connected world.

Rev. 1.0 | 117

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

Peripheral.Resource

PORT

PC

PA

PB

PD

KEYSCAN.COL_OUT_5

KEYSCAN.COL_OUT_6

KEYSCAN.COL_OUT_7

KEYSCAN.ROW_SENSE_0

KEYSCAN.ROW_SENSE_1

KEYSCAN.ROW_SENSE_2

KEYSCAN.ROW_SENSE_3

KEYSCAN.ROW_SENSE_4

KEYSCAN.ROW_SENSE_5

LETIMER0.OUT0

Available

LETIMER0.OUT1

MODEM.ANT0

Available

MODEM.ANT1

MODEM.ANT_ROLL_OVER

MODEM.ANT_RR0

MODEM.ANT_RR1

MODEM.ANT_RR2

MODEM.ANT_RR3

MODEM.ANT_RR4

MODEM.ANT_RR5

MODEM.ANT_SW_EN

MODEM.ANT_SW_US

MODEM.ANT_TRIG

MODEM.ANT_TRIG_STOP

MODEM.DCLK

Available

MODEM.DIN

MODEM.DOUT

PCNT0.S0IN

PCNT0.S1IN

PRS.ASYNCH0

PRS.ASYNCH1

PRS.ASYNCH2

PRS.ASYNCH3

PRS.ASYNCH4

PRS.ASYNCH5

PRS.ASYNCH6

Available

silabs.com | Building a more connected world.

Rev. 1.0 | 118

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

Peripheral.Resource

PORT

PC

PA

PB

PD

PRS.ASYNCH7

PRS.ASYNCH8

PRS.ASYNCH9

PRS.ASYNCH10

PRS.ASYNCH11

PRS.ASYNCH12

PRS.ASYNCH13

PRS.ASYNCH14

PRS.ASYNCH15

PRS.SYNCH0

PRS.SYNCH1

PRS.SYNCH2

PRS.SYNCH3

RAC.LNAEN

Available

RAC.PAEN

TIMER0.CC0

TIMER0.CC1

TIMER0.CC2

TIMER0.CDTI0

TIMER0.CDTI1

TIMER0.CDTI2

TIMER1.CC0

TIMER1.CC1

TIMER1.CC2

TIMER1.CDTI0

TIMER1.CDTI1

TIMER1.CDTI2

TIMER2.CC0

TIMER2.CC1

TIMER2.CC2

TIMER2.CDTI0

TIMER2.CDTI1

TIMER2.CDTI2

TIMER3.CC0

Available

TIMER3.CC1

TIMER3.CC2

silabs.com | Building a more connected world.

Rev. 1.0 | 119

EFR32MG24 Wireless SoC Family Data Sheet

Pin Definitions

Peripheral.Resource

PORT

PC

PA

PB

PD

TIMER3.CDTI0

TIMER3.CDTI1

TIMER3.CDTI2

TIMER4.CC0

TIMER4.CC1

TIMER4.CC2

TIMER4.CDTI0

TIMER4.CDTI1

TIMER4.CDTI2

USART0.CLK

USART0.CS

Available

USART0.CTS

USART0.RTS

USART0.RX

USART0.TX

silabs.com | Building a more connected world.

Rev. 1.0 | 120

EFR32MG24 Wireless SoC Family Data Sheet

QFN40 Package Specifications

7. QFN40 Package Specifications

7.1 QFN40 Package Dimensions

Figure 7.1. QFN40 Package Drawing

silabs.com | Building a more connected world.

Rev. 1.0 | 121

EFR32MG24 Wireless SoC Family Data Sheet

QFN40 Package Specifications

Table 7.1. QFN40 Package Dimensions

Dimension

Min

0.80

0.00

Typ

0.85

Max

0.90

0.05

A

A1

A3

b

0.02

0.20 REF

0.20

0.15

4.90

3.55

0.25

5.10

3.85

D

5.00

E

5.00

D2

E2

e

3.70

0.40 BSC

0.40

L

0.30

0.20

0.50

—

K

—

R

0.075

—

aaa

bbb

ccc

ddd

eee

fff

0.10

0.07

0.10

0.05

0.08

0.10

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

5. Package external pad (epad) may have pin one chamfer.

silabs.com | Building a more connected world.

Rev. 1.0 | 122

EFR32MG24 Wireless SoC Family Data Sheet

QFN40 Package Specifications

7.2 QFN40 PCB Land Pattern

Figure 7.2. QFN40 PCB Land Pattern Drawing

Table 7.2. QFN40 PCB Land Pattern Dimensions

Dimension

Typ

4.25

3.85

0.40

0.22

0.74

0.11

S1

S

L1

W1

e

W

L

R

silabs.com | Building a more connected world.

Rev. 1.0 | 123

EFR32MG24 Wireless SoC Family Data Sheet

QFN40 Package Specifications

Dimension

Typ

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

4. The stencil thickness should be 0.101 mm (4 mils).

5. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.

6. A 3x3 array of 0.90 mm square openings on a 1.20 mm pitch can be used for the center ground pad.

7. A No-Clean, Type-3 solder paste is recommended.

8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

9. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use

different parameters and fine tune their SMT process as required for their application and tooling.

7.3 QFN40 Package Marking

PPPP

PPPPPP

TTTTTT

YYWW

Figure 7.3. QFN40 Package Marking

The package marking consists of:

• Line 1: PPPP – The product family codes (BG24 | MG24)

• Line 2: PPPPPP – The product option codes:

• 1) Security ( A = Secure Vault Mid | B = Secure Vault High )

• 2-4) Product Feature Codes

• 5) Flash ( J = 1024k | V = 1536k )

• 6) Temperature grade (G = -40 to 85 °C | I = -40 to 125 °C )

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

silabs.com | Building a more connected world.

Rev. 1.0 | 124

EFR32MG24 Wireless SoC Family Data Sheet

QFN48 Package Specifications

8. QFN48 Package Specifications

8.1 QFN48 Package Dimensions

Figure 8.1. QFN48 Package Drawing

silabs.com | Building a more connected world.

Rev. 1.0 | 125

EFR32MG24 Wireless SoC Family Data Sheet

QFN48 Package Specifications

Table 8.1. QFN48 Package Dimensions

Dimension

Min

0.80

0.00

Typ

0.85

0.02

0.20 REF

0.2

Max

0.90

0.05

A

A1

A3

b

0.15

5.90

0.25

6.10

D

6.00

0.40 BSC

4.30

0.4

E

e

D2

E2

L

4.15

0.30

0.20

0.075

4.45

0.50

—

K

—

R

—

aaa

bbb

ccc

ddd

eee

fff

0.10

0.07

0.10

0.05

0.08

0.10

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Outline MS-013, Variation AA.

4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.

silabs.com | Building a more connected world.

Rev. 1.0 | 126

EFR32MG24 Wireless SoC Family Data Sheet

QFN48 Package Specifications

8.2 QFN48 PCB Land Pattern

Figure 8.2. QFN48 PCB Land Pattern Drawing

Table 8.2. QFN48 PCB Land Pattern Dimensions

Dimension

Typ

0.86

0.22

0.40

5.01

4.45

0.11

L

W

e

S

S1

L1

W1

R

silabs.com | Building a more connected world.

Rev. 1.0 | 127

EFR32MG24 Wireless SoC Family Data Sheet

QFN48 Package Specifications

Dimension

Typ

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

5. The stencil thickness should be 0.101 mm (4 mils).

6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.

7. A 3x3 array of 1.10mm x 1.10mm openings on 1.30mm pitch should be used for the center ground pad.

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

10. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use

different parameters and fine tune their SMT process as required for their application and tooling.

8.3 QFN48 Package Marking

PPPP

PPPPPP

TTTTTT

YYWW

Figure 8.3. QFN48 Package Marking

The package marking consists of:

• Line 1: PPPP – The product family codes (BG24 | MG24)

• Line 2: PPPPPP – The product option codes:

• 1) Security ( A = Secure Vault Mid | B = Secure Vault High )

• 2-4) Product Feature Codes

• 5) Flash ( J = 1024k | V = 1536k )

• 6) Temperature grade (G = -40 to 85 °C | I = -40 to 125 °C )

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

silabs.com | Building a more connected world.

Rev. 1.0 | 128

EFR32MG24 Wireless SoC Family Data Sheet

Revision History

9. Revision History

Revision 1.0

August, 2022

• Updated "TBD" values in 4.1 Electrical Characteristics tables

• Updates to System Overview Table 3.3 Configuration Summary on page 21 table

• Added 4.27 Typical Performance Curves

• Corrected DCDC output capacitor part number in 4.4 DC-DC Converter

• Modified ACMP Electrical Specifications to show that hysteresis is only supported when BIAS >= 3 in 4.13 Analog Comparator

(ACMP)

• Added "T=25°C" condition to all timing specs in 4.7 Flash Characteristics

Revision 0.6

April, 2022

• Updated values in 4.1 Electrical Characteristics tables

Revision 0.5

March, 2022

• Updated front page block diagram

• Updated typical power consumption and performance numbers and Protocol Support in 1. Feature List

• Updated values in 4.1 Electrical Characteristics tables

• Updated 5. Typical Connections Diagrams

• Updated Package Marking diagrams for 40QFN and 48QFN packages

Revision 0.4

Jan 2022

• Updated front page content

• Updated typical power consumption numbers and Protocol Support in 1. Feature List

• Updated list of OPNs in table

• Removed -G temperature grade information from Electrical Specification tables

• Added typical EM2/3/4 current data to 4.6 Current Consumption tables

• Revised EM2/3 spec format in 4.6 Current Consumption tables

• Added Startup Time and Current Consumption data to 4.10.5 Precision Low Frequency RC Oscillator (LFRCO) table

silabs.com | Building a more connected world.

Rev. 1.0 | 129

EFR32MG24 Wireless SoC Family Data Sheet

Revision History

Revision 0.3

Oct 2021

• Updated typical power consumption numbers in 1. Feature List

• Added IADC High Speed / High Accuracy information and Package Pinout information to table

• Updated IADC information in System Overview

• Corrected "RTCC" to "SYSRTC" in 1. Feature List

• Added 20-bit ADC resolution and sampling rate to 1. Feature List

• Added DALI function to EUSART in 1. Feature List

• In Table 3.2 Peripheral Power Subdomains on page 18 table

• Removed "Tamper"

• Corrected "LFRCO" cells

• Removed "EUSART1"

• Removed footnote from FSRCO suggesting it operates in EM4

• Revised table to show PD0A and PDHV columns

• Revised section text content

• Removed AVDD/DVDD power mux from Figure 3.1 Detailed EFR32MG24 Block Diagram on page 9

Revision 0.2

June 2021

In Electrical Specifications section:

• Added EUSART timing and specifications

• Renamed USART specifications

• Added RX Sensitivity Specifications

• Removed Wi-Fi Notch Filter from Electrical Specifications

Revision 0.1

March 2021

Initial release.

silabs.com | Building a more connected world.

Rev. 1.0 | 130

Simplicity Studio

One-click access to MCU and wireless

tools, documentation, software,

source code libraries & more. Available

for Windows, Mac and Linux!

IoT Portfolio

SW/HW

Quality

Support & Community

www.silabs.com/IoT

www.silabs.com/simplicity

www.silabs.com/quality

www.silabs.com/community

Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software imple-

menters using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each

speciﬁc device, and “Typical” parameters provided can and do vary in diﬀerent applications. Application examples described herein are for illustrative purposes only. Silicon

Labs reserves the right to make changes without further notice to the product information, speciﬁcations, and descriptions herein, and does not give warranties as to the

accuracy or completeness of the included information. Without prior notiﬁcation, Silicon Labs may update product ﬁrmware during the manufacturing process for security or

reliability reasons. Such changes will not alter the speciﬁcations or the performance of the product. Silicon Labs shall have no liability for the consequences of use of the infor-

mation supplied in this document. This document does not imply or expressly grant any license to design or fabricate any integrated circuits. The products are not designed or

authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required or Life Support Systems without the speciﬁc written consent

of Silicon Labs. A “Life Support System” is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in

signiﬁcant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used

in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs disclaims

all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.

Note: This content may contain oﬀensive terminology that is now obsolete. Silicon Labs is replacing these terms with inclusive language wherever possible. For more

information, visit www.silabs.com/about-us/inclusive-lexicon-project

Trademark Information

®

Silicon Laboratories Inc. , Silicon Laboratories , Silicon Labs , SiLabs and the Silicon Labs logo , Bluegiga , Bluegiga Logo , EFM , EFM32 , EFR, Ember , Energy Micro, Energy

®

Micro logo and combinations thereof, “the world’s most energy friendly microcontrollers”, Redpine Signals , WiSeConnect , n-Link, ThreadArch , EZLink , EZRadio , EZRadioPRO ,

®

Gecko , Gecko OS, Gecko OS Studio, Precision32 , Simplicity Studio , Telegesis, the Telegesis Logo , USBXpress , Zentri, the Zentri logo and Zentri DMS, Z-Wave , and others

are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered

trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance. All other products or brand names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

www.silabs.com