转到网站首页
转为中文步骤：
1、请用电脑端360浏览器打开本页地址，如您电脑未安装360浏览器，请点这里下载;
2、点击360浏览器右上角的翻译插件，如右图红圈中所示:
3、点击所弹出窗口里的右下角的按钮 “翻译当前网页”;
4、弹窗提示翻译完毕后关闭弹窗即可；
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
IDT5V41066  
Recommended Applications  
Features/Benefits  
4 Output synthesizer for PCIe Gen1/2  
• 20-pin TSSOP package; small board footprint  
• Spread-spectrum capable; reduces EMI  
General Description  
• Outputs can be terminated to LVDS; can drive a wider  
variety of devices  
The IDT5V41066 is a PCIe Gen2 compliant  
spread-spectrum-capable clock generator. The device has  
4 differential HCSL outputs and can be used in  
communication or embedded systems to subtantially  
reduce electro-magnetic interference (EMI). The spread  
amount and output frequency are selectable via select pins.  
• Power down pin; greater system power management  
• OE control pin; greater system power management  
• Spread% and frequency pin selection; no software  
required to configure device  
• Industrial temperature range available; supports  
demanding embedded applications  
Output Features  
• For PCIe Gen3 applications, see the 5V41236  
• 4 - 0.7V current mode differential HCSL output pairs  
Key Specifications  
• Cycle-to-cycle jitter < 100 ps  
• Output-to-output skew < 50 ps  
• PCIe Gen2 phase jitter < 3.0ps RMS  
Block Diagram  
VDD  
PD  
OE  
2
Spread  
Spectrum/  
Output  
Spread  
Spectrum  
Circuitry  
3
SEL[2:0]  
X1  
clock  
selection  
CLKOUTA  
CLKOUTA  
CLKOUTB  
25 MHz  
crystal or  
clock  
Clock  
Oscillator  
PLL Clock  
Synthesis  
CLKOUTB  
CLKOUTC  
X2  
CLKOUTC  
CLKOUTD  
Optional tuning crystal  
capacitors  
CLKOUTD  
2
Rr(IREF)  
GND  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
1
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Pin Assignment  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CLKA  
VDDXD  
S0  
CLKA  
S1  
S2  
X1  
X2  
PD  
3
CLKB  
4
CLKB  
5
GNDODA  
VDDODA  
CLKC  
6
7
OE  
GNDXD  
IREF  
8
CLKC  
9
CLKD  
10  
CLKD  
20-pin (173 mil) TSSOP  
Spread Spectrum Selection Table  
S2 S1 S0 Spread% Spread Type  
Output  
Frequency  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.5  
-1.0  
-1.5  
Down  
Down  
Down  
100  
100  
100  
No Spread Not Applicable  
100  
-0.5  
-1.0  
-1.5  
Down  
Down  
Down  
200  
200  
200  
No Spread Not Applicable  
200  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
2
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Pin Descriptions  
Pin  
Pin  
Name  
Pin  
Type  
Pin Description  
1
2
3
4
5
6
7
8
VDDXD  
S0  
Power Connect to +3.3 V digital supply.  
Input Spread spectrum select pin #0. See table above. Internal pull-up resistor.  
Input Spread spectrum select pin #1. See table above Internal pull-up resistor.  
Input Spread spectrum select pin #2. See table above. Internal pull-up resistor.  
Input Crystal connection. Connect to a fundamental mode crystal or clock input.  
Output Crystal connection. Connect to a fundamental mode crystal or leave open.  
Input Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor.  
S1  
S2  
X1  
X2  
PD  
OE  
Input Provides output on, tri-states output (High = enable outputs; Low = disable outputs).  
Internal pull-up resistor.  
9
GND  
IREF  
Power Connect to digital ground.  
10  
11  
12  
13  
14  
15  
16  
Output Precision resistor attached to this pin is connected to the internal current reference.  
Output Selectable 100/200 MHz spread spectrum differential Complement output clock D.  
Output Selectable 100/200 MHz spread spectrum differential True output clock D.  
Output Selectable 100/200 MHz spread spectrum differential Complement output clock C.  
Output Selectable 100/200 MHz spread spectrum differential True output clock C.  
Power Connect to +3.3 V analog supply.  
CLKD  
CLKD  
CLKC  
CLKC  
VDDODA  
GND  
Power Connect to analog ground.  
17  
18  
19  
20  
CLKB  
CLKB  
CLKA  
CLKA  
Output Selectable 100/200 MHz spread spectrum differential Complement output clock B.  
Output Selectable 100/200 MHz spread spectrum differential True output clock B.  
Output Selectable 100/200 MHz spread spectrum differential Complement output clock A.  
Output Selectable 100/200 MHz spread spectrum differential True output clock A.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
3
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Application Information  
Decoupling Capacitors  
Load Resistors RL  
As with any high-performance mixed-signal IC, the  
IDT5V41066 must be isolated from system power supply  
noise to perform optimally.  
Since the clock outputs are open source outputs, 50 ohm  
external resistors to ground are to be connected at each  
clock output.  
Decoupling capacitors of 0.01µF must be connected  
between each VDD and the PCB ground plane.  
Output Termination  
The PCI-Express differential clock outputs of the  
IDT5V41066 are open source drivers and require an  
external series resistor and a resistor to ground. These  
resistor values and their allowable locations are shown in  
detail in the PCI-Express Layout Guidelines section.  
PCB Layout Recommendations  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
Each 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible. No vias should be used between decoupling  
capacitor and VDD pin. The PCB trace to VDD pin should  
be kept as short as possible, as should the PCB trace to the  
ground via. Distance of the ferrite bead and bulk decoupling  
from the device is less critical.  
The IDT5V41066 can also be configured for LVDS  
compatible voltage levels. See the LVDS Compatible  
Layout Guidelines section.  
2) An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers (the ferrite bead and bulk decoupling capacitor can be  
mounted on the back). Other signal traces should be routed  
away from the IDT5V41066.  
This includes signal traces just underneath the device, or on  
layers adjacent to the ground plane layer used by the device.  
External Components  
A minimum number of external components are required for  
proper operation. Decoupling capacitors of 0.01 μF should  
be connected between VDD and GND pairs (1,9 and 15,16)  
as close to the device as possible.  
On chip capacitors- Crystal capacitors should be  
connected from pins X1 to ground and X2 to ground to  
optimize the initial accuracy. The value (in pf) of these  
crystal caps equal (C -12)*2 in this equation, C =crystal  
L
L
load capacitance in pf. For example, for a crystal with a 16  
pF load cap, each external crystal cap would be 8 pF.  
[(16-12)x2]=8.  
Current Reference Source Rr (Iref)  
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω  
(1%), providing IREF of 2.32 mA, output current (I ) is  
OH  
equal to 6*IREF.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
4
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Output Structures  
6*IREF  
IREF  
=2.3 mA  
See Output Termination  
Sections - Pages 3 ~ 5  
RR 475  
Ω
General PCB Layout Recommendations  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
1. Each 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible.  
2. No vias should be used between decoupling capacitor  
and VDD pin.  
3. The PCB trace to VDD pin should be kept as short as  
possible, as should the PCB trace to the ground via.  
Distance of the ferrite bead and bulk decoupling from the  
device is less critical.  
4. An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers (any ferrite beads and bulk decoupling capacitors can  
be mounted on the back). Other signal traces should be  
routed away from the IDT5V41066.This includes signal  
traces just underneath the device, or on layers adjacent to  
the ground plane layer used by the device.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
5
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Layout Guidelines  
SRC Reference Clock  
Common Recommendations for Differential Routing  
L1 length, route as non-coupled 50ohm trace  
L2 length, route as non-coupled 50ohm trace  
L3 length, route as non-coupled 50ohm trace  
Dimension or Value  
0.5 max  
0.2 max  
0.2 max  
33  
Unit Figure  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
Rs  
Rt  
49.9  
Down Device Differential Routing  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
2 min to 16 max  
1.8 min to 14.4 max  
inch  
inch  
1
1
Differential Routing to PCI Express Connector  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
0.25 to 14 max  
0.225 min to 12.6 max  
inch  
inch  
2
2
Figure 1: Down Device Routing  
L2  
L1  
Rs  
Rs  
L4  
L4'  
L2'  
L1'  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Down Device  
REF_CLK Input  
L3' L3  
Figure 2: PCI Express Connector Routing  
L2  
L1  
Rs  
L4  
L4'  
L2'  
L1'  
Rs  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Add-in Board  
REF_CLK Input  
L3' L3  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
6
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Alternative Termination for LVDS and other Common Differential Signals (figure 3)  
Vdiff  
0.45v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
R2a = R2b = R2  
Figure 3  
L2  
L1  
R3  
R4  
R1a  
R1b  
L4  
L4'  
L2'  
L1'  
R2a  
R2b  
HCSL Output Buffer  
Down Device  
REF_CLK Input  
L3'  
L3  
Cable Connected AC Coupled Application (figure 4)  
Component  
Value  
Note  
R5a, R5b  
R6a, R6b  
Cc  
8.2K 5%  
1K 5%  
0.1 µF  
Vcm  
0.350 volts  
Figure 4  
3.3 Volts  
R5a  
R5b  
Cc  
L4  
L4'  
Cc  
R6a  
R6b  
PCIe Device  
REF_CLK Input  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
7
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Typical PCI-Express (HCSL) Waveform  
700 mV  
0
500 ps  
500 ps  
tOR  
tOF  
0.52 V  
0.175 V  
0.52 V  
0.175 V  
Typical LVDS Waveform  
1325 mV  
1000 mV  
500 ps  
500 ps  
tOR  
tOF  
1250 mV  
1150 mV  
1250 mV  
1150 mV  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
8
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the IDT5V41066. These ratings are stress  
ratings only. Functional operation of the device at these or any other conditions above those indicated in the  
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for  
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended  
operating temperature range.  
Item  
Rating  
Supply Voltage, VDD, VDDA  
5.5 V  
All Inputs and Outputs  
-0.5 V to VDD+0.5 V  
0 to +70° C  
Ambient Operating Temperature (commercial)  
Ambient Operating Temperature (industrial)  
Storage Temperature  
-40 to +85° C  
-65 to +150° C  
125°C  
Junction Temperature  
Soldering Temperature  
260°C  
ESD Protection (Input)  
2000 V min. (HBM)  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85° C  
Parameter  
Symbol  
Conditions  
Min.  
3.135  
2.2  
Typ.  
3.3  
Max.  
3.465  
Units  
Supply Voltage  
V
1
Input High Voltage  
V
VDD +0.3  
V
IH  
1
Input Low Voltage  
Input Leakage Current  
V
I
VSS-0.3  
-5  
0.8  
5
V
IL  
2
0 < Vin < VDD  
μA  
mA  
mA  
μA  
pF  
pF  
pF  
nH  
kΩ  
kΩ  
IL  
Operating Supply Current  
@100 MHz  
I
R =33Ω, R =50Ω, C =2 pF  
115  
42  
125  
48  
500  
7
DD  
S
P
L
I
OE =Low  
DDOE  
I
No load, PD =Low  
350  
DDPD  
Input Capacitance  
Output Capacitance  
X1, X2 Capacitance  
Pin Inductance  
C
Input pin capacitance  
Output pin capacitance  
IN  
C
L
6
OUT  
C
5
INX  
PIN  
5
Output Impedance  
Pull-up Resistance  
Zo  
CLK outputs  
3.0  
R
OE, SEL, PD pins  
110  
PUP  
1. Single edge is monotonic when transitioning through region.  
2. Inputs with pull-ups/-downs are not included.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
9
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
AC Electrical Characteristics - CLKOUT (A:D)  
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85° C  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ.  
25  
Max.  
Units  
MHz  
MHz  
MHz  
mV  
mV  
mV  
mV  
ps  
Output Frequency  
HCSL termination  
25  
25  
200  
100  
850  
LVDS termination  
HCSL  
1,2  
Output High Voltage  
V
OH  
1,2  
Output Low Voltage  
V
HCSL  
-150  
250  
OL  
1,2  
Crossing Point Voltage  
Crossing Point Voltage  
Absolute  
550  
140  
100  
1,2,4  
Variation over all edges  
1,3  
Jitter, Cycle-to-Cycle  
Frequency Synthesis Error  
Modulation Frequency  
All outputs  
0
ppm  
kHz  
ps  
Spread spectrum  
30  
32.9  
33  
700  
700  
125  
50  
1,2  
Rise Time  
t
From 0.175 V to 0.525 V  
From 0.525 V to 0.175 V  
175  
175  
OR  
1,2  
Fall Time  
t
ps  
OF  
1,2  
Rise/Fall Time Variation  
ps  
Output to Output Skew  
ps  
1,3  
Duty Cycle  
45  
7
55  
%
5
Output Enable Time  
All outputs  
50  
50  
100  
100  
1.8  
30  
ns  
5
Output Disable Time  
All outputs  
ns  
Stabilization Time  
t
From power-up VDD=3.3 V  
ms  
STABLE  
Spread Spectrum Transition  
Time  
t
Stabilization time after spread  
spectrum changes  
ms  
SPREAD  
1
Test setup is R =33Ω, R =50Ω with C =2 pF, Rr = 475Ω (1%).  
S
P
L
2
3
4
5
Measurement taken from a single-ended waveform.  
Measurement taken from a differential waveform.  
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.  
CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its  
PD= low.  
Electrical Characteristics - Differential Phase Jitter  
Parameter  
Symbol  
Conditions  
Min Typ Max  
Units  
ps (p-p)  
Notes  
1,2,3  
1,2,3  
1,2,3  
t
PCIe Gen1  
30  
0.76  
2.0  
86  
3
jphasePLL  
Jitter, Phase  
t
PCIe Gen2, 10 kHz < f < 1.5 MHz  
ps (RMS)  
ps (RMS)  
jphaseLO  
t
PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz)  
3.1  
jphaseHIGH  
Note 1. Guaranteed by design and characterization, not 100% tested in production.  
Note 2. See http://www.pcisig.com for complete specs.  
Note 3: Applies to 100MHz, spread off and 0.5% down spread only.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
10  
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
θ
Still air  
93  
78  
65  
20  
° C/W  
° C/W  
° C/W  
° C/W  
JA  
θ
1 m/s air flow  
3 m/s air flow  
JA  
θ
JA  
Thermal Resistance Junction to Case  
θ
JC  
Marking Diagram (5V41066PGG)  
Marking Diagram (5V41066PGGI)  
20  
11  
20  
11  
IDT5V410  
66PGGI  
IDT5V410  
66PGG  
#YYWW$  
#YYWW$  
1
10  
1
10  
Notes:  
1. Line 1 and 2: IDT part number.  
2. Line 3: # – Die revision; YYWW – Date code; $ – Assembly location.  
3. “G” after the two-letter package code designates RoHS compliant package.  
4. “I” at the end of part number indicates industrial temperature range.  
5. Bottom marking: country of origin if not USA.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
11  
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body)  
Package dimensions are kept current with JEDEC Publication No. 95, MO-153  
Millimeters  
Inches*  
20  
Symbol  
Min  
Max  
1.20  
0.15  
1.05  
0.30  
0.20  
6.60  
Min  
Max  
A
A1  
A2  
b
0.047  
0.006  
0.041  
0.012  
0.05  
0.80  
0.19  
0.09  
6.40  
0.002  
0.032  
0.007  
0.0035 0.008  
0.252 0.260  
0.252 BASIC  
0.169 0.177  
0.0256 Basic  
E1  
E
INDEX  
AREA  
c
D
E
E1  
e
6.40 BASIC  
4.30  
1
2
4.50  
0.65 Basic  
D
L
a
0.45  
0°  
0.75  
8°  
0.018  
0°  
0.030  
8°  
aaa  
--  
0.10  
--  
0.004  
A
A2  
A1  
c
- C -  
e
SEATING  
PLANE  
b
L
aaa C  
Ordering Information  
Part / Order Number  
Marking  
see page 10  
Shipping Packaging  
Tubes  
Package  
Temperature  
0 to +70° C  
0 to +70° C  
-40 to +85° C  
-40 to +85° C  
5V41066PGG  
5V41066PGG8  
5V41066PGGI  
5V41066PGGI8  
20-pin TSSOP  
20-pin TSSOP  
20-pin TSSOP  
20-pin TSSOP  
Tape and Reel  
Tubes  
Tape and Reel  
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
12  
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Revision History  
Rev. Originator  
Date  
Description of Change  
A
B
C
RDW  
RDW  
RDW  
01/20/10 New datasheet; Preliminary initial release.  
04/27/10 Updated electrical tables per char; released to final.  
07/19/10 1. Updated title and general decription  
2. Updated cycle-to-cycle jitter spec from 125 to 100 ps.  
D
RDW  
11/21/11 1. Changed title to “4 Output PCIe GEN1/2 Synthesizer”  
2. Added note to Features section: “For PCIe Gen3 applications, see 5V41236”  
3. Updated Differential Phase Jitter table.  
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
13  
IDT5V41066 REV D 112211  
IDT5V41066  
4 OUTPUT PCIE GEN1/2 SYNTHESIZER  
IMPORTANT NOTICE AND DISCLAIMER  
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL  
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING  
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND  
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,  
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A  
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible  
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)  
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These  
resources are subject to change without notice. Renesas grants you permission to use these resources only for  
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly  
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.  
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,  
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject  
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources  
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.  
('LVFODLPHUꢀRev.1.0 Mar 2020)  
Corporate Headquarters  
TOYOSU FORESIA, 3-2-24 Toyosu,  
Koto-ku, Tokyo 135-0061, Japan  
Contact Information  
For further information on a product, technology, the most  
up-to-date version of a document, or your nearest sales  
www.renesas.com  
office, please visit:  
www.renesas.com/contact/  
Trademarks  
Renesas and the Renesas logo are trademarks of Renesas  
Electronics Corporation. All trademarks and registered  
trademarks are the property of their respective owners.  
© 202ꢀ Renesas Electronics Corporation. All rights reserved.