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PCI-EXPRESS GEN1 CLOCK SOURCE  
ICS557-01  
Description  
Features  
TM  
The ICS557-01 is a clock chip designed for use in  
PCI-Express Cards as a clock source. It provides a pair of  
differential outputs at 100 MHz in a small 8-pin SOIC  
package.  
• Supports PCI-Express HCSL Outputs  
0.7 V current mode differential pair  
• Supports LVDS Output Levels  
• Packaged in 8-pin SOIC  
• RoHS 5 (green) or RoHS 6 (green and lead free)  
Using IDT’s patented Phase-Locked Loop (PLL)  
compliant packaging  
techniques, the device takes a 25 MHz crystal input and  
produces HCSL (Host Clock Signal Level) differential  
outputs at 100 MHz clock frequency. LVDS signal levels can  
also be supported via an alternative termination scheme.  
• Operating voltage of 3.3 V  
• Low power consumption  
• Input frequency of 25 MHz  
• Short term jitter 100 ps (peak-to-peak)  
• Output Enable via pin selection  
• Industrial temperature range available  
• For PCIe Gen2 applications, see the 5V41064  
• For PCIe Gen3 applications, see the 5V41234  
Block Diagram  
VDD  
CLK  
Phase Lock  
Loop  
CLK  
X1  
X2  
Clock  
Buffer/  
Crystal  
Oscillator  
25 MHz  
crystal /clock  
Crystal Tuning Capacitors  
RR(IREF)  
GND  
OE  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
1
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
Pin Assignment  
1
2
3
4
8
7
6
5
VDD  
CLK  
CLK  
IREF  
OE  
X1  
X2  
GND  
8 Pi n (150 mi l ) SOIC  
Pin Descriptions  
Pin  
Number  
Pin  
Name  
Pin  
Type  
Pin Description  
1
OE  
Input Output Enable signal  
(H = outputs are enabled, L = outputs are disabled/tristated).  
Internal pull-up resistor.  
2
3
X1  
X2  
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.  
XO  
Crystal Connection. Connect to a parallel mode crystal.  
Leave floating if clock input.  
4
5
GND  
IREF  
Power Connect to ground.  
Output A 475Ω precision resistor connected between this pin and ground  
establishes the external reference current.  
6
7
8
CLK  
CLK  
VDD  
Output HCSL differential complementary clock output.  
Output HCSL differential clock output.  
Power Connect to +3.3 V.  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
2
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
Applications Information  
External Components  
A minimum number of external components are required for  
proper operation.  
Output Structures  
6*IREF  
IREF  
=2.3 mA  
Decoupling Capacitors  
Decoupling capacitors of 0.01 μF should be connected  
between VDD and the ground plane (pin 4) as close to the  
VDD pin as possible. Do not share ground vias between  
components. Route power from power source through the  
capacitor pad and then into IDT pin.  
Crystal  
See Output Termination  
Sections - Pages 3 ~ 5  
A 25 MHz fundamental mode parallel resonant crystal with  
RR 475  
W
C = 16 pF should be used. This crystal must have less than  
L
300 ppm of error across temperature in order for the  
ICS557-01 to meet PCI Express specifications.  
General PCB Layout Recommendations  
Crystal Capacitors  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
Crystal capacitors are connected from pins X1 to ground  
and X2 to ground to optimize the accuracy of the output  
frequency.  
1. Each 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible.  
C = Crystal’s load capacitance in pF  
L
Crystal Capacitors (pF) = (C - 8) * 2  
L
2. No vias should be used between decoupling capacitor  
and VDD pin.  
For example, for a crystal with a 16 pF load cap, each  
external crystal cap would be 16 pF. (16-8)*2=16.  
3. The PCB trace to VDD pin should be kept as short as  
possible, as should the PCB trace to the ground via.  
Distance of the ferrite bead and bulk decoupling from the  
device is less critical.  
Current Source (Iref) Reference Resistor - R  
R
If board target trace impedance (Z) is 50Ω, then R = 475Ω  
(1%), providing IREF of 2.32 mA. The output current (I ) is  
R
OH  
4. An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers (any ferrite beads and bulk decoupling capacitors can  
be mounted on the back). Other signal traces should be  
routed away from the ICS557-01.This includes signal traces  
just underneath the device, or on layers adjacent to the  
ground plane layer used by the device.  
equal to 6*IREF.  
Output Termination  
The PCI-Express differential clock outputs of the ICS557-01  
are open source drivers and require an external series  
resistor and a resistor to ground. These resistor values and  
their allowable locations are shown in detail in the  
PCI-Express Layout Guidelines section.  
The ICS557-01can also be configured for LVDS compatible  
voltage levels. See the LVDS Compatible Layout Guidelines  
section  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
3
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
PCI-Express Layout Guidelines  
Common Recommendations for Differential Routing  
Dimension or Value Unit Figure Notes  
L1 length, Route as non-coupled 50 ohm trace.  
L2 length, Route as non-coupled 50 ohm trace.  
L3 length, Route as non-coupled 50 ohm trace.  
RS  
RT  
0.5 max  
0.2 max  
0.2 max  
33  
inch  
inch  
inch  
ohm  
ohm  
1,2  
1,2  
1,2  
1,2  
1,2  
49.9  
Differential Routing on a Single PCB  
Dimension or Value Unit Figure Notes  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
2 min to 16 max  
1.8 min to 14.4 max  
inch  
inch  
1
1
Differential Routing to a PCI Express Connector  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
Dimension or Value Unit Figure Notes  
0.25 to 14 max  
inch  
2
2
0.225 min to 12.6 max inch  
Figure 1: PCI-Express Device Routing  
L1  
L2  
L4  
RS  
RS  
L4’  
L1’  
L2’  
RT  
RT  
PCI-Express  
Load or  
Connector  
ICS557-01  
Output  
L3’ L3  
Clock  
Typical PCI-Express (HCSL) Waveform  
700 mV  
0
500 ps  
500 ps  
tOR  
tOF  
0.52 V  
0.175 V  
0.52 V  
0.175 V  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
4
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
LVDS Compatible Layout Guidelines  
Alternative Termination for LVDS and other Common Differential Signals  
Vdiff  
0.45v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
R2a = R2b = R2  
Figure: LVDS Device Routing  
L2  
L1  
R3  
R4  
R1a  
R1b  
L4  
L4'  
L2'  
L1'  
R2a  
R2b  
HCSL Output Buffer  
Down Device  
REF_CLK Input  
L3'  
L3  
Typical LVDS Waveform  
1325 mV  
1000 mV  
500 ps  
500 ps  
tOR  
tOF  
1250 mV  
1150 mV  
1250 mV  
1150 mV  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
5
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the ICS557-01. These ratings are stress  
ratings only. Functional operation of the device at these or any other conditions above those indicated in the  
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for  
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended  
operating temperature range.  
Item  
Rating  
Supply Voltage, VDD, VDDA  
5.5 V  
All Inputs and Outputs  
-0.5 V to VDD+0.5 V  
0 to +70° C  
Ambient Operating Temperature (commercial)  
Ambient Operating Temperature (industrial)  
Storage Temperature  
-40 to +85° C  
-65 to +150° C  
125°C  
Junction Temperature  
Soldering Temperature  
260°C  
ESD Protection (Input)  
2000 V min. (HBM)  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85° C  
Parameter  
Symbol  
Conditions  
Min.  
3.135  
2.0  
Typ.  
Max.  
3.465  
Units  
Supply Voltage  
V
1
Input High Voltage  
V
VDD +0.3  
V
IH  
1
Input Low Voltage  
Input Leakage Current  
V
I
VSS-0.3  
-5  
0.8  
5
V
IL  
2
0 < Vin < VDD  
μA  
mA  
mA  
pF  
pF  
nH  
kΩ  
kΩ  
IL  
Operating Supply Current  
I
With 50Ω and 2 pF load  
OE =Low  
55  
35  
7
DD  
I
DDOE  
Input Capacitance  
Output Capacitance  
Pin Inductance  
C
Input pin capacitance  
Output pin capacitance  
IN  
C
6
OUT  
L
5
PIN  
Output Resistance  
Pull-up Resistor  
Rout  
CLK outputs  
OE  
3.0  
R
60  
PUP  
1 Single edge is monotonic when transitioning through region.  
2 Inputs with pull-ups/-downs are not included.  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
6
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
AC Electrical Characteristics - CLK/CLK  
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85° C  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ.  
25  
Max.  
Units  
MHz  
MHz  
mV  
Output Frequency  
Output High Voltage  
100  
700  
0
1,2  
1,2  
V
660  
-150  
250  
850  
27  
OH  
Output Low Voltage  
Crossing Point  
V
mV  
OL  
Absolute  
350  
550  
mV  
1,2  
Voltage  
Crossing Point  
Voltage  
Variation over all edges  
140  
mV  
1,2,4  
1,3  
Jitter, Cycle-to-Cycle  
80  
ps  
ps  
ps  
ps  
1,2  
Rise Time  
t
From 0.175 V to 0.525 V  
From 0.525 V to 0.175 V  
175  
175  
332  
344  
700  
700  
125  
OR  
1,2  
Fall Time  
t
OF  
Rise/Fall Time  
1,2  
Variation  
1,3  
Duty Cycle  
45  
55  
%
µs  
µs  
ms  
5
Output Enable Time  
Output Disable Time  
Stabilization Time  
All outputs  
30  
30  
5
All outputs  
t
From power-up VDD=3.3 V  
3.0  
STABLE  
1
Test setup is R =50 ohms with 2 pF, R = 475Ω (1%).  
L
R
2
3
4
5
Measurement taken from a single-ended waveform.  
Measurement taken from a differential waveform.  
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.  
CLKOUT pins are tri-stated when OE is low asserted. CLKOUT is driven differential when OE is high.  
Thermal Characteristics (8-pin SOIC)  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
θ
θ
θ
θ
Still air  
150  
140  
120  
40  
° C/W  
° C/W  
° C/W  
° C/W  
JA  
JA  
JA  
JC  
1 m/s air flow  
3 m/s air flow  
Thermal Resistance Junction to Case  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
7
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
Marking Diagram (ICS557M-01LF)  
Marking Diagram (ICS557MI-01LF)  
8
5
8
5
557M01LF  
LOT  
YYWW  
557MI01L  
LOT  
YYWW  
1
4
1
4
Notes:  
1. “LOT” is the lot code.  
2. YYWW is the last two digits of the year, and the week number that the part was assembled.  
3. “L” or “LF” designates Pb (lead) free packaging.  
4. “I” denotes industrial temperature.  
5. Bottom marking: (origin). Origin = country of origin if not USA.  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
8
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Inches*  
Symbol  
Min  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
Max  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
Min  
Max  
.0688  
.0098  
.020  
8
A
A1  
B
C
D
E
e
.0532  
.0040  
.013  
.0075  
.1890  
.1497  
.0098  
.1968  
.1574  
E
H
INDEX  
AREA  
1.27 BASIC  
0.050 BASIC  
H
h
5.80  
0.25  
0.40  
0°  
6.20  
0.50  
1.27  
8°  
.2284  
.010  
.016  
0°  
.2440  
.020  
.050  
8°  
1
2
L
D
a
*For reference only. Controlling dimensions in mm.  
A
h x 45  
A1  
C
- C -  
e
SEATING  
PLANE  
B
L
.10 (.004)  
C
Ordering Information  
Part / Order Number  
557M-01LF  
Marking  
See Page 8  
Shipping Packaging  
Tubes  
Package  
8-pin SOIC  
8-pin SOIC  
8-pin SOIC  
8-pin SOIC  
Temperature  
0 to +70° C  
0 to +70° C  
-40 to +85° C  
-40 to +85° C  
557M-01LFT  
Tape and Reel  
Tubes  
557MI-01LF  
557MI-01LFT  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT® PCI-EXPRESS GEN1 CLOCK SOURCE  
9
ICS557-01  
REV P 072512  
ICS557-01  
PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE  
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