6V31021--Datasheet/数据表在线中文翻译

DATASHEET

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021

General Description

Features/Benefits

The IDT6V31021 is a 4-output low- power differential buffer.

Each output has its own OE# pin. It has a maximum

operating frequency of 167 MHz and supports all SERDES

clock frequencies for Freescale QorIQ CPUs.

• Low power differential outputs; power efficient

• Power down mode when all OE# are high; reduces

system standby power

• Industrial temperature range; can be used in demanding

environments

• 20-pin MLF; space savings

Recommended Application

PCIe Gen1/2/3 or Ethernet Fanout Buffer,or any application

requiring low additive phase jitter.

Key Specifications

• Output cycle-cycle jitter <15ps additive

• Output to Output skew: <50ps

• PCIe Gen3 addtive phasejitter <0.3ps rms

• 10.3125G/64 additive phase jitter <100fs rms

Output Features

• 4 - low power differential output pairss

• Individual OE# control of each output pair

Block Diagram

OE#(3:0)

STOP

DIF_INT

DIF_INC

DIF_LPR(3:0)

LOGIC

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

Pin Configuration

20 19 18 17 16

VDDA 1

GNDA 2

15 VDD_IO

14 GND

OE3# 3

DIF3C_LPR 4

DIF3T_LPR 5

13 OE1#

12 DIF1T_LPR

11 DIF1C_LPR

6V31021

9 10

20-pin MLF

Power Connections

Pin Number (MLF)

Description

VDD

6,15

GND

7,14

VDD_IO for DIF(3:0)

3.3V Analog VDD & GND

Terminations

Zo – 17 = Rs (ohms), where Zo is the single-ended intrinsic impedance of the board

transmission line. Single-ended intrinsic impedance is ½ that of the differential

impedance.

Single Ended

Impedance

(Zo)

tolerance 2% tolerance

Notes

42.5

24 or 27

33.2

27.4

24.9

In general, 5% resistors

may be used. All values are

in ohms.

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

Pin Descriptions

PIN #

PIN NAME

VDDA

GNDA

PIN TYPE

PWR

GND

DESCRIPTION

3.3V Power for the Analog Core

Ground for the Analog Core

Output Enable for DIF3 output. Control is as follows:

0 = enabled, 1 = Low-Low

OE3#

DIF3C_LPR

DIF3T_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

VDD_IO

GND

PWR

GND

Power supply for low power differential outputs, nominal 1.05V to 3.3V

Ground pin

DIF2C_LPR

DIF2T_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

Output Enable for DIF2 output. Control is as follows:

0 = enabled, 1 = Low-Low

OE2#

DIF1C_LPR

DIF1T_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

Output Enable for DIF1 output. Control is as follows:

0 = enabled, 1 = Low-Low

OE1#

GND

VDD_IO

GND

PWR

Ground pin

Power supply for low power differential outputs, nominal 1.05V to 3.3V

DIF0C_LPR

DIF0T_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

Output Enable for DIF0 output. Control is as follows:

0 = enabled, 1 = Low-Low

OE0#

DIF_INC

DIF_INT

Complement side of differential input clock

True side of differential input clock

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the IDT6V31021. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over

the recommended operating temperature range.

PARAMETER

SYMBOL

VDDA

VDD_IO

CONDITIONS

Core Supply Voltage

Low-Voltage Differential I/O

MIN

0.99

TYP

MAX

4.6

3.8

UNITS

Notes

1,7

Maximum Supply Voltage

Maximum Input Voltage

3.3V LVCMOS Inputs

Any Input

4.6

1,7,8

V_IH

V_IL

Minimum Input Voltage

Ambient Operating Temp

Storage Temperature

Input ESD protection

Vss - 0.5

-40

1,7

T_ambIND

ESD prot

Industrial Range

Human Body Model

°C

^°C

-65

2000

150

1,7

Electrical Characteristics–Input/Supply/Common Output Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Supply Voltage

VDDA

Supply Voltage

3.000

3.3

3.600

Low-Voltage Differential I/O

Supply

Supply Voltage

VDDxxx_IO

0.99

1.05-3.3

3.600

Input High Voltage

V_IHSE

V_ILSE

Single-ended inputs

V_DD+ 0.3

0.8

Input Low Voltage

Differential Input High

Voltage

Differential Input Low

Voltage

Single-ended inputs

Differential inputs

(single-ended measurement)

Differential inputs

V_SS- 0.3

V_IHDIF

V_ILDIF

600

1.15

300

_SS- 0.3

(single-ended measurement)

Input Slew Rate - DIF_IN

Input Leakage Current

dv/dt

I_IN

Measured differentially

V_IN= V_{DD ,}V_IN= GND

0.4

-5

V/ns

I_{DD_3.3V}

VDDA supply current

VDD_IO supply @ fOP =

133MHz

VDDA supply current, Input

stopped, OE# pins all high

VDD_IO supply, Input

stopped, OE# pins all high

V_DD= 3.3 V

Operating Supply Current

I_{DD_IO_133M}

I_{DD_SB_3.3V}

I_{DD_SBIO}

500

100

750

150

Power Down Current

(All OE# pins High)

Input Frequency

Pin Inductance

F_i

167

MHz

L_pin

C_IN

Logic Inputs

1.5

Input Capacitance

C_OUT

Output pin capacitance

Number of clocks to enable

or disable output from

assertion/deassertion of OE#

OE# latency

(at least one OE# is low)

T_OE#LAT

periods

Delay from assertion of first

OE# to first clock out

(assumes input clock running

and device in power down

state))

Clock stabilization time

(from all OE# high to first

OE# low).

T_STAB

150

Output enable after

OE# de-assertion

Tdrive_OE#

T_DROE#

Tfall_OE#

Trise_OE#

T_FALL

T_RISE

Fall/rise time of OE# inputs

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

AC Electrical Characteristics–DIF Low Power Differential Outputs

PARAMETER

Rising/Falling Edge Slew

Rate

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

t_SLR

Differential Measurement

1.5

2.2

V/ns

1,2

Slew Rate Variation

t_SLVAR

V_HIGH

Single-ended Measurement

Includes overshoot

783

-22

Maximum Output Voltage

Minimum Output Voltage

Differential Voltage Swing

Crossing Point Voltage

Crossing Point Variation

1150

V_LOW

Includes undershoot

-300

1200

250

V_SWING

V_XABS

Differential Measurement

Single-ended Measurement

Differential Measurement,

fIN<=133.33MHz

Differential Measurement,

Additive

336

550

140

1,3,4

1,3,5

V_XABSVAR

Duty Cycle Distortion

D_CYCDIS0

1.6

2.1

1,6

Additive Cycle-to-Cycle

Jitter

DIFJ_C2CADD

DIF[3:0] Skew

DIF_SKEW

t_PD

Differential Measurement

1, 11

Propagation Delay

Additive Phase Jitter -

PCIe Gen1

Additive Phase Jitter -

PCIe Gen2 High Band

Input to output Delay

2.5

3.3

3.8

Pk-Pk

t_{phase_addPCIG1}

t_{phase_addPCIG2HI}

t_{phase_addPCIG2LO}

1.5MHz < 22MHz

1.6

0.1

0.5

1,9

High Band is 1.5MHz to

Nyquist (50MHz)

0.3

0.8

ps rms

Additive Phase Jitter -

PCIe Gen2 Low Band

Low Band is 10KHz to

1.5MHz

Additive Phase Jitter -

PCIe Gen3

Additive Phase Jitter

161.1328125MHz =

10.3125G/64

2MHz - 4MHz,

2MHz - 5MHz

t_{phase_addPCIG3}

0.19

0.3

1,9

t_{phase_add10G/64}

12KHz to 100MHz

100

fs rms

1,10

Notes on Electrical Characteristics (all measurements use R_S=33ohms/C_L=2pF test load):

¹Guaranteed by design and characterization, not 100% tested in production.

²Slew rate measured through Vswing centered around differential zero

³Vxabs is defined as the voltage where CLK = CLK#

⁴Only applies to the differential rising edge (CLK rising and CLK# falling)

⁵Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of

CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

⁶This figure refers to the maximum distortion of the input wave form.

⁷Operation under these conditions is neither implied, nor guaranteed.

⁸Maximum input voltage is not to exceed maximum VDD

⁹The 6V31021has no PLL, so the part itself contributes very little jitter to the input clock. But this also means that the 9DBL411 cannot 'de-jitter' a noisy

input clock. Values calculated per PCI SIG and per Intel Clock Jitter tool version 1.6.6. For PCIe RMS figures, additive jitter is calculated by solving the

following equation: Additive jitter = SQRT[(total jittter)^2 - (input jitter)^2]

¹⁰Calculated from Agilent E5052A phase noise machine.

¹¹Mean value not including cycle-to-cycle jitter

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

Marking Diagram

6V310

21NLGI

YWW**$

Notes:

1. ‘**’ is the lot sequence.

2. ‘$’ is the mark code.

3. ‘YWW’ is the year and week that the part was assembled.

4. ‘G’ denotes RoHS compliant package.

5. ‘I’ denotes industrial temperature range.

6. Bottom marking: country of origin if not USA.

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

Package Outline and Package Dimensions (20-pin MLF)

(Ref)

N_D& N_E

Even

Seating Plane

(N_D-1)x

(Ref)

Index Area

(Typ)

If N_D& N_E

are Even

Anvil

Singulation

(N_E-1)x

(Ref)

-- or --

Sawn

Singulation

Top View

(Ref)

N_D& N_E

Odd

Thermal Base

0.08

Millimeters

Symbol

Min

Max

1.0

0.8

0.05

0.20 Reference

0.18 0.3

0.50 BASIC

4.00 x 4.00

D x E BASIC

D2 MIN./MAX.

E2 MIN./MAX.

L MIN./MAX.

2.00

0.45

2.25

0.65

Ordering Information

Part / Order Number Shipping Packaging

Package

20-pin MLF

Temperature

-40 to +85°C

6V31021NLGI

6V31021NLGI8

Trays

Tape and Reel

"G" after the two0letetr package code indicates Pb-Free configuration, RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes

no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No

other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications

such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT

does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

Revision History

Rev.

Originator Issue Date Description

Page #

0.1

RDW

10/18/2011 Initial Release

1. Updated General Description and Key Specifications

2. Added Mark Spec

RDW

12/12/2011 3. Moved to Final

1, 6

IDT® 4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

IDT6V31021 REV A 121311

IDT6V31021

4-OUTPUT LOW POWER FANOUT BUFFER FOR PCIE GEN3 AND 10G ETHERNET

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