5V41236--Datasheet/数据表在线中文翻译

DATASHEET

4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41236

Recommended Applications

Features/Benefits

Four output synthesizer for PCIe Gen1/2/3

• 20-TSSOP package; small board footprint

• Spread spectrum capable; reduces EMI

General Description

• Outputs can be terminated to LVDS; can drive a wider

variety of devices

The 5V41236 is a PCIe Gen1/2/3 compliant spread

spectrum capable clock generator. The device has 4

differential HCSL outputs and can be used in

communication or embedded systems to substantially

reduce electro-magnetic interference (EMI). The spread

amount and output frequency are selectable via select pins.

• Power-down pin; greater system power management

• OE control pin; greater system power management

• Spread% and frequency pin selection; no software

required to configure device

• Industrial temperature range available; supports

demanding embedded applications

Output Features

Key Specifications

• Four 0.7V current mode differential HCSL output pairs

• Cycle-to-cycle jitter < 100ps

• Output-to-output skew < 50ps

• PCIe Gen2 phase jitter < 3.0ps RMS

• PCIe Gen3 phase jitter < 1.0ps RMS

Block Diagram

VDD

Spread

Spectrum

Circuitry

Spectrum/

Output

SEL[2:0]

clock

selection

CLKOUTA

CLKOUTB

25 MHz

crystal or

clock

Clock

Oscillator

PLL Clock

Synthesis

CLKOUTB

CLKOUTC

CLKOUTD

Optional tuning crystal

capacitors

CLKOUTD

Rr(IREF)

GND

IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41236

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5V41236

4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Pin Assignment

CLKA

VDDXD

CLKA

CLKB

GNDODA

VDDODA

CLKC

GNDXD

IREF

CLKC

CLKD

20-pin (173 mil) TSSOP

Spread Spectrum Selection Table

S2 S1 S0 Spread% Spread Type

Output

Frequency

-0.5

-1.0

-1.5

Down

100

No Spread Not Applicable

100

-0.5

-1.0

-1.5

Down

200

No Spread Not Applicable

200

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Pin Descriptions

No.

Name

Type

Pin Description

VDDXD

Power Connect to +3.3V digital supply.

Input Spread spectrum select pin #0. See table above. Internal pull-up resistor.

Input Spread spectrum select pin #1. See table above Internal pull-up resistor.

Input Spread spectrum select pin #2. See table above. Internal pull-up resistor.

Input Crystal connection. Connect to a fundamental mode crystal or clock input.

Output Crystal connection. Connect to a fundamental mode crystal or leave open.

Input Powers down all PLLs and tri-states outputs when low. Internal pull-up resistor.

PD#

Input Provides output on, tri-states output (High = enable outputs; Low = disable outputs).

Internal pull-up resistor.

GND

IREF

Power Connect to digital ground.

Output Precision resistor attached to this pin is connected to the internal current reference.

Output Selectable 100/200MHz spread spectrum differential complement output clock D.

Output Selectable 100/200MHz spread spectrum differential true output clock D.

Output Selectable 100/200MHz spread spectrum differential complement output clock C.

Output Selectable 100/200MHz spread spectrum differential true output clock C.

Power Connect to +3.3V analog supply.

CLKD#

CLKD

CLKC#

CLKC

VDDODA

GND

Power Connect to analog ground.

CLKB#

CLKB

Output Selectable 100/200MHz spread spectrum differential complement output clock B.

Output Selectable 100/200MHz spread spectrum differential true output clock B.

Output Selectable 100/200MHz spread spectrum differential complement output clock A.

Output Selectable 100/200MHz spread spectrum differential true output clock A.

CLKA#

CLKA

IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41236

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5V41236

4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Application Information

Decoupling Capacitors

Load Resistors R_L

As with any high-performance mixed-signal IC, the

5V41236 must be isolated from system power supply noise

to perform optimally.

Since the clock outputs are open source outputs, 50

external resistors to ground are to be connected at each

clock output.

Decoupling capacitors of 0.01µF must be connected

between each VDD and the PCB ground plane.

Output Termination

The PCI-Express differential clock outputs of the 5V41236

are open source drivers and require an external series

resistor and a resistor to ground. These resistor values and

their allowable locations are shown in detail in the

PCI-Express Layout Guidelines section.

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between decoupling

capacitor and VDD pin. The PCB trace to VDD pin should

be kept as short as possible, as should the PCB trace to the

ground via. Distance of the ferrite bead and bulk decoupling

from the device is less critical.

The 5V41236 can also be configured for LVDS compatible

voltage levels. See the LVDS Compatible Layout

Guidelines section.

2) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (the ferrite bead and bulk decoupling capacitor can

be mounted on the back). Other signal traces should be

routed away from the 5V41236.

This includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the

device.

External Components

Aminimum number of external components are required for

proper operation. Decoupling capacitors of 0.01F should

be connected between VDD and GND pairs (1,9 and 15,16)

as close to the device as possible.

On chip capacitors- Crystal capacitors should be

connected from pins X1 to ground and X2 to ground to

optimize the initial accuracy. The value (in pf) of these

crystal caps equal (C - 12) × 2 in this equation, C = crystal

load capacitance in pf. For example, for a crystal with a

16pF load cap, each external crystal cap would be 8pF.

[(16 - 12) × 2] = 8.

Current Reference Source R_r(Iref)

If board target trace impedance (Z) is 50, then Rr = 475

(1%), providing IREF of 2.32mA, output current (I ) is

equal to 6 × IREF.

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Output Structures

6*IREF

IREF

=2.3 mA

See Output Termination

Sections - Pages 3 ~ 5

R_R475



General PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1. Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible.

2. No vias should be used between decoupling capacitor

and VDD pin.

3. The PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from the

device is less critical.

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (any ferrite beads and bulk decoupling capacitors can

be mounted on the back). Other signal traces should be

routed away from the 5V41236.This includes signal traces

just underneath the device, or on layers adjacent to the

ground plane layer used by the device.

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Layout Guidelines

SRC Reference Clock

Common Recommendations for Differential Routing

L1 length, route as non-coupled 50ohm trace

L2 length, route as non-coupled 50ohm trace

L3 length, route as non-coupled 50ohm trace

Dimension or Value

0.5 max

0.2 max

Unit Figure

inch

ohm

49.9

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace

L4 length, route as coupled stripline 100ohm differential trace

2 min to 16 max

1.8 min to 14.4 max

inch

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace

L4 length, route as coupled stripline 100ohm differential trace

0.25 to 14 max

0.225 min to 12.6 max

inch

Figure 1: Down Device Routing

L4'

L2'

L1'

HCSL Output Buffer

PCI Express

Down Device

REF_CLK Input

L3' L3

Figure 2: PCI Express Connector Routing

L4'

L2'

L1'

HCSL Output Buffer

PCI Express

Add-in Board

REF_CLK Input

L3' L3

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Alternative Termination for LVDS and other Common Differential Signals (figure 3)

Vdiff

0.45v

0.58

0.80

0.60

Vp-p

0.22v

0.28

0.40

0.3

Vcm

1.08

0.6

1.2

Note

150

78.7

174

100

137

none

140

100

ICS874003i-02 input compatible

Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Figure 3

R1a

R1b

L4'

L2'

L1'

R2a

R2b

HCSL Output Buffer

Down Device

REF_CLK Input

L3'

Cable Connected AC Coupled Application (figure 4)

Component

Value

Note

R5a, R5b

R6a, R6b

8.2K 5%

1K 5%

0.1 µF

Vcm

0.350 volts

Figure 4

3.3 Volts

R5a

R5b

R6b

L4'

R6a

PCIe Device

REF_CLK Input

IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41236

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Typical PCI-Express (HCSL) Waveform

700 mV

500 ps

t_OR

t_OF

0.52 V

0.175 V

0.52 V

0.175 V

Typical LVDS Waveform

1325 mV

1000 mV

500 ps

t_OR

t_OF

1250 mV

1150 mV

1250 mV

1150 mV

IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

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Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5V41236. These ratings are stress ratings

only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of

the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product

reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Item

Rating

Supply Voltage, VDD, VDDA

5.5V

All Inputs and Outputs

-0.5V to VDD+0.5V

0 to +70C

Ambient Operating Temperature (commercial)

Ambient Operating Temperature (industrial)

Storage Temperature

-40 to +85C

-65 to +150C

125C

Junction Temperature

Soldering Temperature

260C

ESD Protection (Input)

2000V min. (HBM)

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85C

Parameter

Symbol

Conditions

Min.

3.135

2.2

Typ.

Max.

Units

Supply Voltage

VDD

3.3

3.465

Input High Voltage

S0, S1, S2, OE, X1, PD#

0 < Vin < VDD

VDD + 0.3

Input Low Voltage

Input Leakage Current

VSS - 0.3

-5

0.8

A

k

Operating Supply Current

at100 MHz

R = 33R = 50, C = 2 pF

113

125

OE = Low

DDOE

Input Capacitance

Output Capacitance

X1, X2 Capacitance

Pin Inductance

Input pin capacitance

Output pin capacitance

OUT

INX

Output Impedance

Pull-up Resistance

CLK outputs

3.0

S0, S1, OE, S2, PD#

100

PUP

1. Single edge is monotonic when transitioning through region.

2. Inputs with pull-ups/-downs are not included.

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AC Electrical Characteristics - CLKOUT (A:D)

Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85C

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

MHz

Input Frequency

Output Frequency

HCSL termination

200

1,2

Output Max. Voltage

660

-300

250

863

-53

377

1150

MAX

1,2

Output Min. Voltage

MIN

1,2

Crossing Point Voltage

Absolute

550

140

125

1,2,4

Crossing Point Voltage

Variation over all edges

1,3

Jitter, Cycle-to-Cycle

Modulation Frequency

Spread spectrum

32.9

237

286

kHz

1,2

Rise Time

From 0.175V to 0.525V

From 0.525V to 0.175V

175

700

125

1,2

Fall Time

1,2

Rise/Fall Time Variation

Skew between Outputs

1,3

Duty Cycle

Output Enable Time

All outputs

100

1.8

Output Disable Time

All outputs

Stabilization Time

From power-up VDD = 3.3V

Settling period after spread change

STABLE

Spread Change Time

SPREAD

Test setup is R = 33R = 50 with C = 2pF, Rr = 475 (1%).

Measurement taken from a single-ended waveform.

Measurement taken from a differential waveform.

Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.

CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its

PD = low.

Electrical Characteristics - Differential Phase Jitter

T_A= Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%

SPEC

Max

PARAMETER

Symbol

t_jphaseG1

Conditions

PCIe Gen 1

Min

Typ

Units Notes

ps (p-p) 1,2,3

PCIe Gen 2

10kHz < f < 1.5MHz

PCIe Gen 2

t_jphaseG2Lo

t_jphaseG2High

t_jphaseG3

3.1

1,2,3

(RMS)

Jitter, Phase

2.3

0.7

1,2,3

(RMS)

1.5MHz < f < Nyquist (50MHz)

PCIe Gen 3

1,2,3

(RMS)

¹Guaranteed by design and characterization, not 100% tested in production.

²See http://www.pcisig.com for complete specs

³Applies to 100MHz, spread off and 0.5% down spread only.

IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

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Thermal Characteristics

Parameter

Symbol

Conditions

Min.

Typ.

Max. Units

C/W

Thermal Resistance Junction to Ambient



Still air



1 m/s air flow

3 m/s air flow

C/W



C/W

Thermal Resistance Junction to Case



C/W

Marking Diagram (5V41236PGG)

Marking Diagram (5V41236PGGI)

IDT5V412

36PGGI

YYWW$

IDT5V412

36PGG

YYWW$

Notes:

1.”**” denotes lot sequence; “YYWW” or “YWW” – Date code; “$” – mark code.

2. “G” after the two-letter package code designates RoHS compliant package.

3. “I” at the end of part number indicates industrial temperature range.

4. Bottom marking: country of origin if not USA.

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Package Outline Drawings

The package outline drawings are appended at the end of this document and are accessible from the link below. The

package information is the most current data available.

www.idt.com/document/psc/pgg20-package-outline-drawing-44-mm-body-065mm-pitch-tssop

Ordering Information

Part / Order Number

5V41236PGG

Marking

Shipping Packaging

Tubes

Package

20-TSSOP

Temperature

0 to +70C

see page 11

5V41236PGG8

5V41236PGGI

Tape and Reel

Tubes

0 to +70C

-40 to +85C

5V41236PGGI8

Tape and Reel

“G” after the two-letter package code are the Pb-Free configuration, RoHS compliant.

Revision History

Date

Description of Change

September 26, 2011

November 22, 2011

Initial release.

1. Changed title to “4 Output PCIe GEN1/2/3 Synthesizer”

2. Updated Differential Phase Jitter table.

February 4, 2014

June 6, 2016

Typo in VFQFPN T&R ordering information and VFQFPN device markings.

1. Updated “Operating Supply Current” parameters/values and Conditions in DC Electrical Characteristics

table.

2. Updated RPUP, VIH and VIL conditions.

February 13, 17

April 4, 2017

1. Updated Operating Supply Current [IDD] typical and maximum values.

2. Added typical values to AC Electrical Characteristics CLKOUT (A:D) table.

3. Updated typical values in Differential Phase Jitter table.

4. Updated 20-VFQFPN POD drawing.

1. Update “AC Electrical Characteristics - CLKOUT(A:D)” table values to latest PCIe specifications and

characterization data.

2. Updated package outline drawings.

3. Updated legal disclaimer.

September 18, 2019

Removed all references to 20-VFQFPN.

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4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

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